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hasvk: Use ELK compiler

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Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/27563>
This commit is contained in:
Caio Oliveira
2024-01-24 21:13:34 -08:00
committed by Marge Bot
parent 4968d1a925
commit 9294afe7fd
14 changed files with 202 additions and 216 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/intel/vulkan_hasvk/anv_blorp.c
+3 -3
View File
@@ -43,7 +43,7 @@ lookup_blorp_shader(struct blorp_batch *batch,
anv_shader_bin_unref(device, bin);
*kernel_out = bin->kernel.offset;
*(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
*(const struct elk_stage_prog_data **)prog_data_out = bin->prog_data;
return true;
}
@@ -79,7 +79,7 @@ upload_blorp_shader(struct blorp_batch *batch, uint32_t stage,
anv_shader_bin_unref(device, bin);
*kernel_out = bin->kernel.offset;
*(const struct brw_stage_prog_data **)prog_data_out = bin->prog_data;
*(const struct elk_stage_prog_data **)prog_data_out = bin->prog_data;
return true;
}
@@ -89,7 +89,7 @@ anv_device_init_blorp(struct anv_device *device)
{
const struct blorp_config config = {};
blorp_init_brw(&device->blorp, device, &device->isl_dev,
blorp_init_elk(&device->blorp, device, &device->isl_dev,
device->physical->compiler, &config);
device->blorp.lookup_shader = lookup_blorp_shader;
device->blorp.upload_shader = upload_blorp_shader;
src/intel/vulkan_hasvk/anv_cmd_buffer.c
+3 -3
View File
@@ -575,13 +575,13 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
struct anv_push_constants *data =
&cmd_buffer->state.compute.base.push_constants;
struct anv_compute_pipeline *pipeline = cmd_buffer->state.compute.pipeline;
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct elk_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct anv_push_range *range = &pipeline->cs->bind_map.push_ranges[0];
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
elk_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
const unsigned total_push_constants_size =
brw_cs_push_const_total_size(cs_prog_data, dispatch.threads);
elk_cs_push_const_total_size(cs_prog_data, dispatch.threads);
if (total_push_constants_size == 0)
return (struct anv_state) { .offset = 0 };
src/intel/vulkan_hasvk/anv_device.c
+4 -4
View File
@@ -830,7 +830,7 @@ anv_physical_device_init_disk_cache(struct anv_physical_device *device)
_mesa_sha1_format(timestamp, device->driver_build_sha1);
const uint64_t driver_flags =
brw_get_compiler_config_value(device->compiler);
elk_get_compiler_config_value(device->compiler);
device->vk.disk_cache = disk_cache_create(renderer, timestamp, driver_flags);
#endif
}
@@ -1187,7 +1187,7 @@ anv_physical_device_try_create(struct vk_instance *vk_instance,
device->always_flush_cache = INTEL_DEBUG(DEBUG_STALL) ||
driQueryOptionb(&instance->dri_options, "always_flush_cache");
device->compiler = brw_compiler_create(NULL, &device->info);
device->compiler = elk_compiler_create(NULL, &device->info);
if (device->compiler == NULL) {
result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
goto fail_base;
@@ -1602,7 +1602,7 @@ anv_get_physical_device_properties_1_1(struct anv_physical_device *pdevice,
p->deviceNodeMask = 0;
p->deviceLUIDValid = false;
p->subgroupSize = BRW_SUBGROUP_SIZE;
p->subgroupSize = ELK_SUBGROUP_SIZE;
VkShaderStageFlags scalar_stages = 0;
for (unsigned stage = 0; stage < MESA_SHADER_STAGES; stage++) {
if (pdevice->compiler->scalar_stage[stage])
@@ -2514,7 +2514,7 @@ VkResult anv_CreateDevice(
if (INTEL_DEBUG(DEBUG_BATCH)) {
const unsigned decode_flags = INTEL_BATCH_DECODE_DEFAULT_FLAGS;
intel_batch_decode_ctx_init_brw(&device->decoder_ctx,
intel_batch_decode_ctx_init_elk(&device->decoder_ctx,
&physical_device->compiler->isa,
&physical_device->info,
stderr, decode_flags, NULL,
src/intel/vulkan_hasvk/anv_nir.h
+8 -8
View File
@@ -38,10 +38,10 @@ bool anv_nir_lower_ycbcr_textures(nir_shader *shader,
static inline nir_address_format
anv_nir_ssbo_addr_format(const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags)
enum elk_robustness_flags robust_flags)
{
if (pdevice->has_a64_buffer_access) {
if (robust_flags & BRW_ROBUSTNESS_SSBO)
if (robust_flags & ELK_ROBUSTNESS_SSBO)
return nir_address_format_64bit_bounded_global;
else
return nir_address_format_64bit_global_32bit_offset;
@@ -52,10 +52,10 @@ anv_nir_ssbo_addr_format(const struct anv_physical_device *pdevice,
static inline nir_address_format
anv_nir_ubo_addr_format(const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags)
enum elk_robustness_flags robust_flags)
{
if (pdevice->has_a64_buffer_access) {
if (robust_flags & BRW_ROBUSTNESS_UBO)
if (robust_flags & ELK_ROBUSTNESS_UBO)
return nir_address_format_64bit_bounded_global;
else
return nir_address_format_64bit_global_32bit_offset;
@@ -68,18 +68,18 @@ bool anv_nir_lower_ubo_loads(nir_shader *shader);
void anv_nir_apply_pipeline_layout(nir_shader *shader,
const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags,
enum elk_robustness_flags robust_flags,
const struct anv_pipeline_layout *layout,
struct anv_pipeline_bind_map *map);
void anv_nir_compute_push_layout(nir_shader *nir,
const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags,
struct brw_stage_prog_data *prog_data,
enum elk_robustness_flags robust_flags,
struct elk_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map,
void *mem_ctx);
void anv_nir_validate_push_layout(struct brw_stage_prog_data *prog_data,
void anv_nir_validate_push_layout(struct elk_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map);
bool anv_nir_add_base_work_group_id(nir_shader *shader);
src/intel/vulkan_hasvk/anv_nir_apply_pipeline_layout.c
+4 -4
View File
@@ -23,7 +23,7 @@
#include "anv_nir.h"
#include "nir/nir_builder.h"
#include "compiler/brw_nir.h"
#include "compiler/elk/elk_nir.h"
#include "util/mesa-sha1.h"
#include "util/set.h"
@@ -914,8 +914,8 @@ lower_load_constant(nir_builder *b, nir_intrinsic_instr *intrin,
offset = nir_umin(b, offset, nir_imm_int(b, max_offset));
nir_def *const_data_base_addr = nir_pack_64_2x32_split(b,
nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW),
nir_load_reloc_const_intel(b, BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH));
nir_load_reloc_const_intel(b, ELK_SHADER_RELOC_CONST_DATA_ADDR_LOW),
nir_load_reloc_const_intel(b, ELK_SHADER_RELOC_CONST_DATA_ADDR_HIGH));
data = nir_load_global_constant(b, nir_iadd(b, const_data_base_addr,
nir_u2u64(b, offset)),
@@ -1232,7 +1232,7 @@ compare_binding_infos(const void *_a, const void *_b)
void
anv_nir_apply_pipeline_layout(nir_shader *shader,
const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags,
enum elk_robustness_flags robust_flags,
const struct anv_pipeline_layout *layout,
struct anv_pipeline_bind_map *map)
{
src/intel/vulkan_hasvk/anv_nir_compute_push_layout.c
+13 -15
View File
@@ -23,7 +23,7 @@
#include "anv_nir.h"
#include "nir_builder.h"
#include "compiler/brw_nir.h"
#include "compiler/elk/elk_nir.h"
#include "util/mesa-sha1.h"
#define sizeof_field(type, field) sizeof(((type *)0)->field)
@@ -31,12 +31,12 @@
void
anv_nir_compute_push_layout(nir_shader *nir,
const struct anv_physical_device *pdevice,
enum brw_robustness_flags robust_flags,
struct brw_stage_prog_data *prog_data,
enum elk_robustness_flags robust_flags,
struct elk_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map,
void *mem_ctx)
{
const struct brw_compiler *compiler = pdevice->compiler;
const struct elk_compiler *compiler = pdevice->compiler;
memset(map->push_ranges, 0, sizeof(map->push_ranges));
bool has_const_ubo = false;
@@ -74,10 +74,9 @@ anv_nir_compute_push_layout(nir_shader *nir,
const bool push_ubo_ranges =
pdevice->info.verx10 >= 75 &&
has_const_ubo && nir->info.stage != MESA_SHADER_COMPUTE &&
!brw_shader_stage_requires_bindless_resources(nir->info.stage);
has_const_ubo && nir->info.stage != MESA_SHADER_COMPUTE;
if (push_ubo_ranges && (robust_flags & BRW_ROBUSTNESS_UBO)) {
if (push_ubo_ranges && (robust_flags & ELK_ROBUSTNESS_UBO)) {
/* We can't on-the-fly adjust our push ranges because doing so would
* mess up the layout in the shader. When robustBufferAccess is
* enabled, we push a mask into the shader indicating which pushed
@@ -137,10 +136,9 @@ anv_nir_compute_push_layout(nir_shader *nir,
* messages. All the push constants are located after the
* RT_DISPATCH_GLOBALS. We just need to add the offset to
* the address right after RT_DISPATCH_GLOBALS (see
* brw_nir_lower_rt_intrinsics.c).
* elk_nir_lower_rt_intrinsics.c).
*/
unsigned base_offset =
brw_shader_stage_requires_bindless_resources(nir->info.stage) ? 0 : push_start;
unsigned base_offset = push_start;
intrin->intrinsic = nir_intrinsic_load_uniform;
nir_intrinsic_set_base(intrin,
nir_intrinsic_base(intrin) -
@@ -157,7 +155,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
}
if (push_ubo_ranges) {
brw_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
elk_nir_analyze_ubo_ranges(compiler, nir, prog_data->ubo_ranges);
/* The vec4 back-end pushes at most 32 regs while the scalar back-end
* pushes up to 64. This is primarily because the scalar back-end has a
@@ -180,7 +178,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
if (push_constant_range.length > 0)
map->push_ranges[n++] = push_constant_range;
if (robust_flags & BRW_ROBUSTNESS_UBO) {
if (robust_flags & ELK_ROBUSTNESS_UBO) {
const uint32_t push_reg_mask_offset =
offsetof(struct anv_push_constants, push_reg_mask[nir->info.stage]);
assert(push_reg_mask_offset >= push_start);
@@ -191,7 +189,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
unsigned range_start_reg = push_constant_range.length;
for (int i = 0; i < 4; i++) {
struct brw_ubo_range *ubo_range = &prog_data->ubo_ranges[i];
struct elk_ubo_range *ubo_range = &prog_data->ubo_ranges[i];
if (ubo_range->length == 0)
continue;
@@ -213,7 +211,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
/* We only bother to shader-zero pushed client UBOs */
if (binding->set < MAX_SETS &&
(robust_flags & BRW_ROBUSTNESS_UBO)) {
(robust_flags & ELK_ROBUSTNESS_UBO)) {
prog_data->zero_push_reg |= BITFIELD64_RANGE(range_start_reg,
ubo_range->length);
}
@@ -242,7 +240,7 @@ anv_nir_compute_push_layout(nir_shader *nir,
}
void
anv_nir_validate_push_layout(struct brw_stage_prog_data *prog_data,
anv_nir_validate_push_layout(struct elk_stage_prog_data *prog_data,
struct anv_pipeline_bind_map *map)
{
#ifndef NDEBUG
src/intel/vulkan_hasvk/anv_pipeline.c
+77 -87
View File
@@ -31,10 +31,10 @@
#include "util/os_time.h"
#include "common/intel_l3_config.h"
#include "common/intel_sample_positions.h"
#include "compiler/brw_disasm.h"
#include "compiler/elk/elk_disasm.h"
#include "anv_private.h"
#include "compiler/elk/elk_nir.h"
#include "compiler/intel_nir.h"
#include "compiler/brw_nir_rt.h"
#include "anv_nir.h"
#include "nir/nir_xfb_info.h"
#include "spirv/nir_spirv.h"
@@ -48,12 +48,12 @@
static nir_shader *
anv_shader_stage_to_nir(struct anv_device *device,
const VkPipelineShaderStageCreateInfo *stage_info,
enum brw_robustness_flags robust_flags,
enum elk_robustness_flags robust_flags,
void *mem_ctx)
{
const struct anv_physical_device *pdevice = device->physical;
const struct anv_instance *instance = pdevice->instance;
const struct brw_compiler *compiler = pdevice->compiler;
const struct elk_compiler *compiler = pdevice->compiler;
gl_shader_stage stage = vk_to_mesa_shader_stage(stage_info->stage);
const nir_shader_compiler_options *nir_options =
compiler->nir_options[stage];
@@ -157,9 +157,9 @@ anv_shader_stage_to_nir(struct anv_device *device,
/* Vulkan uses the separate-shader linking model */
nir->info.separate_shader = true;
struct brw_nir_compiler_opts opts = {};
struct elk_nir_compiler_opts opts = {};
brw_preprocess_nir(compiler, nir, &opts);
elk_preprocess_nir(compiler, nir, &opts);
return nir;
}
@@ -255,15 +255,15 @@ void anv_DestroyPipeline(
static void
populate_sampler_prog_key(const struct intel_device_info *devinfo,
struct brw_sampler_prog_key_data *key)
struct elk_sampler_prog_key_data *key)
{
/* XXX: Handle texture swizzle Pre-HSW */
}
static void
populate_base_prog_key(const struct anv_device *device,
enum brw_robustness_flags robust_flags,
struct brw_base_prog_key *key)
enum elk_robustness_flags robust_flags,
struct elk_base_prog_key *key)
{
key->robust_flags = robust_flags;
key->limit_trig_input_range =
@@ -274,8 +274,8 @@ populate_base_prog_key(const struct anv_device *device,
static void
populate_vs_prog_key(const struct anv_device *device,
enum brw_robustness_flags robust_flags,
struct brw_vs_prog_key *key)
enum elk_robustness_flags robust_flags,
struct elk_vs_prog_key *key)
{
memset(key, 0, sizeof(*key));
@@ -288,9 +288,9 @@ populate_vs_prog_key(const struct anv_device *device,
static void
populate_tcs_prog_key(const struct anv_device *device,
enum brw_robustness_flags robust_flags,
enum elk_robustness_flags robust_flags,
unsigned input_vertices,
struct brw_tcs_prog_key *key)
struct elk_tcs_prog_key *key)
{
memset(key, 0, sizeof(*key));
@@ -301,8 +301,8 @@ populate_tcs_prog_key(const struct anv_device *device,
static void
populate_tes_prog_key(const struct anv_device *device,
enum brw_robustness_flags robust_flags,
struct brw_tes_prog_key *key)
enum elk_robustness_flags robust_flags,
struct elk_tes_prog_key *key)
{
memset(key, 0, sizeof(*key));
@@ -312,7 +312,7 @@ populate_tes_prog_key(const struct anv_device *device,
static void
populate_gs_prog_key(const struct anv_device *device,
bool robust_flags,
struct brw_gs_prog_key *key)
struct elk_gs_prog_key *key)
{
memset(key, 0, sizeof(*key));
@@ -321,11 +321,11 @@ populate_gs_prog_key(const struct anv_device *device,
static void
populate_wm_prog_key(const struct anv_graphics_pipeline *pipeline,
enum brw_robustness_flags robust_flags,
enum elk_robustness_flags robust_flags,
const BITSET_WORD *dynamic,
const struct vk_multisample_state *ms,
const struct vk_render_pass_state *rp,
struct brw_wm_prog_key *key)
struct elk_wm_prog_key *key)
{
const struct anv_device *device = pipeline->base.device;
@@ -334,7 +334,7 @@ populate_wm_prog_key(const struct anv_graphics_pipeline *pipeline,
populate_base_prog_key(device, robust_flags, &key->base);
/* We set this to 0 here and set to the actual value before we call
* brw_compile_fs.
* elk_compile_fs.
*/
key->input_slots_valid = 0;
@@ -354,7 +354,7 @@ populate_wm_prog_key(const struct anv_graphics_pipeline *pipeline,
* when there is SampleMask output.
*/
key->alpha_to_coverage = ms != NULL && ms->alpha_to_coverage_enable ?
BRW_ALWAYS : BRW_NEVER;
ELK_ALWAYS : ELK_NEVER;
/* Vulkan doesn't support fixed-function alpha test */
key->alpha_test_replicate_alpha = false;
@@ -367,8 +367,8 @@ populate_wm_prog_key(const struct anv_graphics_pipeline *pipeline,
key->persample_interp =
(ms->sample_shading_enable &&
(ms->min_sample_shading * ms->rasterization_samples) > 1) ?
BRW_ALWAYS : BRW_NEVER;
key->multisample_fbo = BRW_ALWAYS;
ELK_ALWAYS : ELK_NEVER;
key->multisample_fbo = ELK_ALWAYS;
}
if (device->physical->instance->sample_mask_out_opengl_behaviour)
@@ -378,18 +378,8 @@ populate_wm_prog_key(const struct anv_graphics_pipeline *pipeline,
static void
populate_cs_prog_key(const struct anv_device *device,
enum brw_robustness_flags robust_flags,
struct brw_cs_prog_key *key)
{
memset(key, 0, sizeof(*key));
populate_base_prog_key(device, robust_flags, &key->base);
}
static void
populate_bs_prog_key(const struct anv_device *device,
enum brw_robustness_flags robust_flags,
struct brw_bs_prog_key *key)
enum elk_robustness_flags robust_flags,
struct elk_cs_prog_key *key)
{
memset(key, 0, sizeof(*key));
@@ -403,7 +393,7 @@ struct anv_pipeline_stage {
unsigned char shader_sha1[20];
union brw_any_prog_key key;
union elk_any_prog_key key;
struct {
gl_shader_stage stage;
@@ -416,10 +406,10 @@ struct anv_pipeline_stage {
struct anv_pipeline_binding sampler_to_descriptor[256];
struct anv_pipeline_bind_map bind_map;
union brw_any_prog_data prog_data;
union elk_any_prog_data prog_data;
uint32_t num_stats;
struct brw_compile_stats stats[3];
struct elk_compile_stats stats[3];
char *disasm[3];
VkPipelineCreationFeedback feedback;
@@ -448,7 +438,7 @@ anv_pipeline_hash_graphics(struct anv_graphics_pipeline *pipeline,
if (stages[s].info) {
_mesa_sha1_update(&ctx, stages[s].shader_sha1,
sizeof(stages[s].shader_sha1));
_mesa_sha1_update(&ctx, &stages[s].key, brw_prog_key_size(s));
_mesa_sha1_update(&ctx, &stages[s].key, elk_prog_key_size(s));
}
}
@@ -488,7 +478,7 @@ anv_pipeline_stage_get_nir(struct anv_pipeline *pipeline,
void *mem_ctx,
struct anv_pipeline_stage *stage)
{
const struct brw_compiler *compiler =
const struct elk_compiler *compiler =
pipeline->device->physical->compiler;
const nir_shader_compiler_options *nir_options =
compiler->nir_options[stage->stage];
@@ -532,9 +522,9 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
struct anv_pipeline_layout *layout)
{
const struct anv_physical_device *pdevice = pipeline->device->physical;
const struct brw_compiler *compiler = pdevice->compiler;
const struct elk_compiler *compiler = pdevice->compiler;
struct brw_stage_prog_data *prog_data = &stage->prog_data.base;
struct elk_stage_prog_data *prog_data = &stage->prog_data.base;
nir_shader *nir = stage->nir;
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
@@ -556,8 +546,8 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
NIR_PASS(_, nir, brw_nir_lower_storage_image,
&(struct brw_nir_lower_storage_image_opts) {
NIR_PASS(_, nir, elk_nir_lower_storage_image,
&(struct elk_nir_lower_storage_image_opts) {
.devinfo = compiler->devinfo,
.lower_loads = true,
.lower_stores = true,
@@ -632,7 +622,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
const unsigned chunk_size = 16;
const unsigned shared_size = ALIGN(nir->info.shared_size, chunk_size);
assert(shared_size <=
intel_calculate_slm_size(compiler->devinfo->ver, nir->info.shared_size));
elk_calculate_slm_size(compiler->devinfo->ver, nir->info.shared_size));
NIR_PASS(_, nir, nir_zero_initialize_shared_memory,
shared_size, chunk_size);
@@ -640,7 +630,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
}
if (gl_shader_stage_is_compute(nir->info.stage)) {
NIR_PASS(_, nir, brw_nir_lower_cs_intrinsics, compiler->devinfo,
NIR_PASS(_, nir, elk_nir_lower_cs_intrinsics, compiler->devinfo,
&stage->prog_data.cs);
}
@@ -648,16 +638,16 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
}
static void
anv_pipeline_link_vs(const struct brw_compiler *compiler,
anv_pipeline_link_vs(const struct elk_compiler *compiler,
struct anv_pipeline_stage *vs_stage,
struct anv_pipeline_stage *next_stage)
{
if (next_stage)
brw_nir_link_shaders(compiler, vs_stage->nir, next_stage->nir);
elk_nir_link_shaders(compiler, vs_stage->nir, next_stage->nir);
}
static void
anv_pipeline_compile_vs(const struct brw_compiler *compiler,
anv_pipeline_compile_vs(const struct elk_compiler *compiler,
void *mem_ctx,
struct anv_graphics_pipeline *pipeline,
struct anv_pipeline_stage *vs_stage)
@@ -672,7 +662,7 @@ anv_pipeline_compile_vs(const struct brw_compiler *compiler,
/* Only position is allowed to be per-view */
assert(!(vs_stage->nir->info.per_view_outputs & ~VARYING_BIT_POS));
brw_compute_vue_map(compiler->devinfo,
elk_compute_vue_map(compiler->devinfo,
&vs_stage->prog_data.vs.base.vue_map,
vs_stage->nir->info.outputs_written,
vs_stage->nir->info.separate_shader,
@@ -680,7 +670,7 @@ anv_pipeline_compile_vs(const struct brw_compiler *compiler,
vs_stage->num_stats = 1;
struct brw_compile_vs_params params = {
struct elk_compile_vs_params params = {
.base = {
.nir = vs_stage->nir,
.stats = vs_stage->stats,
@@ -691,7 +681,7 @@ anv_pipeline_compile_vs(const struct brw_compiler *compiler,
.prog_data = &vs_stage->prog_data.vs,
};
vs_stage->code = brw_compile_vs(compiler, &params);
vs_stage->code = elk_compile_vs(compiler, &params);
}
static void
@@ -734,13 +724,13 @@ merge_tess_info(struct shader_info *tes_info,
}
static void
anv_pipeline_link_tcs(const struct brw_compiler *compiler,
anv_pipeline_link_tcs(const struct elk_compiler *compiler,
struct anv_pipeline_stage *tcs_stage,
struct anv_pipeline_stage *tes_stage)
{
assert(tes_stage && tes_stage->stage == MESA_SHADER_TESS_EVAL);
brw_nir_link_shaders(compiler, tcs_stage->nir, tes_stage->nir);
elk_nir_link_shaders(compiler, tcs_stage->nir, tes_stage->nir);
nir_lower_patch_vertices(tes_stage->nir,
tcs_stage->nir->info.tess.tcs_vertices_out,
@@ -762,7 +752,7 @@ anv_pipeline_link_tcs(const struct brw_compiler *compiler,
}
static void
anv_pipeline_compile_tcs(const struct brw_compiler *compiler,
anv_pipeline_compile_tcs(const struct elk_compiler *compiler,
void *mem_ctx,
struct anv_device *device,
struct anv_pipeline_stage *tcs_stage,
@@ -775,7 +765,7 @@ anv_pipeline_compile_tcs(const struct brw_compiler *compiler,
tcs_stage->num_stats = 1;
struct brw_compile_tcs_params params = {
struct elk_compile_tcs_params params = {
.base = {
.nir = tcs_stage->nir,
.stats = tcs_stage->stats,
@@ -786,20 +776,20 @@ anv_pipeline_compile_tcs(const struct brw_compiler *compiler,
.prog_data = &tcs_stage->prog_data.tcs,
};
tcs_stage->code = brw_compile_tcs(compiler, &params);
tcs_stage->code = elk_compile_tcs(compiler, &params);
}
static void
anv_pipeline_link_tes(const struct brw_compiler *compiler,
anv_pipeline_link_tes(const struct elk_compiler *compiler,
struct anv_pipeline_stage *tes_stage,
struct anv_pipeline_stage *next_stage)
{
if (next_stage)
brw_nir_link_shaders(compiler, tes_stage->nir, next_stage->nir);
elk_nir_link_shaders(compiler, tes_stage->nir, next_stage->nir);
}
static void
anv_pipeline_compile_tes(const struct brw_compiler *compiler,
anv_pipeline_compile_tes(const struct elk_compiler *compiler,
void *mem_ctx,
struct anv_device *device,
struct anv_pipeline_stage *tes_stage,
@@ -812,7 +802,7 @@ anv_pipeline_compile_tes(const struct brw_compiler *compiler,
tes_stage->num_stats = 1;
struct brw_compile_tes_params params = {
struct elk_compile_tes_params params = {
.base = {
.nir = tes_stage->nir,
.stats = tes_stage->stats,
@@ -824,33 +814,33 @@ anv_pipeline_compile_tes(const struct brw_compiler *compiler,
.input_vue_map = &tcs_stage->prog_data.tcs.base.vue_map,
};
tes_stage->code = brw_compile_tes(compiler, &params);
tes_stage->code = elk_compile_tes(compiler, &params);
}
static void
anv_pipeline_link_gs(const struct brw_compiler *compiler,
anv_pipeline_link_gs(const struct elk_compiler *compiler,
struct anv_pipeline_stage *gs_stage,
struct anv_pipeline_stage *next_stage)
{
if (next_stage)
brw_nir_link_shaders(compiler, gs_stage->nir, next_stage->nir);
elk_nir_link_shaders(compiler, gs_stage->nir, next_stage->nir);
}
static void
anv_pipeline_compile_gs(const struct brw_compiler *compiler,
anv_pipeline_compile_gs(const struct elk_compiler *compiler,
void *mem_ctx,
struct anv_device *device,
struct anv_pipeline_stage *gs_stage,
struct anv_pipeline_stage *prev_stage)
{
brw_compute_vue_map(compiler->devinfo,
elk_compute_vue_map(compiler->devinfo,
&gs_stage->prog_data.gs.base.vue_map,
gs_stage->nir->info.outputs_written,
gs_stage->nir->info.separate_shader, 1);
gs_stage->num_stats = 1;
struct brw_compile_gs_params params = {
struct elk_compile_gs_params params = {
.base = {
.nir = gs_stage->nir,
.stats = gs_stage->stats,
@@ -861,11 +851,11 @@ anv_pipeline_compile_gs(const struct brw_compiler *compiler,
.prog_data = &gs_stage->prog_data.gs,
};
gs_stage->code = brw_compile_gs(compiler, &params);
gs_stage->code = elk_compile_gs(compiler, &params);
}
static void
anv_pipeline_link_fs(const struct brw_compiler *compiler,
anv_pipeline_link_fs(const struct elk_compiler *compiler,
struct anv_pipeline_stage *stage,
const struct vk_render_pass_state *rp)
{
@@ -927,7 +917,7 @@ anv_pipeline_link_fs(const struct brw_compiler *compiler,
}
static void
anv_pipeline_compile_fs(const struct brw_compiler *compiler,
anv_pipeline_compile_fs(const struct elk_compiler *compiler,
void *mem_ctx,
struct anv_device *device,
struct anv_pipeline_stage *fs_stage,
@@ -938,7 +928,7 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler,
*/
assert(prev_stage);
struct brw_compile_fs_params params = {
struct elk_compile_fs_params params = {
.base = {
.nir = fs_stage->nir,
.stats = fs_stage->stats,
@@ -954,7 +944,7 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler,
fs_stage->key.wm.input_slots_valid =
prev_stage->prog_data.vue.vue_map.slots_valid;
fs_stage->code = brw_compile_fs(compiler, &params);
fs_stage->code = elk_compile_fs(compiler, &params);
fs_stage->num_stats = (uint32_t)fs_stage->prog_data.wm.dispatch_8 +
(uint32_t)fs_stage->prog_data.wm.dispatch_16 +
@@ -964,7 +954,7 @@ anv_pipeline_compile_fs(const struct brw_compiler *compiler,
static void
anv_pipeline_add_executable(struct anv_pipeline *pipeline,
struct anv_pipeline_stage *stage,
struct brw_compile_stats *stats,
struct elk_compile_stats *stats,
uint32_t code_offset)
{
char *nir = NULL;
@@ -1035,7 +1025,7 @@ anv_pipeline_add_executable(struct anv_pipeline *pipeline,
/* Creating this is far cheaper than it looks. It's perfectly fine to
* do it for every binary.
*/
brw_disassemble_with_errors(&pipeline->device->physical->compiler->isa,
elk_disassemble_with_errors(&pipeline->device->physical->compiler->isa,
stage->code, code_offset, stream);
fclose(stream);
@@ -1068,9 +1058,9 @@ anv_pipeline_add_executables(struct anv_pipeline *pipeline,
* the anv_pipeline_stage may not be fully populated if we successfully
* looked up the shader in a cache.
*/
const struct brw_wm_prog_data *wm_prog_data =
(const struct brw_wm_prog_data *)bin->prog_data;
struct brw_compile_stats *stats = bin->stats;
const struct elk_wm_prog_data *wm_prog_data =
(const struct elk_wm_prog_data *)bin->prog_data;
struct elk_compile_stats *stats = bin->stats;
if (wm_prog_data->dispatch_8) {
anv_pipeline_add_executable(pipeline, stage, stats++, 0);
@@ -1090,11 +1080,11 @@ anv_pipeline_add_executables(struct anv_pipeline *pipeline,
}
}
static enum brw_robustness_flags
static enum elk_robustness_flags
anv_device_get_robust_flags(const struct anv_device *device)
{
return device->robust_buffer_access ?
(BRW_ROBUSTNESS_UBO | BRW_ROBUSTNESS_SSBO) : 0;
(ELK_ROBUSTNESS_UBO | ELK_ROBUSTNESS_SSBO) : 0;
}
static void
@@ -1111,7 +1101,7 @@ anv_graphics_pipeline_init_keys(struct anv_graphics_pipeline *pipeline,
vk_pipeline_hash_shader_stage(stages[s].info, NULL, stages[s].shader_sha1);
const struct anv_device *device = pipeline->base.device;
enum brw_robustness_flags robust_flags = anv_device_get_robust_flags(device);
enum elk_robustness_flags robust_flags = anv_device_get_robust_flags(device);
switch (stages[s].stage) {
case MESA_SHADER_VERTEX:
populate_vs_prog_key(device,
@@ -1284,7 +1274,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_pipeline *pipeline,
};
int64_t pipeline_start = os_time_get_nano();
const struct brw_compiler *compiler = pipeline->base.device->physical->compiler;
const struct elk_compiler *compiler = pipeline->base.device->physical->compiler;
struct anv_pipeline_stage stages[ANV_GRAPHICS_SHADER_STAGE_COUNT] = {};
for (uint32_t i = 0; i < info->stageCount; i++) {
gl_shader_stage stage = vk_to_mesa_shader_stage(info->pStages[i].stage);
@@ -1433,7 +1423,7 @@ anv_graphics_pipeline_compile(struct anv_graphics_pipeline *pipeline,
stages[s].code,
stages[s].prog_data.base.program_size,
&stages[s].prog_data.base,
brw_prog_data_size(s),
elk_prog_data_size(s),
stages[s].stats, stages[s].num_stats,
stages[s].nir->xfb_info,
&stages[s].bind_map);
@@ -1499,7 +1489,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
int64_t pipeline_start = os_time_get_nano();
struct anv_device *device = pipeline->base.device;
const struct brw_compiler *compiler = device->physical->compiler;
const struct elk_compiler *compiler = device->physical->compiler;
struct anv_pipeline_stage stage = {
.stage = MESA_SHADER_COMPUTE,
@@ -1573,7 +1563,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
stage.nir->info.uses_wide_subgroup_intrinsics &&
stage.nir->info.subgroup_size == SUBGROUP_SIZE_API_CONSTANT &&
local_size &&
local_size % BRW_SUBGROUP_SIZE == 0)
local_size % ELK_SUBGROUP_SIZE == 0)
stage.nir->info.subgroup_size = SUBGROUP_SIZE_FULL_SUBGROUPS;
/* If the client requests that we dispatch full subgroups but doesn't
@@ -1585,11 +1575,11 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
if (stage.nir->info.subgroup_size == SUBGROUP_SIZE_FULL_SUBGROUPS)
stage.nir->info.subgroup_size =
device->physical->instance->assume_full_subgroups != 0 ?
device->physical->instance->assume_full_subgroups : BRW_SUBGROUP_SIZE;
device->physical->instance->assume_full_subgroups : ELK_SUBGROUP_SIZE;
stage.num_stats = 1;
struct brw_compile_cs_params params = {
struct elk_compile_cs_params params = {
.base = {
.nir = stage.nir,
.stats = stage.stats,
@@ -1600,7 +1590,7 @@ anv_pipeline_compile_cs(struct anv_compute_pipeline *pipeline,
.prog_data = &stage.prog_data.cs,
};
stage.code = brw_compile_cs(compiler, &params);
stage.code = elk_compile_cs(compiler, &params);
if (stage.code == NULL) {
ralloc_free(mem_ctx);
return vk_error(pipeline, VK_ERROR_OUT_OF_HOST_MEMORY);
@@ -2002,7 +1992,7 @@ VkResult anv_GetPipelineExecutableStatisticsKHR(
const struct anv_pipeline_executable *exe =
anv_pipeline_get_executable(pipeline, pExecutableInfo->executableIndex);
const struct brw_stage_prog_data *prog_data;
const struct elk_stage_prog_data *prog_data;
switch (pipeline->type) {
case ANV_PIPELINE_GRAPHICS: {
prog_data = anv_pipeline_to_graphics(pipeline)->shaders[exe->stage]->prog_data;
src/intel/vulkan_hasvk/anv_pipeline_cache.c
+16 -16
View File
@@ -70,18 +70,18 @@ anv_shader_bin_create(struct anv_device *device,
gl_shader_stage stage,
const void *key_data, uint32_t key_size,
const void *kernel_data, uint32_t kernel_size,
const struct brw_stage_prog_data *prog_data_in,
const struct elk_stage_prog_data *prog_data_in,
uint32_t prog_data_size,
const struct brw_compile_stats *stats, uint32_t num_stats,
const struct elk_compile_stats *stats, uint32_t num_stats,
const nir_xfb_info *xfb_info_in,
const struct anv_pipeline_bind_map *bind_map)
{
VK_MULTIALLOC(ma);
VK_MULTIALLOC_DECL(&ma, struct anv_shader_bin, shader, 1);
VK_MULTIALLOC_DECL_SIZE(&ma, void, obj_key_data, key_size);
VK_MULTIALLOC_DECL_SIZE(&ma, struct brw_stage_prog_data, prog_data,
VK_MULTIALLOC_DECL_SIZE(&ma, struct elk_stage_prog_data, prog_data,
prog_data_size);
VK_MULTIALLOC_DECL(&ma, struct brw_shader_reloc, prog_data_relocs,
VK_MULTIALLOC_DECL(&ma, struct elk_shader_reloc, prog_data_relocs,
prog_data_in->num_relocs);
VK_MULTIALLOC_DECL(&ma, uint32_t, prog_data_param, prog_data_in->nr_params);
@@ -114,20 +114,20 @@ anv_shader_bin_create(struct anv_device *device,
prog_data_in->const_data_offset;
int rv_count = 0;
struct brw_shader_reloc_value reloc_values[5];
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW,
struct elk_shader_reloc_value reloc_values[5];
reloc_values[rv_count++] = (struct elk_shader_reloc_value) {
.id = ELK_SHADER_RELOC_CONST_DATA_ADDR_LOW,
.value = shader_data_addr,
};
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH,
reloc_values[rv_count++] = (struct elk_shader_reloc_value) {
.id = ELK_SHADER_RELOC_CONST_DATA_ADDR_HIGH,
.value = shader_data_addr >> 32,
};
reloc_values[rv_count++] = (struct brw_shader_reloc_value) {
.id = BRW_SHADER_RELOC_SHADER_START_OFFSET,
reloc_values[rv_count++] = (struct elk_shader_reloc_value) {
.id = ELK_SHADER_RELOC_SHADER_START_OFFSET,
.value = shader->kernel.offset,
};
brw_write_shader_relocs(&device->physical->compiler->isa,
elk_write_shader_relocs(&device->physical->compiler->isa,
shader->kernel.map, prog_data_in,
reloc_values, rv_count);
@@ -234,7 +234,7 @@ anv_shader_bin_deserialize(struct vk_pipeline_cache *cache,
if (blob->overrun)
return NULL;
union brw_any_prog_data prog_data;
union elk_any_prog_data prog_data;
memcpy(&prog_data, prog_data_bytes,
MIN2(sizeof(prog_data), prog_data_size));
prog_data.base.relocs =
@@ -242,7 +242,7 @@ anv_shader_bin_deserialize(struct vk_pipeline_cache *cache,
sizeof(prog_data.base.relocs[0]));
uint32_t num_stats = blob_read_uint32(blob);
const struct brw_compile_stats *stats =
const struct elk_compile_stats *stats =
blob_read_bytes(blob, num_stats * sizeof(stats[0]));
const nir_xfb_info *xfb_info = NULL;
@@ -309,9 +309,9 @@ anv_device_upload_kernel(struct anv_device *device,
gl_shader_stage stage,
const void *key_data, uint32_t key_size,
const void *kernel_data, uint32_t kernel_size,
const struct brw_stage_prog_data *prog_data,
const struct elk_stage_prog_data *prog_data,
uint32_t prog_data_size,
const struct brw_compile_stats *stats,
const struct elk_compile_stats *stats,
uint32_t num_stats,
const nir_xfb_info *xfb_info,
const struct anv_pipeline_bind_map *bind_map)
src/intel/vulkan_hasvk/anv_private.h
+14 -15
View File
@@ -50,8 +50,7 @@
#include "decoder/intel_decoder.h"
#include "dev/intel_device_info.h"
#include "blorp/blorp.h"
#include "compiler/brw_compiler.h"
#include "compiler/brw_rt.h"
#include "compiler/elk/elk_compiler.h"
#include "ds/intel_driver_ds.h"
#include "util/bitset.h"
#include "util/bitscan.h"
@@ -857,7 +856,7 @@ struct anv_physical_device {
char path[20];
struct intel_device_info info;
bool supports_48bit_addresses;
struct brw_compiler * compiler;
struct elk_compiler * compiler;
struct isl_device isl_dev;
struct intel_perf_config * perf;
/* True if hardware support is incomplete/alpha */
@@ -986,9 +985,9 @@ anv_device_upload_kernel(struct anv_device *device,
gl_shader_stage stage,
const void *key_data, uint32_t key_size,
const void *kernel_data, uint32_t kernel_size,
const struct brw_stage_prog_data *prog_data,
const struct elk_stage_prog_data *prog_data,
uint32_t prog_data_size,
const struct brw_compile_stats *stats,
const struct elk_compile_stats *stats,
uint32_t num_stats,
const struct nir_xfb_info *xfb_info,
const struct anv_pipeline_bind_map *bind_map);
@@ -2772,10 +2771,10 @@ struct anv_shader_bin {
struct anv_state kernel;
uint32_t kernel_size;
const struct brw_stage_prog_data *prog_data;
const struct elk_stage_prog_data *prog_data;
uint32_t prog_data_size;
struct brw_compile_stats stats[3];
struct elk_compile_stats stats[3];
uint32_t num_stats;
struct nir_xfb_info *xfb_info;
@@ -2788,9 +2787,9 @@ anv_shader_bin_create(struct anv_device *device,
gl_shader_stage stage,
const void *key, uint32_t key_size,
const void *kernel, uint32_t kernel_size,
const struct brw_stage_prog_data *prog_data,
const struct elk_stage_prog_data *prog_data,
uint32_t prog_data_size,
const struct brw_compile_stats *stats, uint32_t num_stats,
const struct elk_compile_stats *stats, uint32_t num_stats,
const struct nir_xfb_info *xfb_info,
const struct anv_pipeline_bind_map *bind_map);
@@ -2809,7 +2808,7 @@ anv_shader_bin_unref(struct anv_device *device, struct anv_shader_bin *shader)
struct anv_pipeline_executable {
gl_shader_stage stage;
struct brw_compile_stats stats;
struct elk_compile_stats stats;
char *nir;
char *disasm;
@@ -2968,11 +2967,11 @@ anv_cmd_graphic_state_update_has_uint_rt(struct anv_cmd_graphics_state *state)
}
#define ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(prefix, stage) \
static inline const struct brw_##prefix##_prog_data * \
static inline const struct elk_##prefix##_prog_data * \
get_##prefix##_prog_data(const struct anv_graphics_pipeline *pipeline) \
{ \
if (anv_pipeline_has_stage(pipeline, stage)) { \
return (const struct brw_##prefix##_prog_data *) \
return (const struct elk_##prefix##_prog_data *) \
pipeline->shaders[stage]->prog_data; \
} else { \
return NULL; \
@@ -2985,14 +2984,14 @@ ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(tes, MESA_SHADER_TESS_EVAL)
ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(gs, MESA_SHADER_GEOMETRY)
ANV_DECL_GET_GRAPHICS_PROG_DATA_FUNC(wm, MESA_SHADER_FRAGMENT)
static inline const struct brw_cs_prog_data *
static inline const struct elk_cs_prog_data *
get_cs_prog_data(const struct anv_compute_pipeline *pipeline)
{
assert(pipeline->cs);
return (const struct brw_cs_prog_data *) pipeline->cs->prog_data;
return (const struct elk_cs_prog_data *) pipeline->cs->prog_data;
}
static inline const struct brw_vue_prog_data *
static inline const struct elk_vue_prog_data *
anv_pipeline_get_last_vue_prog_data(const struct anv_graphics_pipeline *pipeline)
{
if (anv_pipeline_has_stage(pipeline, MESA_SHADER_GEOMETRY))
src/intel/vulkan_hasvk/genX_blorp_exec.c
+1 -1
View File
@@ -32,7 +32,7 @@
#undef __gen_combine_address
#include "common/intel_l3_config.h"
#include "blorp/blorp_genX_exec.h"
#include "blorp/blorp_genX_exec_elk.h"
#include "ds/intel_tracepoints.h"
src/intel/vulkan_hasvk/genX_cmd_buffer.c
+18 -19
View File
@@ -34,9 +34,8 @@
#include "common/intel_l3_config.h"
#include "genxml/gen_macros.h"
#include "genxml/genX_pack.h"
#include "genxml/genX_rt_pack.h"
#include "common/intel_guardband.h"
#include "compiler/brw_prim.h"
#include "compiler/elk/elk_prim.h"
#include "nir/nir_xfb_info.h"
@@ -2888,7 +2887,7 @@ cmd_buffer_emit_clip(struct anv_cmd_buffer *cmd_buffer)
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
if (anv_pipeline_is_primitive(pipeline)) {
const struct brw_vue_prog_data *last =
const struct elk_vue_prog_data *last =
anv_pipeline_get_last_vue_prog_data(pipeline);
if (last->vue_map.slots_valid & VARYING_BIT_VIEWPORT) {
clip.MaximumVPIndex = dyn->vp.viewport_count > 0 ?
@@ -3481,7 +3480,7 @@ update_dirty_vbs_for_gfx8_vb_flush(struct anv_cmd_buffer *cmd_buffer,
uint32_t access_type)
{
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
uint64_t vb_used = pipeline->vb_used;
if (vs_prog_data->uses_firstvertex ||
@@ -3497,7 +3496,7 @@ update_dirty_vbs_for_gfx8_vb_flush(struct anv_cmd_buffer *cmd_buffer,
ALWAYS_INLINE static void
cmd_buffer_emit_vertex_constants_and_flush(struct anv_cmd_buffer *cmd_buffer,
const struct brw_vs_prog_data *vs_prog_data,
const struct elk_vs_prog_data *vs_prog_data,
uint32_t base_vertex,
uint32_t base_instance,
uint32_t draw_id,
@@ -3529,7 +3528,7 @@ void genX(CmdDraw)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -3583,7 +3582,7 @@ void genX(CmdDrawMultiEXT)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -3634,7 +3633,7 @@ void genX(CmdDrawIndexed)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -3690,7 +3689,7 @@ void genX(CmdDrawMultiIndexedEXT)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -3810,7 +3809,7 @@ void genX(CmdDrawIndirectByteCountEXT)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, counter_buffer, counterBuffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
/* firstVertex is always zero for this draw function */
const uint32_t firstVertex = 0;
@@ -3921,7 +3920,7 @@ void genX(CmdDrawIndirect)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -3978,7 +3977,7 @@ void genX(CmdDrawIndexedIndirect)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
struct anv_graphics_pipeline *pipeline = cmd_buffer->state.gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -4145,7 +4144,7 @@ void genX(CmdDrawIndirectCount)(
ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
struct anv_cmd_state *cmd_state = &cmd_buffer->state;
struct anv_graphics_pipeline *pipeline = cmd_state->gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -4213,7 +4212,7 @@ void genX(CmdDrawIndexedIndirectCount)(
ANV_FROM_HANDLE(anv_buffer, count_buffer, _countBuffer);
struct anv_cmd_state *cmd_state = &cmd_buffer->state;
struct anv_graphics_pipeline *pipeline = cmd_state->gfx.pipeline;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
if (anv_batch_has_error(&cmd_buffer->batch))
return;
@@ -4507,7 +4506,7 @@ anv_cmd_buffer_push_base_group_id(struct anv_cmd_buffer *cmd_buffer,
static inline void
emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer,
const struct anv_compute_pipeline *pipeline, bool indirect,
const struct brw_cs_prog_data *prog_data,
const struct elk_cs_prog_data *prog_data,
uint32_t groupCountX, uint32_t groupCountY,
uint32_t groupCountZ)
{
@@ -4516,7 +4515,7 @@ emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer,
const struct intel_device_info *devinfo = pipeline->base.device->info;
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, prog_data, NULL);
elk_cs_get_dispatch_info(devinfo, prog_data, NULL);
anv_batch_emit(&cmd_buffer->batch, GENX(GPGPU_WALKER), ggw) {
ggw.IndirectParameterEnable = indirect;
@@ -4538,7 +4537,7 @@ emit_gpgpu_walker(struct anv_cmd_buffer *cmd_buffer,
static inline void
emit_cs_walker(struct anv_cmd_buffer *cmd_buffer,
const struct anv_compute_pipeline *pipeline, bool indirect,
const struct brw_cs_prog_data *prog_data,
const struct elk_cs_prog_data *prog_data,
uint32_t groupCountX, uint32_t groupCountY,
uint32_t groupCountZ)
{
@@ -4557,7 +4556,7 @@ void genX(CmdDispatchBase)(
{
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
struct anv_compute_pipeline *pipeline = cmd_buffer->state.compute.pipeline;
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
const struct elk_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
anv_cmd_buffer_push_base_group_id(cmd_buffer, baseGroupX,
baseGroupY, baseGroupZ);
@@ -4614,7 +4613,7 @@ void genX(CmdDispatchIndirect)(
ANV_FROM_HANDLE(anv_cmd_buffer, cmd_buffer, commandBuffer);
ANV_FROM_HANDLE(anv_buffer, buffer, _buffer);
struct anv_compute_pipeline *pipeline = cmd_buffer->state.compute.pipeline;
const struct brw_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
const struct elk_cs_prog_data *prog_data = get_cs_prog_data(pipeline);
struct anv_address addr = anv_address_add(buffer->address, offset);
UNUSED struct anv_batch *batch = &cmd_buffer->batch;
src/intel/vulkan_hasvk/genX_pipeline.c
+33 -33
View File
@@ -27,7 +27,7 @@
#include "genxml/genX_pack.h"
#include "genxml/genX_rt_pack.h"
#include "common/intel_genX_state.h"
#include "common/intel_genX_state_elk.h"
#include "common/intel_l3_config.h"
#include "common/intel_sample_positions.h"
#include "nir/nir_xfb_info.h"
@@ -92,7 +92,7 @@ static void
emit_vertex_input(struct anv_graphics_pipeline *pipeline,
const struct vk_vertex_input_state *vi)
{
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
/* Pull inputs_read out of the VS prog data */
const uint64_t inputs_read = vs_prog_data->inputs_read;
@@ -319,9 +319,9 @@ emit_urb_setup(struct anv_graphics_pipeline *pipeline,
{
unsigned entry_size[4];
for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
const struct brw_vue_prog_data *prog_data =
const struct elk_vue_prog_data *prog_data =
!anv_pipeline_has_stage(pipeline, i) ? NULL :
(const struct brw_vue_prog_data *) pipeline->shaders[i]->prog_data;
(const struct elk_vue_prog_data *) pipeline->shaders[i]->prog_data;
entry_size[i] = prog_data ? prog_data->urb_entry_size : 1;
}
@@ -335,7 +335,7 @@ emit_urb_setup(struct anv_graphics_pipeline *pipeline,
static void
emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_SBE), sbe);
@@ -365,7 +365,7 @@ emit_3dstate_sbe(struct anv_graphics_pipeline *pipeline)
const struct intel_vue_map *fs_input_map =
&anv_pipeline_get_last_vue_prog_data(pipeline)->vue_map;
int first_slot = brw_compute_first_urb_slot_required(wm_prog_data->inputs,
int first_slot = elk_compute_first_urb_slot_required(wm_prog_data->inputs,
fs_input_map);
assert(first_slot % 2 == 0);
unsigned urb_entry_read_offset = first_slot / 2;
@@ -643,7 +643,7 @@ emit_rs_state(struct anv_graphics_pipeline *pipeline,
#endif
bool point_from_shader;
const struct brw_vue_prog_data *last_vue_prog_data =
const struct elk_vue_prog_data *last_vue_prog_data =
anv_pipeline_get_last_vue_prog_data(pipeline);
point_from_shader = last_vue_prog_data->vue_map.slots_valid & VARYING_BIT_PSIZ;
@@ -851,7 +851,7 @@ emit_cb_state(struct anv_graphics_pipeline *pipeline,
const struct vk_multisample_state *ms)
{
struct anv_device *device = pipeline->base.device;
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
struct GENX(BLEND_STATE) blend_state = {
#if GFX_VER >= 8
@@ -1009,7 +1009,7 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
const struct vk_viewport_state *vp,
const struct vk_rasterization_state *rs)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
(void) wm_prog_data;
struct GENX(3DSTATE_CLIP) clip = {
@@ -1047,7 +1047,7 @@ emit_3dstate_clip(struct anv_graphics_pipeline *pipeline,
clip.MinimumPointWidth = 0.125;
clip.MaximumPointWidth = 255.875;
const struct brw_vue_prog_data *last =
const struct elk_vue_prog_data *last =
anv_pipeline_get_last_vue_prog_data(pipeline);
/* From the Vulkan 1.0.45 spec:
@@ -1090,7 +1090,7 @@ static void
emit_3dstate_streamout(struct anv_graphics_pipeline *pipeline,
const struct vk_rasterization_state *rs)
{
const struct brw_vue_prog_data *prog_data =
const struct elk_vue_prog_data *prog_data =
anv_pipeline_get_last_vue_prog_data(pipeline);
const struct intel_vue_map *vue_map = &prog_data->vue_map;
@@ -1322,7 +1322,7 @@ static void
emit_3dstate_vs(struct anv_graphics_pipeline *pipeline)
{
const struct intel_device_info *devinfo = pipeline->base.device->info;
const struct brw_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct elk_vs_prog_data *vs_prog_data = get_vs_prog_data(pipeline);
const struct anv_shader_bin *vs_bin =
pipeline->shaders[MESA_SHADER_VERTEX];
@@ -1382,8 +1382,8 @@ emit_3dstate_hs_te_ds(struct anv_graphics_pipeline *pipeline,
const struct anv_shader_bin *tes_bin =
pipeline->shaders[MESA_SHADER_TESS_EVAL];
const struct brw_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline);
const struct brw_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
const struct elk_tcs_prog_data *tcs_prog_data = get_tcs_prog_data(pipeline);
const struct elk_tes_prog_data *tes_prog_data = get_tes_prog_data(pipeline);
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_HS), hs) {
hs.Enable = true;
@@ -1475,7 +1475,7 @@ emit_3dstate_gs(struct anv_graphics_pipeline *pipeline,
return;
}
const struct brw_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
const struct elk_gs_prog_data *gs_prog_data = get_gs_prog_data(pipeline);
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_GS), gs) {
gs.Enable = true;
@@ -1556,7 +1556,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
const struct vk_color_blend_state *cb,
const struct vk_graphics_pipeline_state *state)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
struct GENX(3DSTATE_WM) wm = {
GENX(3DSTATE_WM_header),
@@ -1598,7 +1598,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
#endif
wm.BarycentricInterpolationMode =
wm_prog_data_barycentric_modes(wm_prog_data, 0);
elk_wm_prog_data_barycentric_modes(wm_prog_data, 0);
#if GFX_VER < 8
wm.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
@@ -1623,7 +1623,7 @@ emit_3dstate_wm(struct anv_graphics_pipeline *pipeline,
wm.PixelShaderKillsPixel;
if (ms != NULL && ms->rasterization_samples > 1) {
if (brw_wm_prog_data_is_persample(wm_prog_data, 0)) {
if (elk_wm_prog_data_is_persample(wm_prog_data, 0)) {
wm.MultisampleDispatchMode = MSDISPMODE_PERSAMPLE;
} else {
wm.MultisampleDispatchMode = MSDISPMODE_PERPIXEL;
@@ -1663,7 +1663,7 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
return;
}
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
#if GFX_VER < 8
/* The hardware wedges if you have this bit set but don't turn on any dual
@@ -1693,11 +1693,11 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
0 /* msaa_flags */);
ps.KernelStartPointer0 = fs_bin->kernel.offset +
brw_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
elk_wm_prog_data_prog_offset(wm_prog_data, ps, 0);
ps.KernelStartPointer1 = fs_bin->kernel.offset +
brw_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
elk_wm_prog_data_prog_offset(wm_prog_data, ps, 1);
ps.KernelStartPointer2 = fs_bin->kernel.offset +
brw_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
elk_wm_prog_data_prog_offset(wm_prog_data, ps, 2);
ps.SingleProgramFlow = false;
ps.VectorMaskEnable = GFX_VER >= 8 &&
@@ -1729,11 +1729,11 @@ emit_3dstate_ps(struct anv_graphics_pipeline *pipeline,
#endif
ps.DispatchGRFStartRegisterForConstantSetupData0 =
brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
elk_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 0);
ps.DispatchGRFStartRegisterForConstantSetupData1 =
brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
elk_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 1);
ps.DispatchGRFStartRegisterForConstantSetupData2 =
brw_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
elk_wm_prog_data_dispatch_grf_start_reg(wm_prog_data, ps, 2);
ps.PerThreadScratchSpace = get_scratch_space(fs_bin);
ps.ScratchSpaceBasePointer =
@@ -1747,7 +1747,7 @@ emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
const struct vk_rasterization_state *rs,
const struct vk_graphics_pipeline_state *state)
{
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
if (!anv_pipeline_has_stage(pipeline, MESA_SHADER_FRAGMENT)) {
anv_batch_emit(&pipeline->base.batch, GENX(3DSTATE_PS_EXTRA), ps);
@@ -1759,7 +1759,7 @@ emit_3dstate_ps_extra(struct anv_graphics_pipeline *pipeline,
ps.AttributeEnable = wm_prog_data->num_varying_inputs > 0;
ps.oMaskPresenttoRenderTarget = wm_prog_data->uses_omask;
ps.PixelShaderIsPerSample =
brw_wm_prog_data_is_persample(wm_prog_data, 0);
elk_wm_prog_data_is_persample(wm_prog_data, 0);
ps.PixelShaderComputedDepthMode = wm_prog_data->computed_depth_mode;
ps.PixelShaderUsesSourceDepth = wm_prog_data->uses_src_depth;
ps.PixelShaderUsesSourceW = wm_prog_data->uses_src_w;
@@ -1796,7 +1796,7 @@ compute_kill_pixel(struct anv_graphics_pipeline *pipeline,
return;
}
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
/* This computes the KillPixel portion of the computation for whether or
* not we want to enable the PMA fix on gfx8 or gfx9. It's given by this
@@ -1851,7 +1851,7 @@ genX(graphics_pipeline_emit)(struct anv_graphics_pipeline *pipeline,
* Stall" bit set.
*/
if (device->info->platform == INTEL_PLATFORM_IVB)
gfx7_emit_vs_workaround_flush(brw);
gfx7_emit_vs_workaround_flush(elk);
#endif
emit_vertex_input(pipeline, state->vi);
@@ -1878,12 +1878,12 @@ genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
{
struct anv_device *device = pipeline->base.device;
const struct intel_device_info *devinfo = device->info;
const struct brw_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
const struct elk_cs_prog_data *cs_prog_data = get_cs_prog_data(pipeline);
anv_pipeline_setup_l3_config(&pipeline->base, cs_prog_data->base.total_shared > 0);
const struct intel_cs_dispatch_info dispatch =
brw_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
elk_cs_get_dispatch_info(devinfo, cs_prog_data, NULL);
const uint32_t vfe_curbe_allocation =
ALIGN(cs_prog_data->push.per_thread.regs * dispatch.threads +
cs_prog_data->push.cross_thread.regs, 2);
@@ -1932,7 +1932,7 @@ genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
struct GENX(INTERFACE_DESCRIPTOR_DATA) desc = {
.KernelStartPointer =
cs_bin->kernel.offset +
brw_cs_prog_data_prog_offset(cs_prog_data, dispatch.simd_size),
elk_cs_prog_data_prog_offset(cs_prog_data, dispatch.simd_size),
.SamplerCount = get_sampler_count(cs_bin),
/* We add 1 because the CS indirect parameters buffer isn't accounted
* for in bind_map.surface_count.
@@ -1940,7 +1940,7 @@ genX(compute_pipeline_emit)(struct anv_compute_pipeline *pipeline)
.BindingTableEntryCount = 1 + MIN2(cs_bin->bind_map.surface_count, 30),
.BarrierEnable = cs_prog_data->uses_barrier,
.SharedLocalMemorySize =
encode_slm_size(GFX_VER, cs_prog_data->base.total_shared),
elk_encode_slm_size(GFX_VER, cs_prog_data->base.total_shared),
#if GFX_VERx10 != 75
.ConstantURBEntryReadOffset = 0,
src/intel/vulkan_hasvk/gfx8_cmd_buffer.c
+1 -1
View File
@@ -137,7 +137,7 @@ want_depth_pma_fix(struct anv_cmd_buffer *cmd_buffer,
return false;
/* !(3DSTATE_WM::EDSC_Mode == EDSC_PREPS) */
const struct brw_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
const struct elk_wm_prog_data *wm_prog_data = get_wm_prog_data(pipeline);
if (wm_prog_data->early_fragment_tests)
return false;
src/intel/vulkan_hasvk/meson.build
+7 -7
View File
@@ -94,7 +94,7 @@ foreach g : [['70', ['gfx7_cmd_buffer.c']],
dep_libdrm, dep_valgrind, idep_nir_headers, idep_genxml,
idep_vulkan_util_headers, idep_vulkan_wsi_headers,
idep_vulkan_runtime_headers, idep_intel_driver_ds_headers,
idep_intel_blorp,
idep_intel_blorp_elk,
],
)
endforeach
@@ -190,14 +190,14 @@ libvulkan_intel_hasvk = shared_library(
],
link_whole : [libanv_hasvk_common, libanv_per_hw_ver_libs],
link_with : [
libintel_compiler, libisl, libintel_perf,
libintel_compiler_elk, libisl, libintel_perf,
],
dependencies : [
dep_thread, dep_dl, dep_m, anv_deps, idep_libintel_common,
idep_nir, idep_genxml, idep_vulkan_util, idep_vulkan_wsi,
idep_vulkan_runtime, idep_mesautil, idep_xmlconfig,
idep_intel_driver_ds, idep_intel_dev, idep_intel_blorp,
idep_intel_decoder_brw,
idep_intel_driver_ds, idep_intel_dev, idep_intel_blorp_elk,
idep_intel_decoder_elk,
],
c_args : anv_flags,
gnu_symbol_visibility : 'hidden',
@@ -229,14 +229,14 @@ if with_tests
],
link_whole : libanv_hasvk_common,
link_with : [
libanv_per_hw_ver_libs, libintel_compiler, libintel_common,
libanv_per_hw_ver_libs, libintel_compiler_elk, libintel_common,
libisl, libintel_perf,
],
dependencies : [
dep_thread, dep_dl, dep_m, anv_deps,
idep_nir, idep_vulkan_util, idep_vulkan_wsi, idep_vulkan_runtime,
idep_mesautil, idep_intel_dev, idep_intel_blorp,
idep_intel_decoder_brw,
idep_mesautil, idep_intel_dev, idep_intel_blorp_elk,
idep_intel_decoder_elk,
],
c_args : anv_flags,
gnu_symbol_visibility : 'hidden',