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amd: do not emit PA_SU_PRIM_FILTER_CNTL in the common GFX preamble

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RADV needs to adjust this register for user sample locations because
it seems possible to have a sample on the -8 coordinate.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31815>
This commit is contained in:
Samuel Pitoiset
2024-10-24 09:38:37 +02:00
committed by Marge Bot
parent 3d172d08b0
commit 927a17f30a
3 changed files with 13 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_cmdbuf.c
-13
View File
@@ -242,11 +242,6 @@ gfx6_init_graphics_preamble_state(const struct ac_preamble_state *state,
ac_pm4_set_reg(pm4, R_008B10_PA_SC_LINE_STIPPLE_STATE, 0);
}
/* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
ac_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(info->gfx_level >= GFX7) |
S_02882C_YMAX_BOTTOM_EXCLUSION(info->gfx_level >= GFX7));
if (info->gfx_level <= GFX7 || !info->has_clear_state) {
ac_pm4_set_reg(pm4, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
ac_pm4_set_reg(pm4, R_028C5C_VGT_OUT_DEALLOC_CNTL, 16);
@@ -479,10 +474,6 @@ gfx10_init_graphics_preamble_state(const struct ac_preamble_state *state,
if (info->gfx_level >= GFX10_3)
ac_pm4_set_reg(pm4, R_028750_SX_PS_DOWNCONVERT_CONTROL, 0xff);
/* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
ac_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(1) |
S_02882C_YMAX_BOTTOM_EXCLUSION(1));
ac_pm4_set_reg(pm4, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
S_028830_SMALL_PRIM_FILTER_ENABLE(1));
@@ -672,10 +663,6 @@ gfx12_init_graphics_preamble_state(const struct ac_preamble_state *state,
ac_pm4_set_reg(pm4, R_028820_PA_CL_NANINF_CNTL, 0);
ac_pm4_set_reg(pm4, R_028824_PA_SU_LINE_STIPPLE_CNTL, 0);
ac_pm4_set_reg(pm4, R_028828_PA_SU_LINE_STIPPLE_SCALE, 0);
/* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
ac_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(1) |
S_02882C_YMAX_BOTTOM_EXCLUSION(1));
ac_pm4_set_reg(pm4, R_028830_PA_SU_SMALL_PRIM_FILTER_CNTL,
S_028830_SMALL_PRIM_FILTER_ENABLE(1) |
S_028830_SC_1XMSAA_COMPATIBLE_DISABLE(1) /* use sample locations even for MSAA 1x */);
src/amd/vulkan/radv_queue.c
+6
View File
@@ -770,6 +770,12 @@ radv_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs)
radeon_set_context_reg(cs, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET, 0);
}
if (pdev->info.gfx_level >= GFX7) {
/* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
radeon_set_context_reg(cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(1) | S_02882C_YMAX_BOTTOM_EXCLUSION(1));
}
if (pdev->info.gfx_level <= GFX8)
radeon_set_sh_reg(cs, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(pdev->info.address32_hi >> 8));
src/gallium/drivers/radeonsi/si_state.c
+7
View File
@@ -5022,6 +5022,13 @@ static void si_init_graphics_preamble_state(struct si_context *sctx,
};
ac_init_graphics_preamble_state(&preamble_state, &pm4->base);
if (sctx->gfx_level >= GFX7) {
/* If any sample location uses the -8 coordinate, the EXCLUSION fields should be set to 0. */
ac_pm4_set_reg(&pm4->base, R_02882C_PA_SU_PRIM_FILTER_CNTL,
S_02882C_XMAX_RIGHT_EXCLUSION(1) |
S_02882C_YMAX_BOTTOM_EXCLUSION(1));
}
}
static void gfx6_init_gfx_preamble_state(struct si_context *sctx)