i965/vs: Avoid allocating registers in to the gen7 MRF hack region.

This is the corresponding fix to the previous one for the FS, but I
don't have a particular test for it.

NOTE: This is a candidate for the 8.0 branch.

src/mesa/drivers/dri/i965/brw_vec4.h

@@ -334,6 +334,7 @@ public:
    int virtual_grf_count;
    int virtual_grf_array_size;
    int first_non_payload_grf;
+   unsigned int max_grf;
    int *virtual_grf_def;
    int *virtual_grf_use;
    dst_reg userplane[MAX_CLIP_PLANES];

src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp

@@ -87,9 +87,9 @@ vec4_visitor::reg_allocate_trivial()
       assign(hw_reg_mapping, &inst->src[2]);
    }
 
-   if (prog_data->total_grf > BRW_MAX_GRF) {
+   if (prog_data->total_grf > max_grf) {
       fail("Ran out of regs on trivial allocator (%d/%d)\n",
-	   prog_data->total_grf, BRW_MAX_GRF);
+	   prog_data->total_grf, max_grf);
    }
 }
 
@@ -144,7 +144,7 @@ vec4_visitor::reg_allocate()
 {
    int hw_reg_mapping[virtual_grf_count];
    int first_assigned_grf = this->first_non_payload_grf;
-   int base_reg_count = BRW_MAX_GRF - first_assigned_grf;
+   int base_reg_count = max_grf - first_assigned_grf;
    int class_sizes[base_reg_count];
    int class_count = 0;
 

src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp

@@ -2615,6 +2615,8 @@ vec4_visitor::vec4_visitor(struct brw_vs_compile *c,
    this->virtual_grf_array_size = 0;
    this->live_intervals_valid = false;
 
+   this->max_grf = intel->gen >= 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+
    this->uniforms = 0;
 }