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i965: Fix the VS thread limits for GT1, and clarify the WM limits on both.

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This commit is contained in:
Eric Anholt
2011-03-29 13:22:13 -07:00
parent 6586a3b287
commit 904b8ba1bb
3 changed files with 13 additions and 4 deletions
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src/mesa/drivers/dri/i965/brw_context.c
+11 -2
View File
@@ -183,8 +183,17 @@ GLboolean brwCreateContext( int api,
/* WM maximum threads is number of EUs times number of threads per EU. */
if (intel->gen >= 6) {
brw->urb.size = 1024;
brw->vs_max_threads = 60;
brw->wm_max_threads = 80;
if (IS_GT2(intel->intelScreen->deviceID)) {
/* This could possibly be 80, but is supposed to require
* disabling of WIZ hashing (bit 6 of GT_MODE, 0x20d0) and a
* GPU reset to change.
*/
brw->wm_max_threads = 40;
brw->vs_max_threads = 60;
} else {
brw->wm_max_threads = 40;
brw->vs_max_threads = 24;
}
} else if (intel->gen == 5) {
brw->urb.size = 1024;
brw->vs_max_threads = 72;
src/mesa/drivers/dri/i965/gen6_vs_state.c
+1 -1
View File
@@ -137,7 +137,7 @@ upload_vs_state(struct brw_context *brw)
(brw->vs.prog_data->urb_read_length << GEN6_VS_URB_READ_LENGTH_SHIFT) |
(0 << GEN6_VS_URB_ENTRY_READ_OFFSET_SHIFT));
OUT_BATCH(((60 - 1) << GEN6_VS_MAX_THREADS_SHIFT) | /* max 60 threads for gen6 */
OUT_BATCH(((brw->vs_max_threads - 1) << GEN6_VS_MAX_THREADS_SHIFT) |
GEN6_VS_STATISTICS_ENABLE |
GEN6_VS_ENABLE);
ADVANCE_BATCH();
src/mesa/drivers/dri/i965/gen6_wm_state.c
+1 -1
View File
@@ -144,7 +144,7 @@ upload_wm_state(struct brw_context *brw)
dw4 |= (brw->wm.prog_data->first_curbe_grf <<
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
dw5 |= (40 - 1) << GEN6_WM_MAX_THREADS_SHIFT;
dw5 |= (brw->wm_max_threads - 1) << GEN6_WM_MAX_THREADS_SHIFT;
/* CACHE_NEW_WM_PROG */
if (brw->wm.prog_data->dispatch_width == 8)