ir3/legalize: Use define for register size

This was introduced in a previous commit

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22075>
This commit is contained in:
Connor Abbott
2021-10-07 12:47:06 +02:00
committed by Marge Bot
parent 750e6843c0
commit 90067425a6
3 changed files with 3 additions and 17 deletions
-11
View File
@@ -1379,17 +1379,6 @@ writes_pred(struct ir3_instruction *instr)
return false;
}
/* Is it something other than a normal register. Shared regs, p0, and a0/a1
* are considered special here. Special registers are always accessed with one
* size and never alias normal registers, even though a naive calculation
* would sometimes make it seem like e.g. r30.z aliases a0.x.
*/
static inline bool
is_reg_special(const struct ir3_register *reg)
{
return (reg->flags & IR3_REG_SHARED) || !is_reg_gpr(reg);
}
/* r0.x - r47.w are "normal" registers. r48.x - r55.w are shared registers.
* Everything above those are non-GPR registers like a0.x and p0.x that aren't
* assigned by RA.
+1 -4
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@@ -124,14 +124,11 @@ ir3_delayslots_with_repeat(struct ir3_instruction *assigner,
if (assigner->opc == OPC_MOVMSK)
return delay;
bool mismatched_half =
(src->flags & IR3_REG_HALF) != (dst->flags & IR3_REG_HALF);
/* TODO: Handle the combination of (rpt) and different component sizes
* better like below. This complicates things significantly because the
* components don't line up.
*/
if (mismatched_half)
if ((src->flags & IR3_REG_HALF) != (dst->flags & IR3_REG_HALF))
return delay;
/* If an instruction has a (rpt), then it acts as a sequence of
+2 -2
View File
@@ -55,8 +55,8 @@ struct ir3_legalize_ctx {
};
struct ir3_nop_state {
unsigned full_ready[4 * 48];
unsigned half_ready[4 * 48];
unsigned full_ready[GPR_REG_SIZE];
unsigned half_ready[GPR_REG_SIZE];
};
struct ir3_legalize_state {