radv: use ac_emit_cp_pfp_sync_me() more
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/37870>
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8f80a8502d
@@ -5254,27 +5254,26 @@ radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i
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uint64_t va = radv_image_get_fast_clear_va(image, iview->vk.base_mip_level);
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uint32_t reg = R_028C8C_CB_COLOR0_CLEAR_WORD0 + cb_idx * 0x3c;
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radeon_begin(cs);
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if (pdev->info.has_load_ctx_reg_pkt) {
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));
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radeon_emit(va);
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radeon_emit(va >> 32);
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radeon_emit((reg - SI_CONTEXT_REG_OFFSET) >> 2);
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radeon_emit(2);
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radeon_end();
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} else {
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));
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radeon_emit(COPY_DATA_SRC_SEL(COPY_DATA_SRC_MEM) | COPY_DATA_DST_SEL(COPY_DATA_REG) | COPY_DATA_COUNT_SEL);
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radeon_emit(va);
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radeon_emit(va >> 32);
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radeon_emit(reg >> 2);
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radeon_emit(0);
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radeon_end();
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radeon_emit(PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
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radeon_emit(0);
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ac_emit_cp_pfp_sync_me(cs->b, cmd_buffer->state.predicating);
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}
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radeon_end();
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}
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/* GFX9+ metadata cache flushing workaround. metadata cache coherency is
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@@ -13075,10 +13074,7 @@ radv_CmdExecuteGeneratedCommandsEXT(VkCommandBuffer commandBuffer, VkBool32 isPr
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if (!radv_cmd_buffer_uses_mec(cmd_buffer)) {
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radeon_check_space(device->ws, cs->b, 2);
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
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radeon_emit(0);
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radeon_end();
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ac_emit_cp_pfp_sync_me(cs->b, cmd_buffer->state.predicating);
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}
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radv_dgc_execute_ib(cmd_buffer, pGeneratedCommandsInfo);
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@@ -118,10 +118,7 @@ radv_emit_cp_dma(struct radv_cmd_buffer *cmd_buffer, uint64_t dst_va, uint64_t s
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*/
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if (flags & CP_DMA_SYNC) {
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if (cmd_buffer->qf == RADV_QUEUE_GENERAL) {
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radeon_begin(cs);
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radeon_emit(PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));
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radeon_emit(0);
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radeon_end();
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ac_emit_cp_pfp_sync_me(cs->b, cmd_buffer->state.predicating);
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}
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/* CP will see the sync flag and wait for all DMAs to complete. */
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