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i965/vec4/tes: consider register offsets during attribute setup

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Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Iago Toral Quiroga
2016-09-15 10:49:40 +02:00
committed by Samuel Iglesias Gonsálvez
parent 49d4d0268b
commit 8e92b40203
1 changed files with 2 additions and 2 deletions
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src/mesa/drivers/dri/i965/brw_vec4_tes.cpp
+2 -2
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@@ -84,8 +84,8 @@ vec4_tes_visitor::setup_payload()
bool is_64bit = type_sz(inst->src[i].type) == 8;
struct brw_reg grf =
brw_vec4_grf(reg + inst->src[i].nr / 2, 4 * (inst->src[i].nr % 2));
unsigned slot = inst->src[i].nr + inst->src[i].offset / 16;
struct brw_reg grf = brw_vec4_grf(reg + slot / 2, 4 * (slot % 2));
grf = stride(grf, 0, is_64bit ? 2 : 4, 1);
grf.swizzle = inst->src[i].swizzle;
grf.type = inst->src[i].type;