i965/nir/vec4: Implement equality ops on vectors
Adds NIR ALU operations: * nir_op_ball_fequal2 * nir_op_ball_iequal2 * nir_op_ball_fequal3 * nir_op_ball_iequal3 * nir_op_ball_fequal4 * nir_op_ball_iequal4 Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
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committed by
Jason Ekstrand
parent
84d4a9dc2c
commit
8be4b876c9
@@ -922,6 +922,39 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
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brw_conditional_for_nir_comparison(instr->op)));
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break;
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case nir_op_ball_fequal2:
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case nir_op_ball_iequal2:
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case nir_op_ball_fequal3:
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case nir_op_ball_iequal3:
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case nir_op_ball_fequal4:
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case nir_op_ball_iequal4: {
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dst_reg tmp = dst_reg(this, glsl_type::bool_type);
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switch (instr->op) {
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case nir_op_ball_fequal2:
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case nir_op_ball_iequal2:
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tmp.writemask = WRITEMASK_XY;
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break;
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case nir_op_ball_fequal3:
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case nir_op_ball_iequal3:
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tmp.writemask = WRITEMASK_XYZ;
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break;
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case nir_op_ball_fequal4:
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case nir_op_ball_iequal4:
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tmp.writemask = WRITEMASK_XYZW;
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break;
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default:
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unreachable("not reached");
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}
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emit(CMP(tmp, op[0], op[1],
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brw_conditional_for_nir_comparison(instr->op)));
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emit(MOV(dst, src_reg(0)));
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inst = emit(MOV(dst, src_reg(~0)));
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inst->predicate = BRW_PREDICATE_ALIGN16_ALL4H;
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break;
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}
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default:
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unreachable("Unimplemented ALU operation");
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}
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