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r600+radeonsi: use ctx_query_reset_status on radeon

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This allows a nice cleanup, because the winsys always handles it.
This commit is contained in:
Marek Olšák
2019-05-08 20:49:58 -04:00
parent 4549c36788
commit 894e017c9c
10 changed files with 5 additions and 55 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_gpu_info.c
-2
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@@ -379,7 +379,6 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
info->si_TA_CS_BC_BASE_ADDR_allowed = true;
info->has_bo_metadata = true;
info->has_gpu_reset_status_query = true;
info->has_gpu_reset_counter_query = false;
info->has_eqaa_surface_allocator = true;
info->has_format_bc1_through_bc7 = true;
/* DRM 3.1.0 doesn't flush TC for GFX8 correctly. */
@@ -568,7 +567,6 @@ void ac_print_gpu_info(struct radeon_info *info)
printf(" si_TA_CS_BC_BASE_ADDR_allowed = %u\n", info->si_TA_CS_BC_BASE_ADDR_allowed);
printf(" has_bo_metadata = %u\n", info->has_bo_metadata);
printf(" has_gpu_reset_status_query = %u\n", info->has_gpu_reset_status_query);
printf(" has_gpu_reset_counter_query = %u\n", info->has_gpu_reset_counter_query);
printf(" has_eqaa_surface_allocator = %u\n", info->has_eqaa_surface_allocator);
printf(" has_format_bc1_through_bc7 = %u\n", info->has_format_bc1_through_bc7);
printf(" kernel_flushes_tc_l2_after_ib = %u\n", info->kernel_flushes_tc_l2_after_ib);
src/amd/common/ac_gpu_info.h
-1
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@@ -110,7 +110,6 @@ struct radeon_info {
bool si_TA_CS_BC_BASE_ADDR_allowed;
bool has_bo_metadata;
bool has_gpu_reset_status_query;
bool has_gpu_reset_counter_query;
bool has_eqaa_surface_allocator;
bool has_format_bc1_through_bc7;
bool kernel_flushes_tc_l2_after_ib;
src/gallium/drivers/r600/r600_pipe_common.c
+2 -14
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@@ -546,14 +546,8 @@ void radeon_clear_saved_cs(struct radeon_saved_cs *saved)
static enum pipe_reset_status r600_get_reset_status(struct pipe_context *ctx)
{
struct r600_common_context *rctx = (struct r600_common_context *)ctx;
unsigned latest = rctx->ws->query_value(rctx->ws,
RADEON_GPU_RESET_COUNTER);
if (rctx->gpu_reset_counter == latest)
return PIPE_NO_RESET;
rctx->gpu_reset_counter = latest;
return PIPE_UNKNOWN_CONTEXT_RESET;
return rctx->ws->ctx_query_reset_status(rctx->ctx);
}
static void r600_set_debug_callback(struct pipe_context *ctx,
@@ -673,13 +667,7 @@ bool r600_common_context_init(struct r600_common_context *rctx,
else
rctx->b.buffer_subdata = r600_buffer_subdata;
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->gpu_reset_counter =
rctx->ws->query_value(rctx->ws,
RADEON_GPU_RESET_COUNTER);
}
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
r600_init_context_texture_functions(rctx);
src/gallium/drivers/r600/r600_pipe_common.h
-1
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@@ -517,7 +517,6 @@ struct r600_common_context {
struct r600_resource *eop_bug_scratch;
unsigned num_gfx_cs_flushes;
unsigned initial_gfx_cs_size;
unsigned gpu_reset_counter;
unsigned last_dirty_tex_counter;
unsigned last_compressed_colortex_counter;
unsigned last_num_draw_calls;
src/gallium/drivers/radeon/radeon_winsys.h
-1
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@@ -133,7 +133,6 @@ enum radeon_value_id {
RADEON_GPU_TEMPERATURE, /* DRM 2.42.0 */
RADEON_CURRENT_SCLK,
RADEON_CURRENT_MCLK,
RADEON_GPU_RESET_COUNTER, /* DRM 2.43.0 */
RADEON_CS_THREAD_TIME,
};
src/gallium/drivers/radeonsi/si_get.c
+1 -2
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@@ -162,8 +162,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
return !SI_BIG_ENDIAN && sscreen->info.has_userptr;
case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
return sscreen->info.has_gpu_reset_status_query ||
sscreen->info.has_gpu_reset_counter_query;
return sscreen->info.has_gpu_reset_status_query;
case PIPE_CAP_TEXTURE_MULTISAMPLE:
return sscreen->info.has_2d_tiling;
src/gallium/drivers/radeonsi/si_pipe.c
+2 -25
View File
@@ -286,21 +286,7 @@ static enum pipe_reset_status si_get_reset_status(struct pipe_context *ctx)
{
struct si_context *sctx = (struct si_context *)ctx;
if (sctx->screen->info.has_gpu_reset_status_query)
return sctx->ws->ctx_query_reset_status(sctx->ctx);
if (sctx->screen->info.has_gpu_reset_counter_query) {
unsigned latest = sctx->ws->query_value(sctx->ws,
RADEON_GPU_RESET_COUNTER);
if (sctx->gpu_reset_counter == latest)
return PIPE_NO_RESET;
sctx->gpu_reset_counter = latest;
return PIPE_UNKNOWN_CONTEXT_RESET;
}
return PIPE_NO_RESET;
return sctx->ws->ctx_query_reset_status(sctx->ctx);
}
static void si_set_device_reset_callback(struct pipe_context *ctx,
@@ -322,10 +308,7 @@ bool si_check_device_reset(struct si_context *sctx)
if (!sctx->device_reset_callback.reset)
return false;
if (!sctx->b.get_device_reset_status)
return false;
status = sctx->b.get_device_reset_status(&sctx->b);
status = sctx->ws->ctx_query_reset_status(sctx->ctx);
if (status == PIPE_NO_RESET)
return false;
@@ -422,12 +405,6 @@ static struct pipe_context *si_create_context(struct pipe_screen *screen,
sctx->family = sscreen->info.family;
sctx->chip_class = sscreen->info.chip_class;
if (sscreen->info.has_gpu_reset_counter_query) {
sctx->gpu_reset_counter =
sctx->ws->query_value(sctx->ws, RADEON_GPU_RESET_COUNTER);
}
if (sctx->chip_class == GFX7 ||
sctx->chip_class == GFX8 ||
sctx->chip_class == GFX9) {
src/gallium/drivers/radeonsi/si_pipe.h
-1
View File
@@ -859,7 +859,6 @@ struct si_context {
unsigned num_gfx_cs_flushes;
unsigned initial_gfx_cs_size;
unsigned gpu_reset_counter;
unsigned last_dirty_tex_counter;
unsigned last_dirty_buf_counter;
unsigned last_compressed_colortex_counter;
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
-3
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@@ -219,9 +219,6 @@ static uint64_t amdgpu_query_value(struct radeon_winsys *rws,
case RADEON_CURRENT_MCLK:
amdgpu_query_sensor_info(ws->dev, AMDGPU_INFO_SENSOR_GFX_MCLK, 4, &retval);
return retval;
case RADEON_GPU_RESET_COUNTER:
assert(0);
return 0;
case RADEON_CS_THREAD_TIME:
return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
}
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
-5
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@@ -573,7 +573,6 @@ static bool do_winsys_init(struct radeon_drm_winsys *ws)
ws->info.si_TA_CS_BC_BASE_ADDR_allowed = ws->info.drm_minor >= 48;
ws->info.has_bo_metadata = false;
ws->info.has_gpu_reset_status_query = ws->info.drm_minor >= 43;
ws->info.has_gpu_reset_counter_query = ws->info.drm_minor >= 43;
ws->info.has_eqaa_surface_allocator = false;
ws->info.has_format_bc1_through_bc7 = ws->info.drm_minor >= 31;
ws->info.kernel_flushes_tc_l2_after_ib = true;
@@ -730,10 +729,6 @@ static uint64_t radeon_query_value(struct radeon_winsys *rws,
radeon_get_drm_value(ws->fd, RADEON_INFO_CURRENT_GPU_MCLK,
"current-gpu-mclk", (uint32_t*)&retval);
return retval;
case RADEON_GPU_RESET_COUNTER:
radeon_get_drm_value(ws->fd, RADEON_INFO_GPU_RESET_COUNTER,
"gpu-reset-counter", (uint32_t*)&retval);
return retval;
case RADEON_CS_THREAD_TIME:
return util_queue_get_thread_time_nano(&ws->cs_queue, 0);
}