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radv: move chip_class extraction down further.

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This seems to matter here in a profile, without this we spend a lot
more time exiting this function with no flush bits.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Dave Airlie
2017-06-07 09:34:28 +10:00
parent 00fe30f376
commit 86eff151b1
1 changed files with 2 additions and 1 deletions
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src/amd/vulkan/si_cmd_buffer.c
+2 -1
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@@ -1079,7 +1079,7 @@ void
si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
{
bool is_compute = cmd_buffer->queue_family_index == RADV_QUEUE_COMPUTE;
enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
if (is_compute)
cmd_buffer->state.flush_bits &= ~(RADV_CMD_FLAG_FLUSH_AND_INV_CB |
RADV_CMD_FLAG_FLUSH_AND_INV_CB_META |
@@ -1092,6 +1092,7 @@ si_emit_cache_flush(struct radv_cmd_buffer *cmd_buffer)
if (!cmd_buffer->state.flush_bits)
return;
enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;
radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 128);
uint32_t *ptr = NULL;