r300: simplify vectorization rules
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com> Reviewed-by: Emma Anholt <emma@anholt.net> Reviewed-by: Filip Gawin <filip.gawin@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23437>
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@@ -2449,8 +2449,7 @@ type_size(const struct glsl_type *type, bool bindless)
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return glsl_count_attribute_slots(type, false);
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}
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/* Allow vectorizing of ALU instructions, but avoid vectorizing past what we
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* can handle for 64-bit values in TGSI.
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/* Allow vectorizing of ALU instructions.
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*/
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static uint8_t
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ntr_should_vectorize_instr(const nir_instr *instr, const void *data)
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@@ -2458,38 +2457,6 @@ ntr_should_vectorize_instr(const nir_instr *instr, const void *data)
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if (instr->type != nir_instr_type_alu)
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return 0;
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nir_alu_instr *alu = nir_instr_as_alu(instr);
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switch (alu->op) {
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case nir_op_ibitfield_extract:
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case nir_op_ubitfield_extract:
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case nir_op_bitfield_insert:
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/* virglrenderer only looks at the .x channel of the offset/bits operands
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* when translating to GLSL. tgsi.rst doesn't seem to require scalar
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* offset/bits operands.
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*
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* https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues/195
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*/
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return 1;
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default:
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break;
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}
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int src_bit_size = nir_src_bit_size(alu->src[0].src);
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int dst_bit_size = alu->def.bit_size;
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if (src_bit_size == 64 || dst_bit_size == 64) {
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/* Avoid vectorizing 64-bit instructions at all. Despite tgsi.rst
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* claiming support, virglrenderer generates bad shaders on the host when
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* presented with them. Maybe we can make virgl avoid tickling the
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* virglrenderer bugs, but given that glsl-to-TGSI didn't generate vector
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* 64-bit instrs in the first place, I don't see much reason to care about
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* this.
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*/
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return 1;
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}
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return 4;
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}
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