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radv: fix fetching draw vertex data from counter buffers with transform feedback

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counterOffset was just ignored and nobody noticed (missing VKCTS
coverage).

VGT_STRMOUT_DRAW_OPAQUE_OFFSET will do the computation in hw for us.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33407>
This commit is contained in:
Samuel Pitoiset
2025-02-05 18:33:57 +01:00
committed by Marge Bot
parent 4f73689d9a
commit 8625decbcc
3 changed files with 8 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_cmdbuf.c
-2
View File
@@ -249,7 +249,6 @@ gfx6_init_graphics_preamble_state(const struct ac_preamble_state *state,
/* CLEAR_STATE doesn't clear these correctly on certain generations.
* I don't know why. Deduced by trial and error.
*/
ac_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
ac_pm4_set_reg(pm4, R_028204_PA_SC_WINDOW_SCISSOR_TL, S_028204_WINDOW_OFFSET_DISABLE(1));
ac_pm4_set_reg(pm4, R_028030_PA_SC_SCREEN_SCISSOR_TL, 0);
}
@@ -677,7 +676,6 @@ gfx12_init_graphics_preamble_state(const struct ac_preamble_state *state,
ac_pm4_set_reg(pm4, R_028AA0_VGT_DRAW_PAYLOAD_CNTL, 0);
ac_pm4_set_reg(pm4, R_028ABC_DB_HTILE_SURFACE, 0);
ac_pm4_set_reg(pm4, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
ac_pm4_set_reg(pm4, R_028B50_VGT_TESS_DISTRIBUTION,
S_028B50_ACCUM_ISOLINE(128) |
S_028B50_ACCUM_TRI(128) |
src/amd/vulkan/radv_cmd_buffer.c
+5 -2
View File
@@ -13622,7 +13622,8 @@ radv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCou
}
static void
radv_emit_strmout_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *draw_info)
radv_emit_strmout_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *draw_info,
uint32_t counter_offset)
{
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
@@ -13655,6 +13656,8 @@ radv_emit_strmout_buffer(struct radv_cmd_buffer *cmd_buffer, const struct radv_d
radeon_emit(cs, 0); /* unused */
}
radeon_set_context_reg(cs, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, counter_offset);
radv_cs_add_buffer(device->ws, cs, draw_info->strmout_buffer->bo);
}
@@ -13681,7 +13684,7 @@ radv_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanc
if (!radv_before_draw(cmd_buffer, &info, 1, false))
return;
struct VkMultiDrawInfoEXT minfo = {0, 0};
radv_emit_strmout_buffer(cmd_buffer, &info);
radv_emit_strmout_buffer(cmd_buffer, &info, counterOffset);
radv_emit_direct_draw_packets(cmd_buffer, &info, 1, &minfo, S_0287F0_USE_OPAQUE(1), 0);
if (pdev->info.gfx_level == GFX12) {
src/gallium/drivers/radeonsi/si_state.c
+3
View File
@@ -5006,6 +5006,7 @@ static void gfx6_init_gfx_preamble_state(struct si_context *sctx)
}
if (sctx->gfx_level <= GFX7 || !has_clear_state) {
ac_pm4_set_reg(&pm4->base, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
ac_pm4_set_reg(&pm4->base, R_028034_PA_SC_SCREEN_SCISSOR_BR,
S_028034_BR_X(16384) | S_028034_BR_Y(16384));
}
@@ -5153,6 +5154,8 @@ static void gfx12_init_gfx_preamble_state(struct si_context *sctx)
S_028648_IDX0_EXPORT_FORMAT(V_028648_SPI_SHADER_1COMP));
ac_pm4_set_reg(&pm4->base, R_028658_SPI_BARYC_CNTL, 0);
ac_pm4_set_reg(&pm4->base, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
/* The rate combiners have no effect if they are disabled like this:
* VERTEX_RATE: BYPASS_VTX_RATE_COMBINER = 1
* PRIMITIVE_RATE: BYPASS_PRIM_RATE_COMBINER = 1