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nak: Dst is no longer Copy

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Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34794>
This commit is contained in:
Mel Henning
2025-04-30 17:07:42 -04:00
committed by Marge Bot
parent 0ac3296f28
commit 854b2d5882
9 changed files with 220 additions and 220 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/nouveau/compiler/nak/builder.rs
+2 -2
View File
@@ -354,7 +354,7 @@ pub trait SSABuilder: Builder {
self.push_op(OpIAdd3 {
dst: dst.into(),
srcs: [x, y, z],
overflow: [Dst::None; 2],
overflow: [Dst::None, Dst::None],
});
} else {
assert!(z.is_zero());
@@ -488,7 +488,7 @@ pub trait SSABuilder: Builder {
if self.sm() >= 70 {
self.push_op(OpIAdd3 {
dst: dst.into(),
overflow: [Dst::None; 2],
overflow: [Dst::None, Dst::None],
srcs: [0.into(), i.ineg(), 0.into()],
});
} else {
src/nouveau/compiler/nak/from_nir.rs
+1 -1
View File
@@ -1818,7 +1818,7 @@ impl<'a> ShaderFromNir<'a> {
let dst = b.alloc_ssa_vec(RegFile::GPR, dst_comps);
// On Volta and later, the destination is split in two
let mut dsts = [Dst::None; 2];
let mut dsts = [Dst::None, Dst::None];
if dst_comps > 2 && b.sm() >= 70 {
dsts[0] = SSARef::try_from(&dst[0..2]).unwrap().into();
dsts[1] = SSARef::try_from(&dst[2..]).unwrap().into();
src/nouveau/compiler/nak/ir.rs
+1 -1
View File
@@ -660,7 +660,7 @@ impl fmt::Display for RegRef {
}
}
#[derive(Clone, Copy)]
#[derive(Clone)]
pub enum Dst {
None,
SSA(SSARef),
src/nouveau/compiler/nak/legalize.rs
+1 -1
View File
@@ -281,7 +281,7 @@ pub trait LegalizeBuildHelpers: SSABuilder {
if self.sm() >= 70 {
self.push_op(OpIAdd3 {
srcs: [Src::new_zero(), *src, Src::new_zero()],
overflow: [Dst::None; 2],
overflow: [Dst::None, Dst::None],
dst: val.into(),
});
} else {
src/nouveau/compiler/nak/opt_out.rs
+1 -1
View File
@@ -31,7 +31,7 @@ fn try_combine_outs(emit: &mut Instr, cut: &Instr) -> bool {
return false;
}
emit.dst = cut.dst;
emit.dst = cut.dst.clone();
emit.out_type = OutType::EmitThenCut;
true
src/nouveau/compiler/nak/sm20.rs
+56 -56
View File
@@ -242,10 +242,10 @@ impl SM20Encoder<'_> {
self.set_bit(range.end - 1, not ^ src.src_mod.is_bnot());
}
fn set_pred_dst(&mut self, range: Range<usize>, dst: Dst) {
fn set_pred_dst(&mut self, range: Range<usize>, dst: &Dst) {
let reg = match dst {
Dst::None => true_reg(),
Dst::Reg(reg) => reg,
Dst::Reg(reg) => *reg,
_ => panic!("Dst is not pred {dst}"),
};
self.set_pred_reg(range, reg);
@@ -255,13 +255,13 @@ impl SM20Encoder<'_> {
&mut self,
range1: Range<usize>,
range2: Range<usize>,
dst: Dst,
dst: &Dst,
) {
assert!(range1.len() == 2);
assert!(range2.len() == 1);
let reg = match dst {
Dst::None => true_reg(),
Dst::Reg(reg) => reg,
Dst::Reg(reg) => *reg,
_ => panic!("Dst is not pred {dst}"),
};
assert!(reg.file() == RegFile::Pred);
@@ -304,10 +304,10 @@ impl SM20Encoder<'_> {
self.set_reg_src_ref(range, &src.src_ref);
}
fn set_dst(&mut self, range: Range<usize>, dst: Dst) {
fn set_dst(&mut self, range: Range<usize>, dst: &Dst) {
let reg = match dst {
Dst::None => zero_reg(),
Dst::Reg(reg) => reg,
Dst::Reg(reg) => *reg,
_ => panic!("Invalid dst {dst}"),
};
self.set_reg(range, reg);
@@ -325,11 +325,11 @@ impl SM20Encoder<'_> {
}
}
fn set_carry_out(&mut self, bit: usize, dst: Dst) {
fn set_carry_out(&mut self, bit: usize, dst: &Dst) {
match dst {
Dst::None => self.set_bit(bit, false),
Dst::Reg(reg) => {
assert!(reg == RegRef::new(RegFile::Carry, 0, 1));
assert!(*reg == RegRef::new(RegFile::Carry, 0, 1));
self.set_bit(bit, true);
}
_ => panic!("Invalid carry out: {dst}"),
@@ -372,7 +372,7 @@ impl SM20Encoder<'_> {
src2: Option<&Src>,
) {
self.set_opcode(unit, opcode);
if let Some(&dst) = dst {
if let Some(dst) = dst {
self.set_dst(14..20, dst);
}
@@ -442,7 +442,7 @@ impl SM20Encoder<'_> {
imm_src1: u32,
) {
self.set_opcode(SM20Unit::Imm32, opcode);
if let Some(&dst) = dst {
if let Some(dst) = dst {
self.set_dst(14..20, dst);
}
@@ -459,8 +459,8 @@ impl SM20Encoder<'_> {
&mut self,
unit: SM20Unit,
opcode: u8,
dst: Dst,
src: Src,
dst: &Dst,
src: &Src,
) {
self.set_opcode(unit, opcode);
self.set_dst(14..20, dst);
@@ -493,7 +493,7 @@ impl SM20Encoder<'_> {
}
}
fn encode_form_b_imm32(&mut self, opcode: u8, dst: Dst, imm_src: u32) {
fn encode_form_b_imm32(&mut self, opcode: u8, dst: &Dst, imm_src: u32) {
self.set_opcode(SM20Unit::Imm32, opcode);
self.set_dst(14..20, dst);
self.set_field(26..58, imm_src);
@@ -740,7 +740,7 @@ impl SM20Op for OpRro {
}
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.encode_form_b(SM20Unit::Float, 0x18, self.dst, self.src);
e.encode_form_b(SM20Unit::Float, 0x18, &self.dst, &self.src);
e.set_field(
5..6,
match self.op {
@@ -762,7 +762,7 @@ impl SM20Op for OpMuFu {
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.set_opcode(SM20Unit::Float, 0x32);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src_ref(20..26, &self.src.src_ref);
e.set_bit(5, false); // .sat
@@ -840,8 +840,8 @@ impl SM20Op for OpFSetP {
e.set_bit(7, self.srcs[0].src_mod.has_fabs());
e.set_bit(8, self.srcs[1].src_mod.has_fneg());
e.set_bit(9, self.srcs[0].src_mod.has_fneg());
e.set_pred_dst(14..17, Dst::None);
e.set_pred_dst(17..20, self.dst);
e.set_pred_dst(14..17, &Dst::None);
e.set_pred_dst(17..20, &self.dst);
e.set_pred_src(49..53, self.accum);
e.set_pred_set_op(53..55, self.set_op);
e.set_float_cmp_op(55..59, self.cmp_op);
@@ -859,7 +859,7 @@ impl SM20Op for OpFSwz {
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.set_opcode(SM20Unit::Float, 0x12);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, self.srcs[0]);
e.set_reg_src(26..32, self.srcs[1]);
@@ -1033,8 +1033,8 @@ impl SM20Op for OpDSetP {
e.set_bit(7, self.srcs[0].src_mod.has_fabs());
e.set_bit(8, self.srcs[1].src_mod.has_fneg());
e.set_bit(9, self.srcs[0].src_mod.has_fneg());
e.set_pred_dst(14..17, Dst::None);
e.set_pred_dst(17..20, self.dst);
e.set_pred_dst(14..17, &Dst::None);
e.set_pred_dst(17..20, &self.dst);
e.set_pred_src(49..53, self.accum);
e.set_pred_set_op(53..55, self.set_op);
e.set_float_cmp_op(55..59, self.cmp_op);
@@ -1072,7 +1072,7 @@ impl SM20Op for OpFlo {
}
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.encode_form_b(SM20Unit::Int, 0x1e, self.dst, self.src);
e.encode_form_b(SM20Unit::Int, 0x1e, &self.dst, &self.src);
e.set_bit(5, self.signed);
e.set_bit(6, self.return_shift_amount);
e.set_bit(8, self.src.src_mod.is_bnot());
@@ -1106,7 +1106,7 @@ impl SM20Op for OpIAdd2 {
Some(&self.srcs[0]),
imm32,
);
e.set_carry_out(58, self.carry_out);
e.set_carry_out(58, &self.carry_out);
} else {
e.encode_form_a(
SM20Unit::Int,
@@ -1116,7 +1116,7 @@ impl SM20Op for OpIAdd2 {
Some(&self.srcs[1]),
None,
);
e.set_carry_out(48, self.carry_out);
e.set_carry_out(48, &self.carry_out);
}
e.set_bit(5, false); // saturate
@@ -1145,7 +1145,7 @@ impl SM20Op for OpIAdd2X {
Some(&self.srcs[0]),
imm32,
);
e.set_carry_out(58, self.carry_out);
e.set_carry_out(58, &self.carry_out);
} else {
e.encode_form_a(
SM20Unit::Int,
@@ -1155,7 +1155,7 @@ impl SM20Op for OpIAdd2X {
Some(&self.srcs[1]),
None,
);
e.set_carry_out(48, self.carry_out);
e.set_carry_out(48, &self.carry_out);
}
e.set_bit(5, false); // saturate
@@ -1336,8 +1336,8 @@ impl SM20Op for OpISetP {
e.set_bit(5, self.cmp_type.is_signed());
e.set_bit(6, self.ex);
e.set_pred_dst(14..17, Dst::None);
e.set_pred_dst(17..20, self.dst);
e.set_pred_dst(14..17, &Dst::None);
e.set_pred_dst(17..20, &self.dst);
e.set_pred_src(49..53, self.accum);
e.set_pred_set_op(53..55, self.set_op);
e.set_int_cmp_op(55..58, self.cmp_op);
@@ -1476,7 +1476,7 @@ impl SM20Op for OpF2F {
}
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.encode_form_b(SM20Unit::Move, 0x4, self.dst, self.src);
e.encode_form_b(SM20Unit::Move, 0x4, &self.dst, &self.src);
e.set_bit(5, false); // .sat
e.set_bit(6, self.src.src_mod.has_fabs());
e.set_bit(7, self.integer_rnd);
@@ -1496,7 +1496,7 @@ impl SM20Op for OpF2I {
}
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.encode_form_b(SM20Unit::Move, 0x5, self.dst, self.src);
e.encode_form_b(SM20Unit::Move, 0x5, &self.dst, &self.src);
e.set_bit(6, self.src.src_mod.has_fabs());
e.set_bit(7, self.dst_type.is_signed());
e.set_bit(8, self.src.src_mod.has_fneg());
@@ -1516,7 +1516,7 @@ impl SM20Op for OpI2F {
fn encode(&self, e: &mut SM20Encoder<'_>) {
assert!(self.src.src_mod.is_none());
e.encode_form_b(SM20Unit::Move, 0x6, self.dst, self.src);
e.encode_form_b(SM20Unit::Move, 0x6, &self.dst, &self.src);
e.set_bit(6, false); // .abs
e.set_bit(8, false); // .neg
e.set_bit(9, self.src_type.is_signed());
@@ -1535,7 +1535,7 @@ impl SM20Op for OpI2I {
fn encode(&self, e: &mut SM20Encoder<'_>) {
assert!(self.src.src_mod.is_none());
e.encode_form_b(SM20Unit::Move, 0x7, self.dst, self.src);
e.encode_form_b(SM20Unit::Move, 0x7, &self.dst, &self.src);
e.set_bit(5, self.saturate);
e.set_bit(6, self.abs);
e.set_bit(7, self.dst_type.is_signed());
@@ -1554,9 +1554,9 @@ impl SM20Op for OpMov {
fn encode(&self, e: &mut SM20Encoder<'_>) {
if let Some(imm32) = self.src.as_imm_not_i20() {
e.encode_form_b_imm32(0x6, self.dst, imm32);
e.encode_form_b_imm32(0x6, &self.dst, imm32);
} else {
e.encode_form_b(SM20Unit::Move, 0xa, self.dst, self.src);
e.encode_form_b(SM20Unit::Move, 0xa, &self.dst, &self.src);
}
e.set_field(5..9, self.quad_lanes);
}
@@ -1635,8 +1635,8 @@ impl SM20Op for OpShfl {
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.set_opcode(SM20Unit::Mem, 0x22);
e.set_pred_dst2(8..10, 58..59, self.in_bounds);
e.set_dst(14..20, self.dst);
e.set_pred_dst2(8..10, 58..59, &self.in_bounds);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, self.src);
assert!(self.lane.src_mod.is_none());
@@ -1677,8 +1677,8 @@ impl SM20Op for OpPSetP {
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.set_opcode(SM20Unit::Move, 0x3);
e.set_pred_dst(14..17, self.dsts[1]);
e.set_pred_dst(17..20, self.dsts[0]);
e.set_pred_dst(14..17, &self.dsts[1]);
e.set_pred_dst(17..20, &self.dsts[0]);
e.set_pred_src(20..24, self.srcs[0]);
e.set_pred_src(26..30, self.srcs[1]);
e.set_pred_set_op(30..32, self.ops[0]);
@@ -1763,7 +1763,7 @@ impl SM20Op for OpTex {
e.set_field(7..9, 0x2_u8); // TODO: .p
e.set_bit(9, self.nodep);
e.set_dst(14..20, self.dsts[0]);
e.set_dst(14..20, &self.dsts[0]);
assert!(self.dsts[1].is_none());
assert!(self.fault.is_none());
e.set_reg_src(20..26, self.srcs[0]);
@@ -1801,7 +1801,7 @@ impl SM20Op for OpTld {
e.set_field(7..9, 0x2_u8); // TODO: .p
e.set_bit(9, self.nodep);
e.set_dst(14..20, self.dsts[0]);
e.set_dst(14..20, &self.dsts[0]);
assert!(self.dsts[1].is_none());
assert!(self.fault.is_none());
e.set_reg_src(20..26, self.srcs[0]);
@@ -1848,7 +1848,7 @@ impl SM20Op for OpTld4 {
e.set_field(5..7, self.comp);
e.set_field(7..9, 0x2_u8); // TODO: .p
e.set_bit(9, self.nodep);
e.set_dst(14..20, self.dsts[0]);
e.set_dst(14..20, &self.dsts[0]);
assert!(self.dsts[1].is_none());
assert!(self.fault.is_none());
e.set_reg_src(20..26, self.srcs[0]);
@@ -1893,7 +1893,7 @@ impl SM20Op for OpTmml {
e.set_field(7..9, 0x2_u8); // TODO: .p
e.set_bit(9, self.nodep);
e.set_dst(14..20, self.dsts[0]);
e.set_dst(14..20, &self.dsts[0]);
assert!(self.dsts[1].is_none());
e.set_reg_src(20..26, self.srcs[0]);
e.set_reg_src(26..32, self.srcs[1]);
@@ -1927,7 +1927,7 @@ impl SM20Op for OpTxd {
e.set_field(7..9, 0x2_u8); // TODO: .p
e.set_bit(9, self.nodep);
e.set_dst(14..20, self.dsts[0]);
e.set_dst(14..20, &self.dsts[0]);
assert!(self.dsts[1].is_none());
e.set_reg_src(20..26, self.srcs[0]);
e.set_reg_src(26..32, self.srcs[1]);
@@ -1962,7 +1962,7 @@ impl SM20Op for OpTxq {
e.set_field(7..9, 0x2_u8); // TODO: .p
e.set_bit(9, self.nodep);
e.set_dst(14..20, self.dsts[0]);
e.set_dst(14..20, &self.dsts[0]);
assert!(self.dsts[1].is_none());
e.set_reg_src(20..26, self.src);
e.set_reg_src(26..32, 0.into());
@@ -2060,7 +2060,7 @@ impl SM20Op for OpLd {
}
e.set_mem_type(5..8, self.access.mem_type);
// 8..9: cache hints (.ca, .cg, .lu, .cv)
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, self.addr);
}
}
@@ -2092,7 +2092,7 @@ impl SM20Op for OpLdc {
LdcMode::IndexedSegmentedLinear => 3_u8,
},
);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, self.offset);
e.set_field(26..42, cb.offset);
e.set_field(42..47, cb_idx);
@@ -2220,7 +2220,7 @@ impl SM20Op for OpAtom {
if self.dst.is_none() {
e.set_field(26..58, self.addr_offset);
} else {
e.set_dst(43..49, self.dst);
e.set_dst(43..49, &self.dst);
e.set_field(26..43, self.addr_offset & 0x1ffff);
e.set_field(55..58, self.addr_offset >> 17);
}
@@ -2260,7 +2260,7 @@ impl SM20Op for OpALd {
e.set_bit(8, self.patch);
e.set_bit(9, self.output);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, self.offset);
e.set_reg_src(26..32, self.vtx);
e.set_field(32..42, self.addr);
@@ -2312,7 +2312,7 @@ impl SM20Op for OpIpa {
InterpLoc::Offset => 2_u8,
},
);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, 0.into()); // indirect
e.set_reg_src(26..32, self.inv_w);
e.set_reg_src(49..55, self.offset);
@@ -2352,7 +2352,7 @@ impl SM20Op for OpCCtl {
}
},
);
e.set_dst(14..20, Dst::None);
e.set_dst(14..20, &Dst::None);
e.set_reg_src(20..26, self.addr);
e.set_field(26..28, 0); // 1: .u, 2: .c: 3: .i
@@ -2506,7 +2506,7 @@ impl SM20Op for OpBar {
e.set_bit(46, false); // src1_is_imm
e.set_bit(47, false); // src0_is_imm
e.set_pred_src(49..53, true.into());
e.set_pred_dst(53..56, Dst::None);
e.set_pred_dst(53..56, &Dst::None);
}
}
@@ -2529,7 +2529,7 @@ impl SM20Op for OpIsberd {
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.set_opcode(SM20Unit::Tex, 0x0);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, self.idx);
e.set_field(26..42, 0_u16); // offset
}
@@ -2575,10 +2575,10 @@ impl SM20Op for OpPixLd {
other => panic!("Unsupported PixVal: {other}"),
},
);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_reg_src(20..26, 0.into());
e.set_field(26..34, 0_u16); // offset
e.set_pred_dst(53..56, Dst::None);
e.set_pred_dst(53..56, &Dst::None);
}
}
@@ -2589,7 +2589,7 @@ impl SM20Op for OpS2R {
fn encode(&self, e: &mut SM20Encoder<'_>) {
e.set_opcode(SM20Unit::Move, 0xb);
e.set_dst(14..20, self.dst);
e.set_dst(14..20, &self.dst);
e.set_field(26..36, self.idx);
}
}
@@ -2609,9 +2609,9 @@ impl SM20Op for OpVote {
VoteOp::Eq => 2_u8,
},
);
e.set_dst(14..20, self.ballot);
e.set_dst(14..20, &self.ballot);
e.set_pred_src(20..24, self.pred);
e.set_pred_dst(54..57, self.vote);
e.set_pred_dst(54..57, &self.vote);
}
}
src/nouveau/compiler/nak/sm50.rs
+78 -78
View File
@@ -302,12 +302,12 @@ impl SM50Encoder<'_> {
self.set_bit(not_bit, src.src_mod.is_bnot());
}
fn set_pred_dst(&mut self, range: Range<usize>, dst: Dst) {
fn set_pred_dst(&mut self, range: Range<usize>, dst: &Dst) {
match dst {
Dst::None => {
self.set_pred_reg(range, true_reg());
}
Dst::Reg(reg) => self.set_pred_reg(range, reg),
Dst::Reg(reg) => self.set_pred_reg(range, *reg),
_ => panic!("Not a register"),
}
}
@@ -323,10 +323,10 @@ impl SM50Encoder<'_> {
self.set_bit(not_bit, not ^ src.src_mod.is_bnot());
}
fn set_dst(&mut self, dst: Dst) {
fn set_dst(&mut self, dst: &Dst) {
let reg = match dst {
Dst::None => zero_reg(),
Dst::Reg(reg) => reg,
Dst::Reg(reg) => *reg,
_ => panic!("invalid dst {dst}"),
};
self.set_reg(0..8, reg);
@@ -501,7 +501,7 @@ impl SM50Op for OpFAdd {
fn encode(&self, e: &mut SM50Encoder<'_>) {
if let Some(imm32) = self.srcs[1].as_imm_not_f20() {
e.set_opcode(0x0800);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_fmod_src(8..16, 54, 56, self.srcs[0]);
e.set_src_imm32(20..52, imm32);
assert!(self.rnd_mode == FRndMode::NearestEven);
@@ -524,7 +524,7 @@ impl SM50Op for OpFAdd {
src => panic!("Invalid fadd src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_fmod_src(8..16, 46, 48, self.srcs[0]);
e.set_rnd_mode(39..41, self.rnd_mode);
@@ -594,7 +594,7 @@ impl SM50Op for OpFFma {
src => panic!("Invalid ffma src2: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src_ref(8..16, self.srcs[0].src_ref);
e.set_bit(48, fneg_fmul);
@@ -635,7 +635,7 @@ impl SM50Op for OpFMnMx {
}
e.set_reg_fmod_src(8..16, 46, 48, self.srcs[0]);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_pred_src(39..42, 42, self.min);
e.set_bit(44, self.ftz);
}
@@ -706,7 +706,7 @@ impl SM50Op for OpFMul {
}
e.set_reg_src_ref(8..16, self.srcs[0].src_ref);
e.set_dst(self.dst);
e.set_dst(&self.dst);
}
}
@@ -734,7 +734,7 @@ impl SM50Op for OpRro {
src => panic!("Invalid rro src: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_field(
39..40,
match self.op {
@@ -753,7 +753,7 @@ impl SM50Op for OpMuFu {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0x5080);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_fmod_src(8..16, 46, 48, self.src);
e.set_field(
@@ -864,7 +864,7 @@ impl SM50Op for OpFSet {
e.set_float_cmp_op(48..52, self.cmp_op);
e.set_bit(52, true); // bool float
e.set_bit(55, self.ftz);
e.set_dst(self.dst);
e.set_dst(&self.dst);
}
}
@@ -897,8 +897,8 @@ impl SM50Op for OpFSetP {
src => panic!("Invalid fsetp src1: {src}"),
}
e.set_pred_dst(3..6, self.dst);
e.set_pred_dst(0..3, Dst::None); // dst1
e.set_pred_dst(3..6, &self.dst);
e.set_pred_dst(0..3, &Dst::None); // dst1
e.set_reg_fmod_src(8..16, 7, 43, self.srcs[0]);
e.set_pred_src(39..42, 42, self.accum);
e.set_pred_set_op(45..47, self.set_op);
@@ -917,7 +917,7 @@ impl SM50Op for OpFSwzAdd {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0x50f8);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.srcs[0]);
e.set_reg_src(20..28, self.srcs[1]);
@@ -976,7 +976,7 @@ impl SM50Op for OpDAdd {
src => panic!("Invalid dadd src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_fmod_src(8..16, 46, 48, self.srcs[0]);
e.set_rnd_mode(39..41, self.rnd_mode);
}
@@ -1038,7 +1038,7 @@ impl SM50Op for OpDFma {
src => panic!("Invalid dfma src2: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src_ref(8..16, self.srcs[0].src_ref);
e.set_bit(48, fneg_fmul);
@@ -1076,7 +1076,7 @@ impl SM50Op for OpDMnMx {
}
e.set_reg_fmod_src(8..16, 46, 48, self.srcs[0]);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_pred_src(39..42, 42, self.min);
}
}
@@ -1116,7 +1116,7 @@ impl SM50Op for OpDMul {
src => panic!("Invalid dmul src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src_ref(8..16, self.srcs[0].src_ref);
e.set_rnd_mode(39..41, self.rnd_mode);
@@ -1153,8 +1153,8 @@ impl SM50Op for OpDSetP {
src => panic!("Invalid dsetp src1: {src}"),
}
e.set_pred_dst(3..6, self.dst);
e.set_pred_dst(0..3, Dst::None); // dst1
e.set_pred_dst(3..6, &self.dst);
e.set_pred_dst(0..3, &Dst::None); // dst1
e.set_pred_src(39..42, 42, self.accum);
e.set_pred_set_op(45..47, self.set_op);
e.set_float_cmp_op(48..52, self.cmp_op);
@@ -1195,7 +1195,7 @@ impl SM50Op for OpBfe {
}
e.set_reg_src(8..16, self.base);
e.set_dst(self.dst);
e.set_dst(&self.dst);
}
}
@@ -1223,7 +1223,7 @@ impl SM50Op for OpFlo {
src => panic!("Invalid flo src: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_bit(40, self.src.src_mod.is_bnot());
e.set_bit(48, self.signed);
e.set_bit(41, self.return_shift_amount);
@@ -1253,7 +1253,7 @@ impl SM50Op for OpIAdd2 {
self.srcs[0].src_mod.is_none() || self.srcs[1].src_mod.is_none()
);
let carry_out = match self.carry_out {
let carry_out = match &self.carry_out {
Dst::Reg(reg) if reg.file() == RegFile::Carry => true,
Dst::None => false,
dst => panic!("Invalid iadd carry_out: {dst}"),
@@ -1262,7 +1262,7 @@ impl SM50Op for OpIAdd2 {
if let Some(imm32) = self.srcs[1].as_imm_not_i20() {
e.set_opcode(0x1c00);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_ineg_src(8..16, 56, self.srcs[0]);
e.set_src_imm32(20..52, imm32);
@@ -1286,7 +1286,7 @@ impl SM50Op for OpIAdd2 {
src => panic!("Invalid iadd src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_ineg_src(8..16, 49, self.srcs[0]);
e.set_bit(43, false); // .X
@@ -1309,7 +1309,7 @@ impl SM50Op for OpIAdd2X {
src => panic!("Invalid iadd.x carry_in: {src}"),
}
let carry_out = match self.carry_out {
let carry_out = match &self.carry_out {
Dst::Reg(reg) if reg.file() == RegFile::Carry => true,
Dst::None => false,
dst => panic!("Invalid iadd.x carry_out: {dst}"),
@@ -1318,7 +1318,7 @@ impl SM50Op for OpIAdd2X {
if let Some(imm32) = self.srcs[1].as_imm_not_i20() {
e.set_opcode(0x1c00);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_bnot_src(8..16, 56, self.srcs[0]);
e.set_src_imm32(20..52, imm32);
@@ -1342,7 +1342,7 @@ impl SM50Op for OpIAdd2X {
src => panic!("Invalid iadd.x src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_bnot_src(8..16, 49, self.srcs[0]);
e.set_bit(43, true); // .X
@@ -1399,7 +1399,7 @@ impl SM50Op for OpIMad {
src => panic!("Invalid imad src2: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.srcs[0]);
e.set_bit(48, self.signed); // src0 signed
@@ -1452,7 +1452,7 @@ impl SM50Op for OpIMul {
e.set_bit(41, self.signed[1]);
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.srcs[0]);
}
}
@@ -1484,7 +1484,7 @@ impl SM50Op for OpIMnMx {
src => panic!("Invalid imnmx src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.srcs[0]);
e.set_pred_src(39..42, 42, self.min);
e.set_bit(47, false); // .CC
@@ -1527,8 +1527,8 @@ impl SM50Op for OpISetP {
src => panic!("Invalid isetp src1: {src}"),
}
e.set_pred_dst(0..3, Dst::None); // dst1
e.set_pred_dst(3..6, self.dst);
e.set_pred_dst(0..3, &Dst::None); // dst1
e.set_pred_dst(3..6, &self.dst);
e.set_reg_src(8..16, self.srcs[0]);
e.set_pred_src(39..42, 42, self.accum);
@@ -1569,7 +1569,7 @@ impl SM50Op for OpLop2 {
if let Some(imm32) = self.srcs[1].as_imm_not_i20() {
e.set_opcode(0x0400);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_bnot_src(8..16, 55, self.srcs[0]);
e.set_src_imm32(20..52, imm32);
e.set_field(
@@ -1602,7 +1602,7 @@ impl SM50Op for OpLop2 {
src => panic!("Invalid lop2 src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_bnot_src(8..16, 39, self.srcs[0]);
e.set_field(
@@ -1615,7 +1615,7 @@ impl SM50Op for OpLop2 {
},
);
e.set_pred_dst(48..51, Dst::None);
e.set_pred_dst(48..51, &Dst::None);
}
}
}
@@ -1644,7 +1644,7 @@ impl SM50Op for OpPopC {
src => panic!("Invalid popc src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
}
}
@@ -1682,7 +1682,7 @@ impl SM50Op for OpShf {
},
);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.low);
e.set_reg_src(39..47, self.high);
@@ -1707,7 +1707,7 @@ impl SM50Op for OpShl {
}
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.src);
match &self.shift.src_ref {
SrcRef::Zero | SrcRef::Reg(_) => {
@@ -1737,7 +1737,7 @@ impl SM50Op for OpShr {
}
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.src);
match &self.shift.src_ref {
SrcRef::Zero | SrcRef::Reg(_) => {
@@ -1798,7 +1798,7 @@ impl SM50Op for OpF2F {
e.set_bit(44, self.ftz);
e.set_bit(50, false); // saturate
e.set_dst(self.dst);
e.set_dst(&self.dst);
}
}
@@ -1826,7 +1826,7 @@ impl SM50Op for OpF2I {
src => panic!("Invalid f2i src: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
// We can't span 32 bits
assert!(
@@ -1867,7 +1867,7 @@ impl SM50Op for OpI2F {
src => panic!("Invalid i2f src: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
// We can't span 32 bits
assert!(
@@ -1907,7 +1907,7 @@ impl SM50Op for OpI2I {
src => panic!("Invalid i2i src: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
// We can't span 32 bits
assert!(
@@ -1952,7 +1952,7 @@ impl SM50Op for OpMov {
src => panic!("Invalid mov src: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
}
}
@@ -1981,7 +1981,7 @@ impl SM50Op for OpPrmt {
src => panic!("Invalid prmt selector: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.srcs[0]);
e.set_reg_src(39..47, self.srcs[1]);
e.set_field(
@@ -2027,7 +2027,7 @@ impl SM50Op for OpSel {
src => panic!("Invalid sel src1: {src}"),
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.srcs[0]);
e.set_pred_src(39..42, 42, self.cond);
}
@@ -2044,8 +2044,8 @@ impl SM50Op for OpShfl {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xef10);
e.set_dst(self.dst);
e.set_pred_dst(48..51, self.in_bounds);
e.set_dst(&self.dst);
e.set_pred_dst(48..51, &self.in_bounds);
e.set_reg_src(8..16, self.src);
match &self.lane.src_ref {
@@ -2091,8 +2091,8 @@ impl SM50Op for OpPSetP {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0x5090);
e.set_pred_dst(3..6, self.dsts[0]);
e.set_pred_dst(0..3, self.dsts[1]);
e.set_pred_dst(3..6, &self.dsts[0]);
e.set_pred_dst(0..3, &self.dsts[1]);
e.set_pred_src(12..15, 15, self.srcs[0]);
e.set_pred_src(29..32, 32, self.srcs[1]);
@@ -2177,7 +2177,7 @@ impl SM50Op for OpTex {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
assert!(self.dsts[1].is_none());
assert!(self.fault.is_none());
e.set_reg_src(8..16, self.srcs[0]);
@@ -2210,7 +2210,7 @@ impl SM50Op for OpTld {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
assert!(self.dsts[1].is_none());
assert!(self.fault.is_none());
e.set_reg_src(8..16, self.srcs[0]);
@@ -2258,7 +2258,7 @@ impl SM50Op for OpTld4 {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
assert!(self.dsts[1].is_none());
assert!(self.fault.is_none());
e.set_reg_src(8..16, self.srcs[0]);
@@ -2291,7 +2291,7 @@ impl SM50Op for OpTmml {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
assert!(self.dsts[1].is_none());
e.set_reg_src(8..16, self.srcs[0]);
e.set_reg_src(20..28, self.srcs[1]);
@@ -2322,7 +2322,7 @@ impl SM50Op for OpTxd {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
assert!(self.dsts[1].is_none());
assert!(self.fault.is_none());
e.set_reg_src(8..16, self.srcs[0]);
@@ -2354,7 +2354,7 @@ impl SM50Op for OpTxq {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
assert!(self.dsts[1].is_none());
e.set_reg_src(8..16, self.src);
@@ -2475,7 +2475,7 @@ impl SM50Op for OpSuLd {
},
);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.coord);
e.set_reg_src(39..47, self.handle);
@@ -2564,7 +2564,7 @@ impl SM50Op for OpSuAtom {
// image.
e.set_bit(52, true); // .D
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(20..28, self.data);
e.set_reg_src(8..16, self.coord);
@@ -2584,7 +2584,7 @@ impl SM50Op for OpLd {
MemSpace::Shared => 0xef48,
});
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.addr);
e.set_field(20..44, self.offset);
@@ -2609,7 +2609,7 @@ impl SM50Op for OpLdc {
e.set_opcode(0xef90);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.offset);
e.set_field(20..36, cb.offset);
e.set_field(36..41, cb_idx);
@@ -2707,7 +2707,7 @@ impl SM50Op for OpAtom {
} else if let AtomOp::CmpExch(cmp_src) = self.atom_op {
e.set_opcode(0xee00);
e.set_dst(self.dst);
e.set_dst(&self.dst);
// TODO: These are all supported by the disassembler but
// only the packed layout appears to be supported by real
@@ -2736,7 +2736,7 @@ impl SM50Op for OpAtom {
} else {
e.set_opcode(0xed00);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(20..28, self.data);
let data_type = match self.atom_type {
@@ -2800,7 +2800,7 @@ impl SM50Op for OpAtom {
e.set_atom_op(52..56, self.atom_op);
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.addr);
assert_eq!(self.addr_offset % 4, 0);
e.set_field(30..52, self.addr_offset / 4);
@@ -2817,14 +2817,14 @@ impl SM50Op for OpAL2P {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xefa0);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.offset);
e.set_field(20..31, self.addr);
e.set_bit(32, self.output);
e.set_field(47..49, 0_u8); // comps
e.set_pred_dst(44..47, Dst::None);
e.set_pred_dst(44..47, &Dst::None);
}
}
@@ -2836,7 +2836,7 @@ impl SM50Op for OpALd {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xefd8);
e.set_dst(self.dst);
e.set_dst(&self.dst);
if self.phys {
assert!(!self.patch);
assert!(self.offset.src_ref.as_reg().is_some());
@@ -2881,7 +2881,7 @@ impl SM50Op for OpIpa {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xe000);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, 0.into()); // addr
e.set_reg_src(20..28, self.inv_w);
e.set_reg_src(39..47, self.offset);
@@ -2889,7 +2889,7 @@ impl SM50Op for OpIpa {
assert!(self.addr % 4 == 0);
e.set_field(28..38, self.addr);
e.set_bit(38, false); // .IDX
e.set_pred_dst(47..50, Dst::None); // TODO: What is this for?
e.set_pred_dst(47..50, &Dst::None); // TODO: What is this for?
e.set_bit(51, false); // .SAT
e.set_field(
52..54,
@@ -3119,7 +3119,7 @@ impl SM50Op for OpCS2R {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0x50c8);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_field(20..28, self.idx);
}
}
@@ -3131,7 +3131,7 @@ impl SM50Op for OpIsberd {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xefd0);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, self.idx);
}
}
@@ -3167,7 +3167,7 @@ impl SM50Op for OpPixLd {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xefe8);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(8..16, 0.into());
e.set_field(
31..34,
@@ -3180,7 +3180,7 @@ impl SM50Op for OpPixLd {
other => panic!("Unsupported PixVal: {other}"),
},
);
e.set_pred_dst(45..48, Dst::None);
e.set_pred_dst(45..48, &Dst::None);
}
}
@@ -3191,7 +3191,7 @@ impl SM50Op for OpS2R {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0xf0c8);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_field(20..28, self.idx);
}
}
@@ -3204,8 +3204,8 @@ impl SM50Op for OpVote {
fn encode(&self, e: &mut SM50Encoder<'_>) {
e.set_opcode(0x50d8);
e.set_dst(self.ballot);
e.set_pred_dst(45..48, self.vote);
e.set_dst(&self.ballot);
e.set_pred_dst(45..48, &self.vote);
e.set_pred_src(39..42, 42, self.pred);
e.set_field(
@@ -3253,7 +3253,7 @@ impl SM50Op for OpOut {
);
e.set_reg_src(8..16, self.handle);
e.set_dst(self.dst);
e.set_dst(&self.dst);
}
}
src/nouveau/compiler/nak/sm70_encode.rs
+78 -78
View File
@@ -94,10 +94,10 @@ impl SM70Encoder<'_> {
}
}
fn set_pred_dst(&mut self, range: Range<usize>, dst: Dst) {
fn set_pred_dst(&mut self, range: Range<usize>, dst: &Dst) {
match dst {
Dst::None => self.set_pred_reg(range, self.true_reg(RegFile::Pred)),
Dst::Reg(reg) => self.set_pred_reg(range, reg),
Dst::Reg(reg) => self.set_pred_reg(range, *reg),
_ => panic!("Not a register"),
}
}
@@ -161,18 +161,18 @@ impl SM70Encoder<'_> {
self.set_bit(15, pred.pred_inv);
}
fn set_dst(&mut self, dst: Dst) {
fn set_dst(&mut self, dst: &Dst) {
match dst {
Dst::None => self.set_reg(16..24, self.zero_reg(RegFile::GPR)),
Dst::Reg(reg) => self.set_reg(16..24, reg),
Dst::Reg(reg) => self.set_reg(16..24, *reg),
_ => panic!("Not a register"),
}
}
fn set_udst(&mut self, dst: Dst) {
fn set_udst(&mut self, dst: &Dst) {
match dst {
Dst::None => self.set_ureg(16..24, self.zero_reg(RegFile::UGPR)),
Dst::Reg(reg) => self.set_ureg(16..24, reg),
Dst::Reg(reg) => self.set_ureg(16..24, *reg),
_ => panic!("Not a register"),
}
}
@@ -184,7 +184,7 @@ impl SM70Encoder<'_> {
self.set_field(range, reg.base_idx());
}
fn set_bar_dst(&mut self, range: Range<usize>, dst: Dst) {
fn set_bar_dst(&mut self, range: Range<usize>, dst: &Dst) {
self.set_bar_reg(range, *dst.as_reg().unwrap());
}
@@ -259,7 +259,7 @@ fn src_mod_is_bnot(src_mod: SrcMod) -> bool {
}
}
fn dst_is_bar(dst: Dst) -> bool {
fn dst_is_bar(dst: &Dst) -> bool {
match dst {
Dst::None => false,
Dst::SSA(ssa) => ssa.file().unwrap() == RegFile::Bar,
@@ -456,7 +456,7 @@ impl SM70Encoder<'_> {
is_fp16_alu: bool,
) {
if let Some(dst) = dst {
self.set_dst(*dst);
self.set_dst(dst);
}
let src0 = ALUSrc::from_src(self, src0, false);
@@ -541,7 +541,7 @@ impl SM70Encoder<'_> {
src2: Option<&Src>,
) {
if let Some(dst) = dst {
self.set_udst(*dst);
self.set_udst(dst);
}
let src0 = ALUSrc::from_src(self, src0, true);
@@ -856,8 +856,8 @@ impl SM70Op for OpFSetP {
e.set_float_cmp_op(76..80, self.cmp_op);
e.set_bit(80, self.ftz);
e.set_pred_dst(81..84, self.dst);
e.set_pred_dst(84..87, Dst::None); // dst1
e.set_pred_dst(81..84, &self.dst);
e.set_pred_dst(84..87, &Dst::None); // dst1
e.set_pred_src(87..90, 90, self.accum);
}
@@ -873,7 +873,7 @@ impl SM70Op for OpFSwzAdd {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x822);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.srcs[0]);
e.set_reg_src(64..72, self.srcs[1]);
@@ -1018,8 +1018,8 @@ impl SM70Op for OpDSetP {
e.set_pred_set_op(74..76, self.set_op);
e.set_float_cmp_op(76..80, self.cmp_op);
e.set_pred_dst(81..84, self.dst);
e.set_pred_dst(84..87, Dst::None); /* dst1 */
e.set_pred_dst(81..84, &self.dst);
e.set_pred_dst(84..87, &Dst::None); /* dst1 */
e.set_pred_src(87..90, 90, self.accum);
}
@@ -1191,8 +1191,8 @@ impl SM70Op for OpHSetP2 {
e.set_float_cmp_op(76..80, self.cmp_op);
e.set_bit(80, self.ftz);
e.set_pred_dst(81..84, self.dsts[0]);
e.set_pred_dst(84..87, self.dsts[1]);
e.set_pred_dst(81..84, &self.dsts[0]);
e.set_pred_dst(84..87, &self.dsts[1]);
e.set_pred_src(87..90, 90, self.accum);
}
@@ -1282,7 +1282,7 @@ impl SM70Op for OpFlo {
} else {
e.encode_alu(0x100, Some(&self.dst), None, Some(&self.src), None)
};
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
e.set_field(74..75, self.return_shift_amount as u8);
e.set_field(73..74, self.signed as u8);
let not_mod = matches!(self.src.src_mod, SrcMod::BNot);
@@ -1346,8 +1346,8 @@ impl SM70Op for OpIAdd3 {
e.set_pred_src(87..90, 90, false.into());
e.set_pred_src(77..80, 80, false.into());
e.set_pred_dst(81..84, self.overflow[0]);
e.set_pred_dst(84..87, self.overflow[1]);
e.set_pred_dst(81..84, &self.overflow[0]);
e.set_pred_dst(84..87, &self.overflow[1]);
}
}
@@ -1361,7 +1361,7 @@ impl SM70Op for OpIAdd3X {
let val = b.alloc_ssa(gpr);
b.push_op(OpIAdd3X {
srcs: [Src::new_zero(), *src0, Src::new_zero()],
overflow: [Dst::None; 2],
overflow: [Dst::None, Dst::None],
dst: val.into(),
carry: [false.into(); 2],
});
@@ -1407,8 +1407,8 @@ impl SM70Op for OpIAdd3X {
e.set_bit(74, true); // .X
e.set_pred_dst(81..84, self.overflow[0]);
e.set_pred_dst(84..87, self.overflow[1]);
e.set_pred_dst(81..84, &self.overflow[0]);
e.set_pred_dst(84..87, &self.overflow[1]);
}
}
@@ -1480,7 +1480,7 @@ impl SM70Op for OpIMad {
Some(&self.srcs[2]),
)
};
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
e.set_bit(73, self.signed);
}
}
@@ -1512,7 +1512,7 @@ impl SM70Op for OpIMad64 {
Some(&self.srcs[2]),
)
};
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
e.set_bit(73, self.signed);
}
}
@@ -1596,8 +1596,8 @@ impl SM70Op for OpISetP {
e.set_pred_set_op(74..76, self.set_op);
e.set_int_cmp_op(76..79, self.cmp_op);
e.set_pred_dst(81..84, self.dst);
e.set_pred_dst(84..87, Dst::None); // dst1
e.set_pred_dst(81..84, &self.dst);
e.set_pred_dst(84..87, &Dst::None); // dst1
}
}
@@ -1649,7 +1649,7 @@ impl SM70Op for OpLea {
e.set_bit(72, self.intermediate_mod.is_ineg());
e.set_field(75..80, self.shift);
e.set_bit(80, self.dst_high);
e.set_pred_dst(81..84, self.overflow);
e.set_pred_dst(81..84, &self.overflow);
e.set_bit(74, false); // .X
}
}
@@ -1704,7 +1704,7 @@ impl SM70Op for OpLeaX {
e.set_bit(72, self.intermediate_mod.is_bnot());
e.set_field(75..80, self.shift);
e.set_bit(80, self.dst_high);
e.set_pred_dst(81..84, self.overflow);
e.set_pred_dst(81..84, &self.overflow);
e.set_bit(74, true); // .X
}
}
@@ -1981,7 +1981,7 @@ impl SM70Op for OpMov {
fn encode(&self, e: &mut SM70Encoder<'_>) {
if self.is_uniform() {
e.set_opcode(0xc82);
e.set_udst(self.dst);
e.set_udst(&self.dst);
// umov is encoded like a non-uniform ALU op
let src = ALUSrc::from_src(e, Some(&self.src), true);
@@ -2126,8 +2126,8 @@ impl SM70Op for OpShfl {
_ => panic!("Invalid instruction form"),
};
e.set_dst(self.dst);
e.set_pred_dst(81..84, self.in_bounds);
e.set_dst(&self.dst);
e.set_pred_dst(81..84, &self.in_bounds);
e.set_reg_src(24..32, self.src);
e.set_field(
58..60,
@@ -2208,8 +2208,8 @@ impl SM70Op for OpPLop3 {
e.set_field(64..67, self.ops[0].lut & 0x7);
e.set_field(72..77, self.ops[0].lut >> 3);
e.set_pred_dst(81..84, self.dsts[0]);
e.set_pred_dst(84..87, self.dsts[1]);
e.set_pred_dst(81..84, &self.dsts[0]);
e.set_pred_dst(84..87, &self.dsts[1]);
}
}
@@ -2220,9 +2220,9 @@ impl SM70Op for OpR2UR {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x3c2);
e.set_udst(self.dst);
e.set_udst(&self.dst);
e.set_reg_src(24..32, self.src);
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
}
}
@@ -2365,13 +2365,13 @@ impl SM70Op for OpTex {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
if let Dst::Reg(reg) = self.dsts[1] {
e.set_reg(64..72, reg);
} else {
e.set_field(64..72, 255_u8);
}
e.set_pred_dst(81..84, self.fault);
e.set_pred_dst(81..84, &self.fault);
e.set_reg_src(24..32, self.srcs[0]);
e.set_reg_src(32..40, self.srcs[1]);
@@ -2418,13 +2418,13 @@ impl SM70Op for OpTld {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
if let Dst::Reg(reg) = self.dsts[1] {
e.set_reg(64..72, reg);
} else {
e.set_field(64..72, 255_u8);
}
e.set_pred_dst(81..84, self.fault);
e.set_pred_dst(81..84, &self.fault);
e.set_reg_src(24..32, self.srcs[0]);
e.set_reg_src(32..40, self.srcs[1]);
@@ -2472,13 +2472,13 @@ impl SM70Op for OpTld4 {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
if let Dst::Reg(reg) = self.dsts[1] {
e.set_reg(64..72, reg);
} else {
e.set_field(64..72, 255_u8);
}
e.set_pred_dst(81..84, self.fault);
e.set_pred_dst(81..84, &self.fault);
e.set_reg_src(24..32, self.srcs[0]);
e.set_reg_src(32..40, self.srcs[1]);
@@ -2526,7 +2526,7 @@ impl SM70Op for OpTmml {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
if let Dst::Reg(reg) = self.dsts[1] {
e.set_reg(64..72, reg);
} else {
@@ -2569,13 +2569,13 @@ impl SM70Op for OpTxd {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
if let Dst::Reg(reg) = self.dsts[1] {
e.set_reg(64..72, reg);
} else {
e.set_field(64..72, 255_u8);
}
e.set_pred_dst(81..84, self.fault);
e.set_pred_dst(81..84, &self.fault);
e.set_reg_src(24..32, self.srcs[0]);
e.set_reg_src(32..40, self.srcs[1]);
@@ -2614,7 +2614,7 @@ impl SM70Op for OpTxq {
}
}
e.set_dst(self.dsts[0]);
e.set_dst(&self.dsts[0]);
if let Dst::Reg(reg) = self.dsts[1] {
e.set_reg(64..72, reg);
} else {
@@ -2736,10 +2736,10 @@ impl SM70Op for OpSuLd {
}
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.coord);
e.set_reg_src(64..72, self.handle);
e.set_pred_dst(81..84, self.fault);
e.set_pred_dst(81..84, &self.fault);
e.set_image_dim(61..64, self.image_dim);
e.set_mem_order(&self.mem_order);
@@ -2791,11 +2791,11 @@ impl SM70Op for OpSuAtom {
e.set_atom_op(87..91, self.atom_op);
};
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.coord);
e.set_reg_src(32..40, self.data);
e.set_reg_src(64..72, self.handle);
e.set_pred_dst(81..84, self.fault);
e.set_pred_dst(81..84, &self.fault);
e.set_image_dim(61..64, self.image_dim);
e.set_mem_order(&self.mem_order);
@@ -2815,7 +2815,7 @@ impl SM70Op for OpLd {
match self.access.space {
MemSpace::Global(_) => {
e.set_opcode(0x381);
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
e.set_mem_access(&self.access);
}
MemSpace::Local => {
@@ -2843,7 +2843,7 @@ impl SM70Op for OpLd {
}
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.addr);
e.set_field(40..64, self.offset);
}
@@ -2864,13 +2864,13 @@ impl SM70Op for OpLdc {
CBuf::Binding(idx) => {
if self.is_uniform() {
e.set_opcode(0xab9);
e.set_udst(self.dst);
e.set_udst(&self.dst);
assert!(self.offset.is_zero());
assert!(self.mode == LdcMode::Indexed);
} else {
e.set_opcode(0xb82);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.offset);
e.set_field(
@@ -2889,12 +2889,12 @@ impl SM70Op for OpLdc {
CBuf::BindlessUGPR(handle) => {
if self.is_uniform() {
e.set_opcode(0xab9);
e.set_udst(self.dst);
e.set_udst(&self.dst);
assert!(self.offset.is_zero());
} else {
e.set_opcode(0x582);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(64..72, self.offset);
}
@@ -3049,7 +3049,7 @@ impl SM70Op for OpAtom {
e.set_atom_op(87..91, self.atom_op);
}
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
e.set_field(
72..73,
@@ -3093,7 +3093,7 @@ impl SM70Op for OpAtom {
}
}
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.addr);
e.set_field(40..64, self.addr_offset);
e.set_atom_type(self.atom_type);
@@ -3108,7 +3108,7 @@ impl SM70Op for OpAL2P {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x920);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.offset);
e.set_field(40..50, self.addr);
@@ -3125,7 +3125,7 @@ impl SM70Op for OpALd {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x321);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(32..40, self.vtx);
e.set_reg_src(24..32, self.offset);
@@ -3164,7 +3164,7 @@ impl SM70Op for OpIpa {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x326);
e.set_dst(self.dst);
e.set_dst(&self.dst);
assert!(self.addr % 4 == 0);
e.set_field(64..72, self.addr >> 2);
@@ -3193,7 +3193,7 @@ impl SM70Op for OpIpa {
e.set_reg_src(32..40, self.offset);
// TODO: What is this for?
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
}
}
@@ -3204,7 +3204,7 @@ impl SM70Op for OpLdTram {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x3ad);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_ureg(24..32, e.zero_reg(RegFile::UGPR));
assert!(self.addr % 4 == 0);
@@ -3292,8 +3292,8 @@ impl SM70Op for OpBClear {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x355);
e.set_dst(Dst::None);
e.set_bar_dst(24..28, self.dst);
e.set_dst(&Dst::None);
e.set_bar_dst(24..28, &self.dst);
e.set_bit(84, true); // .CLEAR
}
@@ -3305,17 +3305,17 @@ impl SM70Op for OpBMov {
}
fn encode(&self, e: &mut SM70Encoder<'_>) {
if dst_is_bar(self.dst) {
if dst_is_bar(&self.dst) {
e.set_opcode(0x356);
e.set_bar_dst(24..28, self.dst);
e.set_bar_dst(24..28, &self.dst);
e.set_reg_src(32..40, self.src);
e.set_bit(84, self.clear);
} else {
e.set_opcode(0x355);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_bar_src(24..28, self.src);
e.set_bit(84, self.clear);
@@ -3331,7 +3331,7 @@ impl SM70Op for OpBreak {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x942);
assert!(self.bar_in.src_ref.as_reg() == self.bar_out.as_reg());
e.set_bar_dst(16..20, self.bar_out);
e.set_bar_dst(16..20, &self.bar_out);
e.set_pred_src(87..90, 90, self.cond);
}
}
@@ -3344,7 +3344,7 @@ impl SM70Op for OpBSSy {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x945);
assert!(self.bar_in.src_ref.as_reg() == self.bar_out.as_reg());
e.set_bar_dst(16..20, self.bar_out);
e.set_bar_dst(16..20, &self.bar_out);
e.set_rel_offset(34..64, &self.target);
e.set_pred_src(87..90, 90, self.cond);
}
@@ -3436,7 +3436,7 @@ impl SM70Op for OpCS2R {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x805);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_field(72..80, self.idx);
e.set_bit(80, self.dst.as_reg().unwrap().comps() == 2); // .64
}
@@ -3449,7 +3449,7 @@ impl SM70Op for OpIsberd {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x923);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_reg_src(24..32, self.idx);
}
}
@@ -3482,7 +3482,7 @@ impl SM70Op for OpPixLd {
fn encode(&self, e: &mut SM70Encoder<'_>) {
e.set_opcode(0x925);
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_field(
78..81,
match &self.val {
@@ -3494,7 +3494,7 @@ impl SM70Op for OpPixLd {
other => panic!("Unsupported PixVal: {other}"),
},
);
e.set_pred_dst(81..84, Dst::None);
e.set_pred_dst(81..84, &Dst::None);
}
}
@@ -3506,7 +3506,7 @@ impl SM70Op for OpS2R {
fn encode(&self, e: &mut SM70Encoder<'_>) {
assert!(!self.is_uniform());
e.set_opcode(if self.is_uniform() { 0x9c3 } else { 0x919 });
e.set_dst(self.dst);
e.set_dst(&self.dst);
e.set_field(72..80, self.idx);
}
}
@@ -3563,10 +3563,10 @@ impl SM70Op for OpVote {
fn encode(&self, e: &mut SM70Encoder<'_>) {
if self.is_uniform() {
e.set_opcode(0x886);
e.set_udst(self.ballot);
e.set_udst(&self.ballot);
} else {
e.set_opcode(0x806);
e.set_dst(self.ballot);
e.set_dst(&self.ballot);
}
e.set_field(
@@ -3578,7 +3578,7 @@ impl SM70Op for OpVote {
},
);
e.set_pred_dst(81..84, self.vote);
e.set_pred_dst(81..84, &self.vote);
e.set_pred_src(87..90, 90, self.pred);
}
}
src/nouveau/compiler/nak/to_cssa.rs
+2 -2
View File
@@ -333,8 +333,8 @@ impl Function {
}
let tmp = self.ssa_alloc.alloc(file);
pcopy.push(*dst, tmp.into());
*dst = tmp.into();
let old_dst = std::mem::replace(dst, tmp.into());
pcopy.push(old_dst, tmp.into());
}
instrs.push(instr);