AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv: Stop using the misleading round_up_u* functions

Browse Source 
The functions had the same behavior as DIV_ROUND_UP but their names do
not mention a division.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24210>
This commit is contained in:
Konstantin Seurer
2023-07-18 14:39:27 +02:00
committed by Marge Bot
parent 34a12a2727
commit 839d6f9fa2
6 changed files with 12 additions and 24 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/meta/radv_meta_clear.c
+1 -1
View File
@@ -597,7 +597,7 @@ clear_htile_mask(struct radv_cmd_buffer *cmd_buffer, const struct radv_image *im
{
struct radv_device *device = cmd_buffer->device;
struct radv_meta_state *state = &device->meta_state;
uint64_t block_count = round_up_u64(size, 1024);
uint64_t block_count = DIV_ROUND_UP(size, 1024);
struct radv_meta_saved_state saved_state;
struct radv_buffer dst_buffer;
src/amd/vulkan/radv_cmd_buffer.c
+3 -3
View File
@@ -9492,9 +9492,9 @@ radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv
remainder[1] = blocks[1] + cs_block_size[1] - align_u32_npot(blocks[1], cs_block_size[1]);
remainder[2] = blocks[2] + cs_block_size[2] - align_u32_npot(blocks[2], cs_block_size[2]);
blocks[0] = round_up_u32(blocks[0], cs_block_size[0]);
blocks[1] = round_up_u32(blocks[1], cs_block_size[1]);
blocks[2] = round_up_u32(blocks[2], cs_block_size[2]);
blocks[0] = DIV_ROUND_UP(blocks[0], cs_block_size[0]);
blocks[1] = DIV_ROUND_UP(blocks[1], cs_block_size[1]);
blocks[2] = DIV_ROUND_UP(blocks[2], cs_block_size[2]);
for (unsigned i = 0; i < 3; ++i) {
assert(offsets[i] % cs_block_size[i] == 0);
src/amd/vulkan/radv_device_generated_commands.c
+1 -1
View File
@@ -1242,7 +1242,7 @@ radv_prepare_dgc(struct radv_cmd_buffer *cmd_buffer, const VkGeneratedCommandsIn
radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE,
cmd_buffer->device->meta_state.dgc_prepare.p_layout, 0, ds_cnt, ds_writes);
unsigned block_count = MAX2(1, round_up_u32(pGeneratedCommandsInfo->sequencesCount, 64));
unsigned block_count = MAX2(1, DIV_ROUND_UP(pGeneratedCommandsInfo->sequencesCount, 64));
vk_common_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 1);
radv_buffer_finish(&token_buffer);
src/amd/vulkan/radv_image.c
+4 -4
View File
@@ -2216,8 +2216,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
unsigned img_bw = vk_format_get_blockwidth(image->planes[iview->plane_id].format);
unsigned img_bh = vk_format_get_blockheight(image->planes[iview->plane_id].format);
iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
iview->extent.width = DIV_ROUND_UP(iview->extent.width * view_bw, img_bw);
iview->extent.height = DIV_ROUND_UP(iview->extent.height * view_bh, img_bh);
/* Comment ported from amdvlk -
* If we have the following image:
@@ -2257,8 +2257,8 @@ radv_image_view_init(struct radv_image_view *iview, struct radv_device *device,
unsigned lvl_width = radv_minify(image->vk.extent.width, range->baseMipLevel);
unsigned lvl_height = radv_minify(image->vk.extent.height, range->baseMipLevel);
lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
lvl_width = DIV_ROUND_UP(lvl_width * view_bw, img_bw);
lvl_height = DIV_ROUND_UP(lvl_height * view_bh, img_bh);
iview->extent.width = CLAMP(lvl_width << range->baseMipLevel, iview->extent.width,
iview->image->planes[0].surface.u.gfx9.base_mip_width);
src/amd/vulkan/radv_private.h
-12
View File
@@ -185,18 +185,6 @@ radv_is_aligned(uintmax_t n, uintmax_t a)
return (n & (a - 1)) == 0;
}
static inline uint32_t
round_up_u32(uint32_t v, uint32_t a)
{
return (v + a - 1) / a;
}
static inline uint64_t
round_up_u64(uint64_t v, uint64_t a)
{
return (v + a - 1) / a;
}
static inline uint32_t
radv_minify(uint32_t n, uint32_t levels)
{
src/amd/vulkan/radv_queue.c
+3 -3
View File
@@ -635,12 +635,12 @@ radv_emit_graphics_scratch(struct radv_device *device, struct radeon_cmdbuf *cs,
waves /= info->num_se;
radeon_set_context_reg_seq(cs, R_0286E8_SPI_TMPRING_SIZE, 3);
radeon_emit(cs, S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 256)));
radeon_emit(cs, S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, 256)));
radeon_emit(cs, va >> 8); /* SPI_GFX_SCRATCH_BASE_LO */
radeon_emit(cs, va >> 40); /* SPI_GFX_SCRATCH_BASE_HI */
} else {
radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
S_0286E8_WAVES(waves) | S_0286E8_WAVESIZE(DIV_ROUND_UP(size_per_wave, 1024)));
}
}
@@ -679,7 +679,7 @@ radv_emit_compute_scratch(struct radv_device *device, struct radeon_cmdbuf *cs,
radeon_set_sh_reg(
cs, R_00B860_COMPUTE_TMPRING_SIZE,
S_00B860_WAVES(waves) | S_00B860_WAVESIZE(round_up_u32(size_per_wave, info->gfx_level >= GFX11 ? 256 : 1024)));
S_00B860_WAVES(waves) | S_00B860_WAVESIZE(DIV_ROUND_UP(size_per_wave, info->gfx_level >= GFX11 ? 256 : 1024)));
}
static void