r300_fragprog: Use less complex instructions
MOV, ADD and MUL do not fit the hardware as well as MAD, but they are less complex and thus leave more room for future optimizations.
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@@ -89,21 +89,15 @@ static GLboolean transform_TEX(
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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tgt->Opcode = OPCODE_MAD;
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tgt->Opcode = OPCODE_MOV;
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tgt->DstReg = inst.DstReg;
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tgt->SrcReg[0].File = PROGRAM_BUILTIN;
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tgt->SrcReg[0].Swizzle = SWIZZLE_0000;
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tgt->SrcReg[1].File = PROGRAM_BUILTIN;
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tgt->SrcReg[1].Swizzle = SWIZZLE_0000;
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tgt->SrcReg[2].File = PROGRAM_BUILTIN;
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tgt->SrcReg[2].Swizzle = comparefunc == GL_ALWAYS ? SWIZZLE_1111 : SWIZZLE_0000;
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tgt->SrcReg[0].Swizzle = comparefunc == GL_ALWAYS ? SWIZZLE_1111 : SWIZZLE_0000;
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return GL_TRUE;
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}
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int tempreg = radeonCompilerAllocateTemporary(context->compiler);
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inst.DstReg.File = PROGRAM_TEMPORARY;
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inst.DstReg.Index = tempreg;
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inst.DstReg.Index = radeonCompilerAllocateTemporary(context->compiler);
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inst.DstReg.WriteMask = WRITEMASK_XYZW;
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}
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@@ -129,14 +123,12 @@ static GLboolean transform_TEX(
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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tgt->Opcode = OPCODE_MAD;
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tgt->Opcode = OPCODE_MUL;
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tgt->DstReg.File = PROGRAM_TEMPORARY;
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tgt->DstReg.Index = tempreg;
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tgt->SrcReg[0] = inst.SrcReg[0];
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tgt->SrcReg[1].File = PROGRAM_STATE_VAR;
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tgt->SrcReg[1].Index = factor_index;
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tgt->SrcReg[2].File = PROGRAM_BUILTIN;
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tgt->SrcReg[2].Swizzle = SWIZZLE_0000;
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reset_srcreg(&inst.SrcReg[0]);
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inst.SrcReg[0].File = PROGRAM_TEMPORARY;
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@@ -153,14 +145,10 @@ static GLboolean transform_TEX(
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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tgt->Opcode = OPCODE_MAD;
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tgt->Opcode = OPCODE_MOV;
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tgt->DstReg.File = PROGRAM_TEMPORARY;
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tgt->DstReg.Index = tempreg;
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tgt->SrcReg[0] = inst.SrcReg[0];
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tgt->SrcReg[1].File = PROGRAM_BUILTIN;
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tgt->SrcReg[1].Swizzle = SWIZZLE_1111;
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tgt->SrcReg[2].File = PROGRAM_BUILTIN;
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tgt->SrcReg[2].Swizzle = SWIZZLE_0000;
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reset_srcreg(&inst.SrcReg[0]);
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inst.SrcReg[0].File = PROGRAM_TEMPORARY;
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@@ -191,7 +179,7 @@ static GLboolean transform_TEX(
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 2);
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tgt[0].Opcode = OPCODE_MAD;
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tgt[0].Opcode = OPCODE_ADD;
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tgt[0].DstReg = inst.DstReg;
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tgt[0].DstReg.WriteMask = orig_inst->DstReg.WriteMask;
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tgt[0].SrcReg[0].File = PROGRAM_TEMPORARY;
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@@ -200,10 +188,8 @@ static GLboolean transform_TEX(
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tgt[0].SrcReg[0].Swizzle = MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z);
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else if (depthmode == 2) /* GL_ALPHA */
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tgt[0].SrcReg[0].Swizzle = SWIZZLE_WWWW;
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tgt[0].SrcReg[1].File = PROGRAM_BUILTIN;
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tgt[0].SrcReg[1].Swizzle = SWIZZLE_1111;
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tgt[0].SrcReg[2] = inst.SrcReg[0];
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tgt[0].SrcReg[2].Swizzle = SWIZZLE_ZZZZ;
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tgt[0].SrcReg[1] = inst.SrcReg[0];
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tgt[0].SrcReg[1].Swizzle = SWIZZLE_ZZZZ;
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/* Recall that SrcReg[0] is tex, SrcReg[2] is r and:
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* r < tex <=> -tex+r < 0
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@@ -211,7 +197,7 @@ static GLboolean transform_TEX(
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if (comparefunc == GL_LESS || comparefunc == GL_GEQUAL)
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tgt[0].SrcReg[0].NegateBase = tgt[0].SrcReg[0].NegateBase ^ NEGATE_XYZW;
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else
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tgt[0].SrcReg[2].NegateBase = tgt[0].SrcReg[2].NegateBase ^ NEGATE_XYZW;
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tgt[0].SrcReg[1].NegateBase = tgt[0].SrcReg[1].NegateBase ^ NEGATE_XYZW;
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tgt[1].Opcode = OPCODE_CMP;
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tgt[1].DstReg = orig_inst->DstReg;
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@@ -231,14 +217,10 @@ static GLboolean transform_TEX(
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tgt = radeonClauseInsertInstructions(context->compiler, context->dest,
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context->dest->NumInstructions, 1);
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tgt->Opcode = OPCODE_MAD;
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tgt->Opcode = OPCODE_MOV;
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tgt->DstReg = orig_inst->DstReg;
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tgt->SrcReg[0].File = PROGRAM_TEMPORARY;
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tgt->SrcReg[0].Index = inst.DstReg.Index;
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tgt->SrcReg[1].File = PROGRAM_BUILTIN;
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tgt->SrcReg[1].Swizzle = SWIZZLE_1111;
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tgt->SrcReg[2].File = PROGRAM_BUILTIN;
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tgt->SrcReg[2].Swizzle = SWIZZLE_0000;
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}
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return GL_TRUE;
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