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freedreno/a6xx: The great register renaming

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Align register names to internal docs to avoid having to mentally remap
register names between the names we invented over the years and what
they are actually called.

Signed-off-by: Rob Clark <rob.clark@oss.qualcomm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35803>
This commit is contained in:
Rob Clark
2025-06-19 07:32:34 -07:00
committed by Marge Bot
parent a8c052ca9d
commit 7fd99c88b9
42 changed files with 13765 additions and 13767 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/.gitlab-ci/reference/crash.log
+1550 -1550
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src/freedreno/.gitlab-ci/reference/crash_prefetch.log
+7124 -7124
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src/freedreno/.gitlab-ci/reference/dEQP-VK.draw.indirect_draw.indexed.indirect_draw_count.triangle_list.log
+520 -520
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src/freedreno/.gitlab-ci/reference/fd-clouds.log
+762 -762
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src/freedreno/.gitlab-ci/reference/prefetch-test.log
+1761 -1761
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src/freedreno/common/freedreno_dev_info.h
+2 -2
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@@ -174,7 +174,7 @@ struct fd_dev_info {
/* see enum a6xx_ccu_cache_size */
uint32_t gmem_ccu_color_cache_fraction;
/* Corresponds to HLSQ_CONTROL_1_REG::PRIMALLOCTHRESHOLD */
/* Corresponds to SP_LB_PARAM_LIMIT::PRIMALLOCTHRESHOLD */
uint32_t prim_alloc_threshold;
uint32_t vs_max_inputs_count;
@@ -239,7 +239,7 @@ struct fd_dev_info {
uint32_t VPC_DBG_ECO_CNTL;
uint32_t UCHE_UNKNOWN_0E12;
uint32_t RB_UNKNOWN_8E06;
uint32_t RB_CCU_DBG_ECO_CNTL;
} magic;
struct {
src/freedreno/common/freedreno_devices.py
+33 -33
View File
@@ -865,7 +865,7 @@ add_gpus([
SP_DBG_ECO_CNTL = 0x0,
RB_DBG_ECO_CNTL = 0x100000,
RB_DBG_ECO_CNTL_blit = 0x100000,
HLSQ_DBG_ECO_CNTL = 0,
HLSQ_DBG_ECO_CNTL = 0x02000000,
RB_UNKNOWN_8E01 = 0x1,
VPC_DBG_ECO_CNTL = 0x0,
UCHE_UNKNOWN_0E12 = 0x1,
@@ -985,22 +985,22 @@ a730_magic_regs = dict(
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x3200000,
RB_UNKNOWN_8E06 = 0x02080000,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
)
a730_raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00840004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00002400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00002400],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00000000],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000040],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00008000],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00008000],
[A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x20080000],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21fc7f00],
[A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00000000],
[A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
@@ -1044,22 +1044,22 @@ a740_magic_regs = dict(
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000000,
RB_UNKNOWN_8E06 = 0x02080000,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
)
a740_raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430800],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000400],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430800],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000],
[A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21585600],
[A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00008000],
[A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
@@ -1157,21 +1157,21 @@ add_gpus([
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000000,
RB_UNKNOWN_8E06 = 0x02080000,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00000000],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00040724],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430800],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000400],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430800],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000],
[A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x01585600],
[A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00008000],
[A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
@@ -1246,15 +1246,15 @@ add_gpus([
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00040004],
[A6XXRegs.REG_A6XX_TPL1_DBG_ECO_CNTL1, 0x00000700],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000400],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00430820],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000400],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00430820],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000080],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00000000],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000],
[A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x21585600],
[A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00008000],
[A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
@@ -1317,7 +1317,7 @@ add_gpus([
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x00000000,
RB_UNKNOWN_8E06 = 0x02080000,
RB_CCU_DBG_ECO_CNTL = 0x02080000,
),
raw_magic_regs = a740_raw_magic_regs,
))
@@ -1348,19 +1348,19 @@ add_gpus([
VPC_DBG_ECO_CNTL = 0x02000000,
UCHE_UNKNOWN_0E12 = 0x40000000,
RB_UNKNOWN_8E06 = 0x02082000,
RB_CCU_DBG_ECO_CNTL = 0x02082000,
),
raw_magic_regs = [
[A6XXRegs.REG_A6XX_UCHE_CACHE_WAYS, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E10, 0x00000000],
[A6XXRegs.REG_A7XX_UCHE_UNKNOWN_0E11, 0x00000080],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE08, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE09, 0x00431800],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE0A, 0x00800000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6C, 0x00000000],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_1, 0x00000000],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_2, 0x00431800],
[A6XXRegs.REG_A7XX_SP_CHICKEN_BITS_3, 0x00800000],
[A6XXRegs.REG_A7XX_SP_HLSQ_DBG_ECO_CNTL, 0x00000000],
[A6XXRegs.REG_A6XX_PC_DBG_ECO_CNTL, 0x00100000],
[A6XXRegs.REG_A7XX_PC_UNKNOWN_9E24, 0x01585600],
[A6XXRegs.REG_A7XX_VFD_UNKNOWN_A600, 0x00008000],
[A6XXRegs.REG_A7XX_VFD_DBG_ECO_CNTL, 0x00008000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE06, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6A, 0x00000000],
[A6XXRegs.REG_A7XX_SP_UNKNOWN_AE6B, 0x00000080],
@@ -1393,8 +1393,8 @@ add_gpus([
[0x930a, 0],
[0x960a, 1],
[A6XXRegs.REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL, 0],
[A6XXRegs.REG_A7XX_SP_PS_ALIASED_COMPONENTS, 0],
[A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_CNTL, 0],
[A6XXRegs.REG_A7XX_SP_PS_OUTPUT_CONST_MASK, 0],
],
))
src/freedreno/common/freedreno_stompable_regs.h
+14 -14
View File
@@ -37,13 +37,13 @@ fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
/* Faults in
* dEQP-VK.conditional_rendering.draw.condition_host_memory_expect_noop.draw
*/
case REG_A6XX_HLSQ_VS_CNTL ... REG_A6XX_HLSQ_GS_CNTL:
case REG_A6XX_HLSQ_FS_CNTL:
case REG_A6XX_SP_VS_CONST_CONFIG ... REG_A6XX_SP_GS_CONST_CONFIG:
case REG_A6XX_SP_PS_CONST_CONFIG:
/* Faults in
* dEQP-VK.memory_model.message_passing.ext.u32.coherent.atomic_atomic.atomicrmw.device.payload_local.image.guard_local.image.comp
* while there is even no fragment shaders.
*/
case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1:
case REG_A6XX_SP_PS_BASE ... REG_A6XX_SP_PS_BASE + 1:
return false;
/* Not used on A6XX but causes failures when set */
case REG_A6XX_TPL1_DBG_ECO_CNTL1:
@@ -54,24 +54,24 @@ fd_reg_stomp_allowed(chip CHIP, uint16_t reg)
case A7XX: {
switch (reg) {
case REG_A6XX_RB_DEPTH_PLANE_CNTL:
case REG_A7XX_HLSQ_VS_CNTL:
case REG_A7XX_HLSQ_HS_CNTL:
case REG_A7XX_HLSQ_DS_CNTL:
case REG_A7XX_HLSQ_GS_CNTL:
case REG_A7XX_HLSQ_FS_CNTL:
case REG_A6XX_SP_VS_OBJ_START ... REG_A6XX_SP_VS_OBJ_START + 1:
case REG_A6XX_SP_FS_OBJ_START ... REG_A6XX_SP_FS_OBJ_START + 1:
case REG_A7XX_SP_VS_CONST_CONFIG:
case REG_A7XX_SP_HS_CONST_CONFIG:
case REG_A7XX_SP_DS_CONST_CONFIG:
case REG_A7XX_SP_GS_CONST_CONFIG:
case REG_A7XX_SP_PS_CONST_CONFIG:
case REG_A6XX_SP_VS_BASE ... REG_A6XX_SP_VS_BASE + 1:
case REG_A6XX_SP_PS_BASE ... REG_A6XX_SP_PS_BASE + 1:
/* There is a guess that GPU may not be able to handle different values of
* certain debug register between BR/BV. This one causes GPU to hang.
*/
case REG_A7XX_SP_UNKNOWN_AE73:
case REG_A7XX_RB_UNKNOWN_8E79:
case REG_A7XX_SP_UNKNOWN_AE09:
case REG_A7XX_SP_CHICKEN_BITS_2:
case REG_A6XX_TPL1_DBG_ECO_CNTL:
return false;
case REG_A7XX_SP_GS_VGPR_CONFIG:
case REG_A7XX_SP_FS_VGPR_CONFIG:
case REG_A7XX_SP_CS_VGPR_CONFIG:
case REG_A7XX_SP_GS_VGS_CNTL:
case REG_A7XX_SP_PS_VGS_CNTL:
case REG_A7XX_SP_CS_VGS_CNTL:
return false;
}
break;
src/freedreno/computerator/a6xx.cc
+56 -56
View File
@@ -123,14 +123,14 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
const struct ir3_info *i = &v->info;
enum a6xx_threadsize thrsz = i->double_threadsize ? THREAD128 : THREAD64;
OUT_REG(ring, A6XX_SP_MODE_CONTROL(.constant_demotion_enable = true,
OUT_REG(ring, A6XX_SP_MODE_CNTL(.constant_demotion_enable = true,
.isammode = ISAMMODE_GL,
.shared_consts_enable = false));
OUT_PKT4(ring, REG_A6XX_SP_PERFCTR_ENABLE, 1);
OUT_RING(ring, A6XX_SP_PERFCTR_ENABLE_CS);
OUT_PKT4(ring, REG_A6XX_SP_PERFCTR_SHADER_MASK, 1);
OUT_RING(ring, A6XX_SP_PERFCTR_SHADER_MASK_CS);
OUT_PKT4(ring, REG_A6XX_SP_FLOAT_CNTL, 1);
OUT_PKT4(ring, REG_A6XX_SP_NC_MODE_CNTL_2, 1);
OUT_RING(ring, 0);
for (size_t i = 0; i < ARRAY_SIZE(a6xx_backend->info->a6xx.magic_raw); i++) {
@@ -142,7 +142,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
OUT_RING(ring, magic_reg.value);
}
OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP,
OUT_REG(ring, SP_UPDATE_CNTL(CHIP,
.vs_state = true,
.hs_state = true,
.ds_state = true,
@@ -153,7 +153,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
));
unsigned constlen = align(v->constlen, 4);
OUT_REG(ring, HLSQ_CS_CNTL(CHIP, .constlen = constlen, .enabled = true, ));
OUT_REG(ring, SP_CS_CONST_CONFIG(CHIP, .constlen = constlen, .enabled = true, ));
OUT_PKT4(ring, REG_A6XX_SP_CS_CONFIG, 2);
OUT_RING(ring, A6XX_SP_CS_CONFIG_ENABLED |
@@ -162,21 +162,21 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
A6XX_SP_CS_CONFIG_NSAMP(v->num_samp)); /* SP_VS_CONFIG */
OUT_RING(ring, v->instrlen); /* SP_VS_INSTRLEN */
OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG0, 1);
OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 1);
OUT_RING(ring,
A6XX_SP_CS_CTRL_REG0_THREADSIZE(thrsz) |
A6XX_SP_CS_CTRL_REG0_FULLREGFOOTPRINT(i->max_reg + 1) |
A6XX_SP_CS_CTRL_REG0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
COND(v->mergedregs, A6XX_SP_CS_CTRL_REG0_MERGEDREGS) |
COND(v->early_preamble, A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE) |
A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(ir3_shader_branchstack_hw(v)));
A6XX_SP_CS_CNTL_0_THREADSIZE(thrsz) |
A6XX_SP_CS_CNTL_0_FULLREGFOOTPRINT(i->max_reg + 1) |
A6XX_SP_CS_CNTL_0_HALFREGFOOTPRINT(i->max_half_reg + 1) |
COND(v->mergedregs, A6XX_SP_CS_CNTL_0_MERGEDREGS) |
COND(v->early_preamble, A6XX_SP_CS_CNTL_0_EARLYPREAMBLE) |
A6XX_SP_CS_CNTL_0_BRANCHSTACK(ir3_shader_branchstack_hw(v)));
if (CHIP == A7XX) {
OUT_REG(ring, HLSQ_FS_CNTL_0(CHIP, .threadsize = THREAD64));
OUT_REG(ring, SP_PS_WAVE_CNTL(CHIP, .threadsize = THREAD64));
OUT_REG(ring, HLSQ_CONTROL_2_REG(CHIP, .dword = 0xfcfcfcfc),
HLSQ_CONTROL_3_REG(CHIP, .dword = 0xfcfcfcfc),
HLSQ_CONTROL_4_REG(CHIP, .dword = 0xfcfcfcfc),
HLSQ_CONTROL_5_REG(CHIP, .dword = 0x0000fc00), );
OUT_REG(ring, SP_REG_PROG_ID_0(CHIP, .dword = 0xfcfcfcfc),
SP_REG_PROG_ID_1(CHIP, .dword = 0xfcfcfcfc),
SP_REG_PROG_ID_2(CHIP, .dword = 0xfcfcfcfc),
SP_REG_PROG_ID_3(CHIP, .dword = 0x0000fc00), );
}
uint32_t shared_size = MAX2(((int)v->shared_size - 1) / 1024, 1);
@@ -184,9 +184,9 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
v->constlen > 256 ? CONSTLEN_512 :
(v->constlen > 192 ? CONSTLEN_256 :
(v->constlen > 128 ? CONSTLEN_192 : CONSTLEN_128));
OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG1, 1);
OUT_RING(ring, A6XX_SP_CS_CTRL_REG1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_CTRL_REG1_CONSTANTRAMMODE(mode));
OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_1, 1);
OUT_RING(ring, A6XX_SP_CS_CNTL_1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_CNTL_1_CONSTANTRAMMODE(mode));
if (CHIP == A6XX && a6xx_backend->info->a6xx.has_lpac) {
OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CTRL_REG1, 1);
@@ -200,13 +200,13 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
work_group_id = ir3_find_sysval_regid(v, SYSTEM_VALUE_WORKGROUP_ID);
if (CHIP == A6XX) {
OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz));
OUT_PKT4(ring, REG_A6XX_SP_CS_CONST_CONFIG_0, 2);
OUT_RING(ring, A6XX_SP_CS_CONST_CONFIG_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_CONST_CONFIG_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_CONST_CONFIG_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_CONST_CONFIG_0_LOCALIDREGID(local_invocation_id));
OUT_RING(ring, A6XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_WGE_CNTL_THREADSIZE(thrsz));
} else {
unsigned tile_height = (local_size[1] % 8 == 0) ? 3
: (local_size[1] % 4 == 0) ? 5
@@ -214,7 +214,7 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
: 17;
OUT_REG(ring,
HLSQ_CS_CNTL_1(CHIP,
SP_CS_WGE_CNTL(CHIP,
.linearlocalidregid = regid(63, 0),
.threadsize = thrsz,
.workgrouprastorderzfirsten = true,
@@ -225,31 +225,31 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
}
if (CHIP == A7XX || a6xx_backend->info->a6xx.has_lpac) {
OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 1);
OUT_RING(ring, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
OUT_PKT4(ring, REG_A6XX_SP_CS_WIE_CNTL_0, 1);
OUT_RING(ring, A6XX_SP_CS_WIE_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_WIE_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_LOCALIDREGID(local_invocation_id));
if (CHIP == A7XX) {
/* TODO allow the shader to control the tiling */
OUT_REG(ring,
SP_CS_CNTL_1(A7XX, .linearlocalidregid = regid(63, 0),
SP_CS_WIE_CNTL_1(A7XX, .linearlocalidregid = regid(63, 0),
.threadsize = thrsz,
.workitemrastorder = WORKITEMRASTORDER_LINEAR));
} else {
OUT_REG(ring,
SP_CS_CNTL_1(CHIP, .linearlocalidregid = regid(63, 0),
SP_CS_WIE_CNTL_1(CHIP, .linearlocalidregid = regid(63, 0),
.threadsize = thrsz));
}
}
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_OBJ_START_LO/HI */
OUT_PKT4(ring, REG_A6XX_SP_CS_BASE, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0); /* SP_CS_BASE_LO/HI */
OUT_PKT4(ring, REG_A6XX_SP_CS_INSTRLEN, 1);
OUT_PKT4(ring, REG_A6XX_SP_CS_INSTR_SIZE, 1);
OUT_RING(ring, v->instrlen);
OUT_PKT4(ring, REG_A6XX_SP_CS_OBJ_START, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_BASE, 2);
OUT_RELOC(ring, v->bo, 0, 0, 0);
uint32_t shader_preload_size =
@@ -276,8 +276,8 @@ cs_program_emit(struct fd_ringbuffer *ring, struct kernel *kernel)
COND(v->pvtmem_per_wave,
A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT));
OUT_PKT4(ring, REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET, 1);
OUT_RING(ring, A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(per_sp_size));
OUT_PKT4(ring, REG_A6XX_SP_CS_PVT_MEM_STACK_OFFSET, 1);
OUT_RING(ring, A6XX_SP_CS_PVT_MEM_STACK_OFFSET_OFFSET(per_sp_size));
}
}
@@ -402,13 +402,13 @@ cs_ibo_emit(struct fd_ringbuffer *ring, struct fd_submit *submit,
OUT_RB(ring, state);
if (CHIP == A6XX) {
OUT_PKT4(ring, REG_A6XX_SP_CS_UAV, 2);
OUT_PKT4(ring, REG_A6XX_SP_CS_UAV_BASE, 2);
} else {
OUT_PKT4(ring, REG_A7XX_SP_CS_UAV, 2);
OUT_PKT4(ring, REG_A7XX_SP_CS_UAV_BASE, 2);
}
OUT_RB(ring, state);
OUT_PKT4(ring, REG_A6XX_SP_CS_UAV_COUNT, 1);
OUT_PKT4(ring, REG_A6XX_SP_CS_USIZE, 1);
OUT_RING(ring, kernel->num_bufs);
fd_ringbuffer_del(state);
@@ -501,34 +501,34 @@ a6xx_emit_grid(struct kernel *kernel, uint32_t grid[3],
work_dim++;
}
OUT_REG(ring, HLSQ_CS_NDRANGE_0(CHIP,
OUT_REG(ring, SP_CS_NDRANGE_0(CHIP,
.kerneldim = work_dim,
.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1,
));
if (CHIP == A7XX) {
OUT_REG(ring, A7XX_HLSQ_CS_LAST_LOCAL_SIZE(.localsizex = local_size[0] - 1,
OUT_REG(ring, A7XX_SP_CS_NDRANGE_7(.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1, ));
}
OUT_REG(ring, HLSQ_CS_NDRANGE_1(CHIP,
OUT_REG(ring, SP_CS_NDRANGE_1(CHIP,
.globalsize_x = local_size[0] * num_groups[0],
));
OUT_REG(ring, HLSQ_CS_NDRANGE_2(CHIP, 0));
OUT_REG(ring, HLSQ_CS_NDRANGE_3(CHIP,
OUT_REG(ring, SP_CS_NDRANGE_2(CHIP, 0));
OUT_REG(ring, SP_CS_NDRANGE_3(CHIP,
.globalsize_y = local_size[1] * num_groups[1],
));
OUT_REG(ring, HLSQ_CS_NDRANGE_4(CHIP, 0));
OUT_REG(ring, HLSQ_CS_NDRANGE_5(CHIP,
OUT_REG(ring, SP_CS_NDRANGE_4(CHIP, 0));
OUT_REG(ring, SP_CS_NDRANGE_5(CHIP,
.globalsize_z = local_size[2] * num_groups[2],
));
OUT_REG(ring, HLSQ_CS_NDRANGE_6(CHIP, 0));
OUT_REG(ring, SP_CS_NDRANGE_6(CHIP, 0));
OUT_REG(ring, HLSQ_CS_KERNEL_GROUP_X(CHIP, 1));
OUT_REG(ring, HLSQ_CS_KERNEL_GROUP_Y(CHIP, 1));
OUT_REG(ring, HLSQ_CS_KERNEL_GROUP_Z(CHIP, 1));
OUT_REG(ring, SP_CS_KERNEL_GROUP_X(CHIP, 1));
OUT_REG(ring, SP_CS_KERNEL_GROUP_Y(CHIP, 1));
OUT_REG(ring, SP_CS_KERNEL_GROUP_Z(CHIP, 1));
if (a6xx_backend->num_perfcntrs > 0) {
a6xx_backend->query_mem = fd_bo_new(
src/freedreno/decode/cffdec.c
+25 -25
View File
@@ -682,34 +682,34 @@ static struct {
REG(CP_SCRATCH[0x6].REG, reg_dump_scratch),
REG(CP_SCRATCH[0x7].REG, reg_dump_scratch),
REG64(SP_VS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_HS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_DS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_GS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_FS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_CS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_VS_BASE, reg_disasm_gpuaddr64),
REG64(SP_HS_BASE, reg_disasm_gpuaddr64),
REG64(SP_DS_BASE, reg_disasm_gpuaddr64),
REG64(SP_GS_BASE, reg_disasm_gpuaddr64),
REG64(SP_PS_BASE, reg_disasm_gpuaddr64),
REG64(SP_CS_BASE, reg_disasm_gpuaddr64),
REG64(SP_VS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_VS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_HS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_HS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_DS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_DS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_GS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_GS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_FS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_FS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_CS_TEX_CONST, reg_dump_gpuaddr64),
REG64(SP_CS_TEX_SAMP, reg_dump_gpuaddr64),
REG64(SP_VS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_VS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_HS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_HS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_DS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_DS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_GS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_GS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_PS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_PS_SAMPLER_BASE, reg_dump_gpuaddr64),
REG64(SP_CS_TEXMEMOBJ_BASE, reg_dump_gpuaddr64),
REG64(SP_CS_SAMPLER_BASE, reg_dump_gpuaddr64),
{NULL},
}, reg_a7xx[] = {
REG64(SP_VS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_HS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_DS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_GS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_FS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_CS_OBJ_START, reg_disasm_gpuaddr64),
REG64(SP_VS_BASE, reg_disasm_gpuaddr64),
REG64(SP_HS_BASE, reg_disasm_gpuaddr64),
REG64(SP_DS_BASE, reg_disasm_gpuaddr64),
REG64(SP_GS_BASE, reg_disasm_gpuaddr64),
REG64(SP_PS_BASE, reg_disasm_gpuaddr64),
REG64(SP_CS_BASE, reg_disasm_gpuaddr64),
{NULL},
}, *type0_reg;
@@ -1508,7 +1508,7 @@ dump_bindless_descriptors(bool is_compute, int level)
if (is_compute) {
sprintf(reg_name, "SP_CS_BINDLESS_BASE[%u].DESCRIPTOR", i);
} else {
sprintf(reg_name, "SP_BINDLESS_BASE[%u].DESCRIPTOR", i);
sprintf(reg_name, "SP_GFX_BINDLESS_BASE[%u].DESCRIPTOR", i);
}
const unsigned base_reg = regbase(reg_name);
if (!base_reg)
src/freedreno/decode/rddecompiler.c
+6 -6
View File
@@ -209,12 +209,12 @@ static struct {
uint32_t regbase;
uint32_t (*fxn)(const char *name, uint32_t regbase, uint32_t *dwords, int level);
} reg_a6xx[] = {
{REG_A6XX_SP_VS_OBJ_START, decompile_shader},
{REG_A6XX_SP_HS_OBJ_START, decompile_shader},
{REG_A6XX_SP_DS_OBJ_START, decompile_shader},
{REG_A6XX_SP_GS_OBJ_START, decompile_shader},
{REG_A6XX_SP_FS_OBJ_START, decompile_shader},
{REG_A6XX_SP_CS_OBJ_START, decompile_shader},
{REG_A6XX_SP_VS_BASE, decompile_shader},
{REG_A6XX_SP_HS_BASE, decompile_shader},
{REG_A6XX_SP_DS_BASE, decompile_shader},
{REG_A6XX_SP_GS_BASE, decompile_shader},
{REG_A6XX_SP_PS_BASE, decompile_shader},
{REG_A6XX_SP_CS_BASE, decompile_shader},
{0, NULL},
}, *type0_reg;
src/freedreno/decode/scripts/parse-submits.lua
+47 -47
View File
@@ -202,25 +202,25 @@ function CP_EVENT_WRITE(pkt, size)
local m = tostring(mode)
if m == "RM6_BIN_RENDER_START" then
-- either clear or restore:
if r.RB_BLIT_INFO.CLEAR_MASK == 0 then
restored[r.RB_BLIT_BASE_GMEM] = 1
if r.RB_RESOLVE_OPERATION.CLEAR_MASK == 0 then
restored[r.RB_RESOLVE_GMEM_BUFFER_BASE] = 1
else
cleared[r.RB_BLIT_BASE_GMEM] = 1
cleared[r.RB_RESOLVE_GMEM_BUFFER_BASE] = 1
end
-- push_mrt() because we could have GMEM
-- passes with only a clear and no draws:
local flag = 0
local sysmem = 0;
-- try to match up the GMEM addr with the MRT/DEPTH state,
-- to avoid relying on RB_BLIT_DST also getting written:
for n = 0,r.RB_FS_OUTPUT_CNTL1.MRT-1 do
if r.RB_MRT[n].BASE_GMEM == r.RB_BLIT_BASE_GMEM then
-- to avoid relying on RB_RESOLVE_SYSTEM_BUFFER_BASE also getting written:
for n = 0,r.RB_PS_MRT_CNTL.MRT-1 do
if r.RB_MRT[n].BASE_GMEM == r.RB_RESOLVE_GMEM_BUFFER_BASE then
sysmem = r.RB_MRT[n].BASE
flag = r.RB_MRT_FLAG_BUFFER[n].ADDR
flag = r.RB_COLOR_FLAG_BUFFER[n].ADDR
break
end
end
if sysmem == 0 and r.RB_BLIT_BASE_GMEM == r.RB_DEPTH_BUFFER_BASE_GMEM then
if sysmem == 0 and r.RB_RESOLVE_GMEM_BUFFER_BASE == r.RB_DEPTH_GMEM_BASE then
sysmem = r.RB_DEPTH_BUFFER_BASE
flag = r.RB_DEPTH_FLAG_BUFFER_BASE
@@ -228,24 +228,24 @@ function CP_EVENT_WRITE(pkt, size)
--NOTE this can get confused by previous blits:
--if sysmem == 0 then
-- -- fallback:
-- sysmem = r.RB_BLIT_DST
-- flag = r.RB_BLIT_FLAG_DST
-- sysmem = r.RB_RESOLVE_SYSTEM_BUFFER_BASE
-- flag = r.RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE
--end
if not r.RB_BLIT_DST_INFO.FLAGS then
if not r.RB_RESOLVE_SYSTEM_BUFFER_INFO.FLAGS then
flag = 0
end
-- TODO maybe just emit RB_BLIT_DST/HI for clears.. otherwise
-- TODO maybe just emit RB_RESOLVE_SYSTEM_BUFFER_BASE/HI for clears.. otherwise
-- we get confused by stale values in registers.. not sure
-- if this is a problem w/ blob
push_mrt(r.RB_BLIT_DST_INFO.COLOR_FORMAT,
r.RB_BLIT_SCISSOR_BR.X + 1,
r.RB_BLIT_SCISSOR_BR.Y + 1,
r.RB_BLIT_DST_INFO.SAMPLES,
push_mrt(r.RB_RESOLVE_SYSTEM_BUFFER_INFO.COLOR_FORMAT,
r.RB_RESOLVE_CNTL_2.X + 1,
r.RB_RESOLVE_CNTL_2.Y + 1,
r.RB_RESOLVE_SYSTEM_BUFFER_INFO.SAMPLES,
sysmem,
flag,
r.RB_BLIT_BASE_GMEM)
r.RB_RESOLVE_GMEM_BUFFER_BASE)
elseif m == "RM6_BIN_RESOLVE" then
resolved[r.RB_BLIT_BASE_GMEM] = 1
resolved[r.RB_RESOLVE_GMEM_BUFFER_BASE] = 1
else
printf("I am confused!!!\n")
end
@@ -263,7 +263,7 @@ function handle_blit()
-- blob sometimes uses CP_BLIT for resolves, so filter those out:
-- TODO it would be nice to not hard-code GMEM addr:
-- TODO I guess the src can be an offset from GMEM addr..
if r.SP_PS_2D_SRC == 0x100000 and not r.RB_2D_BLIT_CNTL.SOLID_COLOR then
if r.TPL1_A2D_SRC_TEXTURE_BASE == 0x100000 and not r.RB_A2D_BLT_CNTL.SOLID_COLOR then
resolved[0] = 1
return
end
@@ -275,23 +275,23 @@ function handle_blit()
-- This kinda assumes that we are doing full img blits, which is maybe
-- Not completely legit. We could perhaps instead just track pitch and
-- size/pitch?? Or maybe the size doesn't matter much
push_mrt(r.RB_2D_DST_INFO.COLOR_FORMAT,
r.GRAS_2D_DST_BR.X + 1,
r.GRAS_2D_DST_BR.Y + 1,
push_mrt(r.RB_A2D_DEST_BUFFER_INFO.COLOR_FORMAT,
r.GRAS_A2D_DEST_BR.X + 1,
r.GRAS_A2D_DEST_BR.Y + 1,
"MSAA_ONE",
r.RB_2D_DST,
r.RB_2D_DST_FLAGS,
r.RB_A2D_DEST_BUFFER_BASE,
r.RB_A2D_DEST_FLAG_BUFFER_BASE,
-1)
if r.RB_2D_BLIT_CNTL.SOLID_COLOR then
dbg("CLEAR=%x\n", r.RB_2D_DST)
cleared[r.RB_2D_DST] = 1
if r.RB_A2D_BLT_CNTL.SOLID_COLOR then
dbg("CLEAR=%x\n", r.RB_A2D_DEST_BUFFER_BASE)
cleared[r.RB_A2D_DEST_BUFFER_BASE] = 1
else
push_source(r.SP_2D_SRC_FORMAT.COLOR_FORMAT,
r.GRAS_2D_SRC_BR_X.X + 1,
r.GRAS_2D_SRC_BR_Y.Y + 1,
r.GRAS_A2D_SRC_XMAX.X + 1,
r.GRAS_A2D_SRC_YMAX.Y + 1,
"MSAA_ONE",
r.SP_PS_2D_SRC,
r.SP_PS_2D_SRC_FLAGS)
r.TPL1_A2D_SRC_TEXTURE_BASE,
r.TPL1_A2D_SRC_TEXTURE_FLAG_BASE)
end
blits = blits + 1
finish()
@@ -356,22 +356,22 @@ function draw(primtype, nindx)
drawmode = m
local render_components = {}
render_components[0] = r.RB_RENDER_COMPONENTS.RT0;
render_components[1] = r.RB_RENDER_COMPONENTS.RT1;
render_components[2] = r.RB_RENDER_COMPONENTS.RT2;
render_components[3] = r.RB_RENDER_COMPONENTS.RT3;
render_components[4] = r.RB_RENDER_COMPONENTS.RT4;
render_components[5] = r.RB_RENDER_COMPONENTS.RT5;
render_components[6] = r.RB_RENDER_COMPONENTS.RT6;
render_components[7] = r.RB_RENDER_COMPONENTS.RT7;
for n = 0,r.RB_FS_OUTPUT_CNTL1.MRT-1 do
render_components[0] = r.RB_PS_OUTPUT_MASK.RT0;
render_components[1] = r.RB_PS_OUTPUT_MASK.RT1;
render_components[2] = r.RB_PS_OUTPUT_MASK.RT2;
render_components[3] = r.RB_PS_OUTPUT_MASK.RT3;
render_components[4] = r.RB_PS_OUTPUT_MASK.RT4;
render_components[5] = r.RB_PS_OUTPUT_MASK.RT5;
render_components[6] = r.RB_PS_OUTPUT_MASK.RT6;
render_components[7] = r.RB_PS_OUTPUT_MASK.RT7;
for n = 0,r.RB_PS_MRT_CNTL.MRT-1 do
if render_components[n] ~= 0 then
push_mrt(r.RB_MRT[n].BUF_INFO.COLOR_FORMAT,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.X + 1,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_BLIT_GMEM_MSAA_CNTL.SAMPLES,
r.RB_RESOLVE_GMEM_BUFFER_INFO.SAMPLES,
r.RB_MRT[n].BASE,
r.RB_MRT_FLAG_BUFFER[n].ADDR,
r.RB_COLOR_FLAG_BUFFER[n].ADDR,
r.RB_MRT[n].BASE_GMEM)
end
end
@@ -382,10 +382,10 @@ function draw(primtype, nindx)
push_mrt(r.RB_DEPTH_BUFFER_INFO.DEPTH_FORMAT,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.X + 1,
r.GRAS_SC_SCREEN_SCISSOR[0].BR.Y + 1,
r.RB_BLIT_GMEM_MSAA_CNTL.SAMPLES,
r.RB_RESOLVE_GMEM_BUFFER_INFO.SAMPLES,
depthbase,
r.RB_DEPTH_FLAG_BUFFER_BASE,
r.RB_DEPTH_BUFFER_BASE_GMEM)
r.RB_DEPTH_GMEM_BASE)
end
if r.RB_DEPTH_CNTL.Z_WRITE_ENABLE then
@@ -397,11 +397,11 @@ function draw(primtype, nindx)
end
-- clearly 0 != false.. :-/
if r.RB_STENCILWRMASK.WRMASK ~= 0 then
if r.RB_STENCIL_WRITE_MASK.WRMASK ~= 0 then
stencilwrite = true
end
if r.RB_STENCIL_CONTROL.STENCIL_ENABLE then
if r.RB_STENCIL_CNTL.STENCIL_ENABLE then
stenciltest = true
end
@@ -410,7 +410,7 @@ function draw(primtype, nindx)
if m == "RM6_BIN_RENDER_START" then
binw = r.VSC_BIN_SIZE.WIDTH
binh = r.VSC_BIN_SIZE.HEIGHT
nbins = r.VSC_BIN_COUNT.NX * r.VSC_BIN_COUNT.NY
nbins = r.VSC_EXPANDED_BIN_CNTL.NX * r.VSC_EXPANDED_BIN_CNTL.NY
end
draws = draws + 1
src/freedreno/decode/scripts/sanity-a6xx.lua
+6 -6
View File
@@ -31,12 +31,12 @@ stages = {
-- maps shader stage to HLSQ_xS_CNTL register name:
cntl_regs = {
["SB6_VS_SHADER"] = "HLSQ_VS_CNTL",
["SB6_HS_SHADER"] = "HLSQ_HS_CNTL",
["SB6_DS_SHADER"] = "HLSQ_DS_CNTL",
["SB6_GS_SHADER"] = "HLSQ_GS_CNTL",
["SB6_FS_SHADER"] = "HLSQ_FS_CNTL",
["SB6_CS_SHADER"] = "HLSQ_CS_CNTL",
["SB6_VS_SHADER"] = "SP_VS_CONST_CONFIG",
["SB6_HS_SHADER"] = "SP_HS_CONST_CONFIG",
["SB6_DS_SHADER"] = "SP_DS_CONST_CONFIG",
["SB6_GS_SHADER"] = "SP_GS_CONST_CONFIG",
["SB6_FS_SHADER"] = "SP_PS_CONST_CONFIG",
["SB6_CS_SHADER"] = "SP_CS_CONST_CONFIG",
}
-- initialize constant updated ranges:
src/freedreno/decode/scripts/test.lua
+1 -1
View File
@@ -8,7 +8,7 @@ end
function draw(primtype, nindx)
io.write("DRAW: " .. primtype .. ", " .. nindx .. "\n")
-- io.write("GRAS_CL_VPORT_XOFFSET: " .. r.GRAS_CL_VPORT_XOFFSET .. "\n")
-- io.write("GRAS_CL_VIEWPORT[0].XOFFSET: " .. r.GRAS_CL_VIEWPORT[0].XOFFSET .. "\n")
io.write("RB_MRT[0].CONTROL.ROP_CODE: " .. r.RB_MRT[0].CONTROL.ROP_CODE .. "\n")
io.write("SP_VS_OUT[0].A_COMPMASK: " .. r.SP_VS_OUT[0].A_COMPMASK .. "\n")
--io.write("RB_DEPTH_CONTROL.Z_TEST_ENABLE: " .. tostring(r.RB_DEPTH_CONTROL.Z_TEST_ENABLE) .. "\n")
src/freedreno/decode/scripts/tex3d-layout.lua
+5 -5
View File
@@ -41,16 +41,16 @@ function draw(primtype, nindx)
-- Just in case, filter out anything that isn't starting
-- at 0,0
if r.GRAS_2D_DST_TL.X ~= 0 or r.GRAS_2D_DST_TL.Y ~= 0 then
if r.GRAS_A2D_DEST_TL.X ~= 0 or r.GRAS_A2D_DEST_TL.Y ~= 0 then
return
end
local blit = {}
blit.width = r.GRAS_2D_DST_BR.X + 1
blit.height = r.GRAS_2D_DST_BR.Y + 1
blit.pitch = r.RB_2D_DST_SIZE.PITCH
blit.addr = r.RB_2D_DST_LO | (r.RB_2D_DST_HI << 32)
blit.width = r.GRAS_A2D_DEST_BR.X + 1
blit.height = r.GRAS_A2D_DEST_BR.Y + 1
blit.pitch = r.RB_A2D_DEST_BUFFER_BASE_SIZE.PITCH
blit.addr = r.RB_A2D_DEST_BUFFER_BASE_LO | (r.RB_A2D_DEST_BUFFER_BASE_HI << 32)
blit.base = bos.base(blit.addr)
blit.endaddr = 0 -- filled in later
--printf("Found blit: 0x%x (0x%x)\n", blit.addr, blit.base)
src/freedreno/decode/scripts/texturator-to-unit-test.lua
+9 -9
View File
@@ -61,24 +61,24 @@ function draw(primtype, nindx)
if primtype == "BLIT_OP_SCALE" then
-- Just in case, filter out anything that isn't starting
-- at 0,0
if r.GRAS_2D_DST_TL.X ~= 0 or r.GRAS_2D_DST_TL.Y ~= 0 then
if r.GRAS_A2D_DEST_TL.X ~= 0 or r.GRAS_A2D_DEST_TL.Y ~= 0 then
return
end
blit.width = r.GRAS_2D_DST_BR.X + 1
blit.height = r.GRAS_2D_DST_BR.Y + 1
blit.pitch = r.RB_2D_DST_PITCH
blit.addr = r.RB_2D_DST
blit.ubwc_addr = r.RB_2D_DST_FLAGS
blit.ubwc_pitch = r.RB_2D_DST_FLAGS_PITCH
blit.width = r.GRAS_A2D_DEST_BR.X + 1
blit.height = r.GRAS_A2D_DEST_BR.Y + 1
blit.pitch = r.RB_A2D_DEST_BUFFER_PITCH
blit.addr = r.RB_A2D_DEST_BUFFER_BASE
blit.ubwc_addr = r.RB_A2D_DEST_FLAG_BUFFER_BASE
blit.ubwc_pitch = r.RB_A2D_DEST_FLAG_BUFFER_PITCH
type="blit";
else
blit.width = r.GRAS_SC_WINDOW_SCISSOR_BR.X + 1
blit.height = r.GRAS_SC_WINDOW_SCISSOR_BR.Y + 1
blit.pitch = r.RB_MRT[0].PITCH
blit.addr = r.RB_MRT[0].BASE
blit.ubwc_addr = r.RB_MRT_FLAG_BUFFER[0].ADDR
blit.ubwc_pitch = r.RB_MRT_FLAG_BUFFER[0].PITCH.PITCH
blit.ubwc_addr = r.RB_COLOR_FLAG_BUFFER[0].ADDR
blit.ubwc_pitch = r.RB_COLOR_FLAG_BUFFER[0].PITCH.PITCH
type="draw"
end
blit.base = bos.base(blit.addr)
src/freedreno/fdl/fd6_view.c
+36 -36
View File
@@ -317,21 +317,21 @@ fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
view->pitch = pitch;
view->SP_PS_2D_SRC_INFO =
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(storage_format) |
A6XX_SP_PS_2D_SRC_INFO_TILE_MODE(tile_mode) |
A6XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(swap) |
COND(ubwc_enabled, A6XX_SP_PS_2D_SRC_INFO_FLAGS) |
COND(util_format_is_srgb(args->format), A6XX_SP_PS_2D_SRC_INFO_SRGB) |
A6XX_SP_PS_2D_SRC_INFO_SAMPLES(util_logbase2(layout->nr_samples)) |
COND(samples_average, A6XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE) |
A6XX_SP_PS_2D_SRC_INFO_UNK20 |
A6XX_SP_PS_2D_SRC_INFO_UNK22 |
COND(is_mutable, A6XX_SP_PS_2D_SRC_INFO_MUTABLEEN);
view->TPL1_A2D_SRC_TEXTURE_INFO =
A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_FORMAT(storage_format) |
A6XX_TPL1_A2D_SRC_TEXTURE_INFO_TILE_MODE(tile_mode) |
A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_SWAP(swap) |
COND(ubwc_enabled, A6XX_TPL1_A2D_SRC_TEXTURE_INFO_FLAGS) |
COND(util_format_is_srgb(args->format), A6XX_TPL1_A2D_SRC_TEXTURE_INFO_SRGB) |
A6XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES(util_logbase2(layout->nr_samples)) |
COND(samples_average, A6XX_TPL1_A2D_SRC_TEXTURE_INFO_SAMPLES_AVERAGE) |
A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK20 |
A6XX_TPL1_A2D_SRC_TEXTURE_INFO_UNK22 |
COND(is_mutable, A6XX_TPL1_A2D_SRC_TEXTURE_INFO_MUTABLEEN);
view->SP_PS_2D_SRC_SIZE =
A6XX_SP_PS_2D_SRC_SIZE_WIDTH(width) |
A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(height);
view->TPL1_A2D_SRC_TEXTURE_SIZE =
A6XX_TPL1_A2D_SRC_TEXTURE_SIZE_WIDTH(width) |
A6XX_TPL1_A2D_SRC_TEXTURE_SIZE_HEIGHT(height);
/* note: these have same encoding for MRT and 2D (except 2D PITCH src) */
view->FLAG_BUFFER_PITCH =
@@ -341,10 +341,10 @@ fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
const struct util_format_description *format_desc =
util_format_description(args->format);
if (util_format_has_depth(format_desc)) {
view->GRAS_LRZ_DEPTH_VIEW =
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_LAYER(args->base_array_layer) |
A6XX_GRAS_LRZ_DEPTH_VIEW_LAYER_COUNT(args->layer_count) |
A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(args->base_miplevel);
view->GRAS_LRZ_VIEW_INFO =
A6XX_GRAS_LRZ_VIEW_INFO_BASE_LAYER(args->base_array_layer) |
A6XX_GRAS_LRZ_VIEW_INFO_LAYER_COUNT(args->layer_count) |
A6XX_GRAS_LRZ_VIEW_INFO_BASE_MIP_LEVEL(args->base_miplevel);
}
view->base_addr = base_addr;
@@ -412,26 +412,26 @@ fdl6_view_init(struct fdl6_view *view, const struct fdl_layout **layouts,
A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(color_swap) |
COND(is_mutable, A7XX_RB_MRT_BUF_INFO_MUTABLEEN);
view->SP_FS_MRT_REG =
A6XX_SP_FS_MRT_REG_COLOR_FORMAT(color_format) |
COND(util_format_is_pure_sint(args->format), A6XX_SP_FS_MRT_REG_COLOR_SINT) |
COND(util_format_is_pure_uint(args->format), A6XX_SP_FS_MRT_REG_COLOR_UINT);
view->SP_PS_MRT_REG =
A6XX_SP_PS_MRT_REG_COLOR_FORMAT(color_format) |
COND(util_format_is_pure_sint(args->format), A6XX_SP_PS_MRT_REG_COLOR_SINT) |
COND(util_format_is_pure_uint(args->format), A6XX_SP_PS_MRT_REG_COLOR_UINT);
view->RB_2D_DST_INFO =
A6XX_RB_2D_DST_INFO_COLOR_FORMAT(color_format) |
A6XX_RB_2D_DST_INFO_TILE_MODE(tile_mode) |
A6XX_RB_2D_DST_INFO_COLOR_SWAP(color_swap) |
COND(ubwc_enabled, A6XX_RB_2D_DST_INFO_FLAGS) |
COND(util_format_is_srgb(args->format), A6XX_RB_2D_DST_INFO_SRGB) |
COND(is_mutable, A6XX_RB_2D_DST_INFO_MUTABLEEN);;
view->RB_A2D_DEST_BUFFER_INFO =
A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_FORMAT(color_format) |
A6XX_RB_A2D_DEST_BUFFER_INFO_TILE_MODE(tile_mode) |
A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_SWAP(color_swap) |
COND(ubwc_enabled, A6XX_RB_A2D_DEST_BUFFER_INFO_FLAGS) |
COND(util_format_is_srgb(args->format), A6XX_RB_A2D_DEST_BUFFER_INFO_SRGB) |
COND(is_mutable, A6XX_RB_A2D_DEST_BUFFER_INFO_MUTABLEEN);;
view->RB_BLIT_DST_INFO =
A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode) |
A6XX_RB_BLIT_DST_INFO_SAMPLES(util_logbase2(layout->nr_samples)) |
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(blit_format) |
A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(color_swap) |
COND(ubwc_enabled, A6XX_RB_BLIT_DST_INFO_FLAGS) |
COND(is_mutable, A6XX_RB_BLIT_DST_INFO_MUTABLEEN);
view->RB_RESOLVE_SYSTEM_BUFFER_INFO =
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_TILE_MODE(tile_mode) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_SAMPLES(util_logbase2(layout->nr_samples)) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_FORMAT(blit_format) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_SWAP(color_swap) |
COND(ubwc_enabled, A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_FLAGS) |
COND(is_mutable, A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_MUTABLEEN);
}
void
src/freedreno/fdl/freedreno_layout.h
+6 -6
View File
@@ -316,16 +316,16 @@ struct fdl6_view {
uint32_t FLAG_BUFFER_PITCH;
uint32_t RB_MRT_BUF_INFO;
uint32_t SP_FS_MRT_REG;
uint32_t SP_PS_MRT_REG;
uint32_t SP_PS_2D_SRC_INFO;
uint32_t SP_PS_2D_SRC_SIZE;
uint32_t TPL1_A2D_SRC_TEXTURE_INFO;
uint32_t TPL1_A2D_SRC_TEXTURE_SIZE;
uint32_t RB_2D_DST_INFO;
uint32_t RB_A2D_DEST_BUFFER_INFO;
uint32_t RB_BLIT_DST_INFO;
uint32_t RB_RESOLVE_SYSTEM_BUFFER_INFO;
uint32_t GRAS_LRZ_DEPTH_VIEW;
uint32_t GRAS_LRZ_VIEW_INFO;
};
void
src/freedreno/registers/adreno/a6xx.xml
+474 -476
View File
File diff suppressed because it is too large Load Diff
src/freedreno/registers/adreno/adreno_pm4.xml
+8 -8
View File
@@ -31,8 +31,8 @@ xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
<value name="STAT_EVENT" value="16" variants="A2XX-A4XX"/>
<value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX-A4XX"/>
<doc>
If A6XX_RB_SAMPLE_COUNT_CONTROL.copy is true, writes OQ Z passed
sample counts to RB_SAMPLE_COUNT_ADDR. This writes to main
If A6XX_RB_SAMPLE_COUNTER_CNTL.copy is true, writes OQ Z passed
sample counts to RB_SAMPLE_COUNTER_BASE. This writes to main
memory, skipping UCHE.
</doc>
<value name="ZPASS_DONE" value="21"/>
@@ -1946,9 +1946,9 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
If concurrent binning is disabled then BR also does binning so it will also
write the "real" registers in BR.
-->
<value value="8" name="DRAW_STRM_ADDRESS"/>
<value value="9" name="DRAW_STRM_SIZE_ADDRESS"/>
<value value="10" name="PRIM_STRM_ADDRESS"/>
<value value="8" name="VSC_PIPE_DATA_DRAW_BASE"/>
<value value="9" name="VSC_SIZE_BASE"/>
<value value="10" name="VSC_PIPE_DATA_PRIM_BASE"/>
<value value="11" name="UNK_STRM_ADDRESS"/>
<value value="12" name="UNK_STRM_SIZE_ADDRESS"/>
@@ -2201,12 +2201,12 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<value name="UNK_EVENT_WRITE" value="0x4"/>
<doc>
Tracks GRAS_LRZ_CNTL::GREATER, GRAS_LRZ_CNTL::DIR, and
GRAS_LRZ_DEPTH_VIEW with previous values, and if one of
GRAS_LRZ_VIEW_INFO with previous values, and if one of
the following is true:
- GRAS_LRZ_CNTL::GREATER has changed
- GRAS_LRZ_CNTL::DIR has changed, the old value is not
CUR_DIR_GE, and the new value is not CUR_DIR_DISABLED
- GRAS_LRZ_DEPTH_VIEW has changed
- GRAS_LRZ_VIEW_INFO has changed
then it does a LRZ_FLUSH with GRAS_LRZ_CNTL::ENABLE
forced to 1.
Only exists in a650_sqe.fw.
@@ -2321,7 +2321,7 @@ opcode: CP_LOAD_STATE4 (30) (4 dwords)
<domain name="CP_MEM_TO_SCRATCH_MEM" width="32">
<doc>
Best guess is that it is a faster way to fetch all the VSC_STATE registers
Best guess is that it is a faster way to fetch all the VSC_CHANNEL_VISIBILITY registers
and keep them in a local scratch memory instead of fetching every time
when skipping IBs.
</doc>
src/freedreno/registers/gen_header.py
+1 -1
View File
@@ -123,7 +123,7 @@ def field_name(reg, f):
name = f.name.lower()
else:
# We hit this path when a reg is defined with no bitset fields, ie.
# <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
# <reg32 offset="0x88db" name="RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
name = reg.name.lower()
if (name in [ "double", "float", "int" ]) or not (name[0].isalpha()):
src/freedreno/vulkan/tu_autotune.cc
+4 -4
View File
@@ -669,7 +669,7 @@ tu_autotune_begin_renderpass(struct tu_cmd_buffer *cmd,
(struct tu_renderpass_samples *) tu_suballoc_bo_map(
&autotune_result->bo);
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.copy = true));
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (cmd->device->physical_device->info->a7xx.has_event_write_sample_count) {
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE7, 3);
tu_cs_emit(cs, CP_EVENT_WRITE7_0(.event = ZPASS_DONE,
@@ -692,7 +692,7 @@ tu_autotune_begin_renderpass(struct tu_cmd_buffer *cmd,
}
} else {
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNT_ADDR(.qword = result_iova));
A6XX_RB_SAMPLE_COUNTER_BASE(.qword = result_iova));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, ZPASS_DONE);
}
@@ -712,7 +712,7 @@ void tu_autotune_end_renderpass(struct tu_cmd_buffer *cmd,
uint64_t result_iova = autotune_result->bo.iova;
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.copy = true));
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (cmd->device->physical_device->info->a7xx.has_event_write_sample_count) {
/* If the renderpass contains ZPASS_DONE events we emit a fake ZPASS_DONE
@@ -738,7 +738,7 @@ void tu_autotune_end_renderpass(struct tu_cmd_buffer *cmd,
result_iova += offsetof(struct tu_renderpass_samples, samples_end);
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNT_ADDR(.qword = result_iova));
A6XX_RB_SAMPLE_COUNTER_BASE(.qword = result_iova));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, ZPASS_DONE);
}
src/freedreno/vulkan/tu_clear_blit.cc
+163 -163
View File
@@ -150,17 +150,17 @@ r2d_coords(struct tu_cmd_buffer *cmd,
const VkExtent2D extent)
{
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_DST_TL(.x = dst.x, .y = dst.y),
A6XX_GRAS_2D_DST_BR(.x = dst.x + extent.width - 1, .y = dst.y + extent.height - 1));
A6XX_GRAS_A2D_DEST_TL(.x = dst.x, .y = dst.y),
A6XX_GRAS_A2D_DEST_BR(.x = dst.x + extent.width - 1, .y = dst.y + extent.height - 1));
if (src.x == blt_no_coord.x)
return;
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_SRC_TL_X(src.x),
A6XX_GRAS_2D_SRC_BR_X(src.x + extent.width - 1),
A6XX_GRAS_2D_SRC_TL_Y(src.y),
A6XX_GRAS_2D_SRC_BR_Y(src.y + extent.height - 1));
A6XX_GRAS_A2D_SRC_XMIN(src.x),
A6XX_GRAS_A2D_SRC_XMAX(src.x + extent.width - 1),
A6XX_GRAS_A2D_SRC_YMIN(src.y),
A6XX_GRAS_A2D_SRC_YMAX(src.y + extent.height - 1));
}
static void
@@ -226,7 +226,7 @@ r2d_clear_value(struct tu_cmd_buffer *cmd,
break;
}
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_CLEAR_COLOR_DW0, 4);
tu_cs_emit_array(cs, clear_value, 4);
}
@@ -272,24 +272,24 @@ r2d_src(struct tu_cmd_buffer *cmd,
VkFilter filter,
enum pipe_format dst_format)
{
uint32_t src_info = iview->SP_PS_2D_SRC_INFO;
uint32_t src_info = iview->TPL1_A2D_SRC_TEXTURE_INFO;
if (filter != VK_FILTER_NEAREST)
src_info |= A6XX_SP_PS_2D_SRC_INFO_FILTER;
src_info |= A6XX_TPL1_A2D_SRC_TEXTURE_INFO_FILTER;
enum a6xx_format fmt = (enum a6xx_format) pkt_field_get(
A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT, src_info);
A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_FORMAT, src_info);
enum pipe_format src_format = iview->format;
fixup_src_format(&src_format, dst_format, &fmt);
src_info =
pkt_field_set(A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT, src_info, fmt);
pkt_field_set(A6XX_TPL1_A2D_SRC_TEXTURE_INFO_COLOR_FORMAT, src_info, fmt);
tu_cs_emit_pkt4(cs, SP_PS_2D_SRC_INFO(CHIP,).reg, 5);
tu_cs_emit_pkt4(cs, TPL1_A2D_SRC_TEXTURE_INFO(CHIP,).reg, 5);
tu_cs_emit(cs, src_info);
tu_cs_emit(cs, iview->SP_PS_2D_SRC_SIZE);
tu_cs_emit(cs, iview->TPL1_A2D_SRC_TEXTURE_SIZE);
tu_cs_image_ref_2d<CHIP>(cs, iview, layer, true);
tu_cs_emit_pkt4(cs, __SP_PS_2D_SRC_FLAGS<CHIP>({}).reg, 3);
tu_cs_emit_pkt4(cs, __TPL1_A2D_SRC_TEXTURE_FLAG_BASE<CHIP>({}).reg, 3);
tu_cs_image_flag_ref(cs, iview, layer);
}
@@ -301,14 +301,14 @@ r2d_src_depth(struct tu_cmd_buffer *cmd,
uint32_t layer,
VkFilter filter)
{
tu_cs_emit_pkt4(cs, SP_PS_2D_SRC_INFO(CHIP).reg, 5);
tu_cs_emit(cs, tu_image_view_depth(iview, SP_PS_2D_SRC_INFO));
tu_cs_emit(cs, iview->view.SP_PS_2D_SRC_SIZE);
tu_cs_emit_pkt4(cs, TPL1_A2D_SRC_TEXTURE_INFO(CHIP).reg, 5);
tu_cs_emit(cs, tu_image_view_depth(iview, TPL1_A2D_SRC_TEXTURE_INFO));
tu_cs_emit(cs, iview->view.TPL1_A2D_SRC_TEXTURE_SIZE);
tu_cs_emit_qw(cs, iview->depth_base_addr + iview->depth_layer_size * layer);
/* SP_PS_2D_SRC_PITCH has shifted pitch field */
tu_cs_emit(cs, SP_PS_2D_SRC_PITCH(CHIP, .pitch = iview->depth_pitch).value);
/* TPL1_A2D_SRC_TEXTURE_PITCH has shifted pitch field */
tu_cs_emit(cs, TPL1_A2D_SRC_TEXTURE_PITCH(CHIP, .pitch = iview->depth_pitch).value);
tu_cs_emit_pkt4(cs, __SP_PS_2D_SRC_FLAGS<CHIP>({}).reg, 3);
tu_cs_emit_pkt4(cs, __TPL1_A2D_SRC_TEXTURE_FLAG_BASE<CHIP>({}).reg, 3);
tu_cs_image_flag_ref(cs, &iview->view, layer);
}
@@ -320,11 +320,11 @@ r2d_src_stencil(struct tu_cmd_buffer *cmd,
uint32_t layer,
VkFilter filter)
{
tu_cs_emit_pkt4(cs, SP_PS_2D_SRC_INFO(CHIP,).reg, 5);
tu_cs_emit(cs, tu_image_view_stencil(iview, SP_PS_2D_SRC_INFO) & ~A6XX_SP_PS_2D_SRC_INFO_FLAGS);
tu_cs_emit(cs, iview->view.SP_PS_2D_SRC_SIZE);
tu_cs_emit_pkt4(cs, TPL1_A2D_SRC_TEXTURE_INFO(CHIP,).reg, 5);
tu_cs_emit(cs, tu_image_view_stencil(iview, TPL1_A2D_SRC_TEXTURE_INFO) & ~A6XX_TPL1_A2D_SRC_TEXTURE_INFO_FLAGS);
tu_cs_emit(cs, iview->view.TPL1_A2D_SRC_TEXTURE_SIZE);
tu_cs_emit_qw(cs, iview->stencil_base_addr + iview->stencil_layer_size * layer);
tu_cs_emit(cs, SP_PS_2D_SRC_PITCH(CHIP, .pitch = iview->stencil_pitch).value);
tu_cs_emit(cs, TPL1_A2D_SRC_TEXTURE_PITCH(CHIP, .pitch = iview->stencil_pitch).value);
}
template <chip CHIP>
@@ -341,15 +341,15 @@ r2d_src_buffer(struct tu_cmd_buffer *cmd,
fixup_src_format(&format, dst_format, &color_format);
tu_cs_emit_regs(cs,
SP_PS_2D_SRC_INFO(CHIP,
TPL1_A2D_SRC_TEXTURE_INFO(CHIP,
.color_format = color_format,
.color_swap = fmt.swap,
.srgb = util_format_is_srgb(format),
.unk20 = 1,
.unk22 = 1),
SP_PS_2D_SRC_SIZE(CHIP, .width = width, .height = height),
SP_PS_2D_SRC(CHIP, .qword = va),
SP_PS_2D_SRC_PITCH(CHIP, .pitch = pitch));
TPL1_A2D_SRC_TEXTURE_SIZE(CHIP, .width = width, .height = height),
TPL1_A2D_SRC_TEXTURE_BASE(CHIP, .qword = va),
TPL1_A2D_SRC_TEXTURE_PITCH(CHIP, .pitch = pitch));
}
template <chip CHIP>
@@ -376,18 +376,18 @@ r2d_src_buffer_unaligned(struct tu_cmd_buffer *cmd,
uint32_t offset_texels = ((va & 0x3f) / util_format_get_blocksize(format));
va &= ~0x3f;
tu_cs_emit_regs(cs,
A7XX_TPL1_2D_SRC_CNTL(.raw_copy = false,
A7XX_TPL1_A2D_BLT_CNTL(.raw_copy = false,
.start_offset_texels = offset_texels,
.type = A6XX_TEX_IMG_BUFFER));
tu_cs_emit_regs(cs,
SP_PS_2D_SRC_INFO(CHIP, .color_format = color_format,
TPL1_A2D_SRC_TEXTURE_INFO(CHIP, .color_format = color_format,
.color_swap = fmt.swap,
.srgb = util_format_is_srgb(format),
.unk20 = 1, .unk22 = 1),
SP_PS_2D_SRC_SIZE(CHIP, .width = width, .height = height),
SP_PS_2D_SRC(CHIP, .qword = va),
SP_PS_2D_SRC_PITCH(CHIP, .pitch = pitch));
TPL1_A2D_SRC_TEXTURE_SIZE(CHIP, .width = width, .height = height),
TPL1_A2D_SRC_TEXTURE_BASE(CHIP, .qword = va),
TPL1_A2D_SRC_TEXTURE_PITCH(CHIP, .pitch = pitch));
}
template <chip CHIP>
@@ -395,40 +395,40 @@ static void
r2d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer,
enum pipe_format src_format)
{
uint32_t dst_info = iview->RB_2D_DST_INFO;
uint32_t dst_info = iview->RB_A2D_DEST_BUFFER_INFO;
enum a6xx_format fmt = (enum a6xx_format) pkt_field_get(
A6XX_RB_2D_DST_INFO_COLOR_FORMAT, dst_info);
A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_FORMAT, dst_info);
enum pipe_format dst_format = iview->format;
fixup_dst_format(src_format, &dst_format, &fmt);
dst_info = pkt_field_set(A6XX_RB_2D_DST_INFO_COLOR_FORMAT, dst_info, fmt);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_INFO, 4);
dst_info = pkt_field_set(A6XX_RB_A2D_DEST_BUFFER_INFO_COLOR_FORMAT, dst_info, fmt);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_DEST_BUFFER_INFO, 4);
tu_cs_emit(cs, dst_info);
tu_cs_image_ref_2d<CHIP>(cs, iview, layer, false);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_DEST_FLAG_BUFFER_BASE, 3);
tu_cs_image_flag_ref(cs, iview, layer);
}
static void
r2d_dst_depth(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_INFO, 4);
tu_cs_emit(cs, tu_image_view_depth(iview, RB_2D_DST_INFO));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_DEST_BUFFER_INFO, 4);
tu_cs_emit(cs, tu_image_view_depth(iview, RB_A2D_DEST_BUFFER_INFO));
tu_cs_emit_qw(cs, iview->depth_base_addr + iview->depth_layer_size * layer);
tu_cs_emit(cs, A6XX_RB_2D_DST_PITCH(iview->depth_pitch).value);
tu_cs_emit(cs, A6XX_RB_A2D_DEST_BUFFER_PITCH(iview->depth_pitch).value);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_FLAGS, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_DEST_FLAG_BUFFER_BASE, 3);
tu_cs_image_flag_ref(cs, &iview->view, layer);
}
static void
r2d_dst_stencil(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t layer)
{
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_DST_INFO, 4);
tu_cs_emit(cs, tu_image_view_stencil(iview, RB_2D_DST_INFO) & ~A6XX_RB_2D_DST_INFO_FLAGS);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_DEST_BUFFER_INFO, 4);
tu_cs_emit(cs, tu_image_view_stencil(iview, RB_A2D_DEST_BUFFER_INFO) & ~A6XX_RB_A2D_DEST_BUFFER_INFO_FLAGS);
tu_cs_emit_qw(cs, iview->stencil_base_addr + iview->stencil_layer_size * layer);
tu_cs_emit(cs, A6XX_RB_2D_DST_PITCH(iview->stencil_pitch).value);
tu_cs_emit(cs, A6XX_RB_A2D_DEST_BUFFER_PITCH(iview->stencil_pitch).value);
}
static void
@@ -441,12 +441,12 @@ r2d_dst_buffer(struct tu_cs *cs, enum pipe_format format, uint64_t va, uint32_t
fmt.fmt = color_fmt;
tu_cs_emit_regs(cs,
A6XX_RB_2D_DST_INFO(
A6XX_RB_A2D_DEST_BUFFER_INFO(
.color_format = fmt.fmt,
.color_swap = fmt.swap,
.srgb = util_format_is_srgb(format)),
A6XX_RB_2D_DST(.qword = va),
A6XX_RB_2D_DST_PITCH(pitch));
A6XX_RB_A2D_DEST_BUFFER_BASE(.qword = va),
A6XX_RB_A2D_DEST_BUFFER_PITCH(pitch));
}
template <chip CHIP>
@@ -481,10 +481,10 @@ r2d_setup_common(struct tu_cmd_buffer *cmd,
unknown_8c01 = 0x00084001;
}
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_UNKNOWN_8C01, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_PIXEL_CNTL, 1);
tu_cs_emit(cs, unknown_8c01); // TODO: seem to be always 0 on A7XX
uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL(
uint32_t blit_cntl = A6XX_RB_A2D_BLT_CNTL(
.rotate = (enum a6xx_rotation) blit_param,
.solid_color = clear,
.color_format = fmt,
@@ -494,14 +494,14 @@ r2d_setup_common(struct tu_cmd_buffer *cmd,
.ifmt = util_format_is_srgb(dst_format) ? R2D_UNORM8_SRGB : ifmt,
).value;
tu_cs_emit_pkt4(cs, REG_A6XX_RB_2D_BLIT_CNTL, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_A2D_BLT_CNTL, 1);
tu_cs_emit(cs, blit_cntl);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_A2D_BLT_CNTL, 1);
tu_cs_emit(cs, blit_cntl);
if (CHIP > A6XX) {
tu_cs_emit_regs(cs, A7XX_TPL1_2D_SRC_CNTL(.raw_copy = false,
tu_cs_emit_regs(cs, A7XX_TPL1_A2D_BLT_CNTL(.raw_copy = false,
.start_offset_texels = 0,
.type = A6XX_TEX_2D));
}
@@ -509,7 +509,7 @@ r2d_setup_common(struct tu_cmd_buffer *cmd,
if (fmt == FMT6_10_10_10_2_UNORM_DEST)
fmt = FMT6_16_16_16_16_FLOAT;
tu_cs_emit_regs(cs, SP_2D_DST_FORMAT(CHIP,
tu_cs_emit_regs(cs, SP_A2D_OUTPUT_INFO(CHIP,
.sint = util_format_is_pure_sint(dst_format),
.uint = util_format_is_pure_uint(dst_format),
.color_format = fmt,
@@ -896,7 +896,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
struct ir3_shader_variant *fs = cmd->device->global_shader_variants[fs_id];
uint64_t fs_iova = cmd->device->global_shader_va[fs_id];
tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
tu_cs_emit_regs(cs, SP_UPDATE_CNTL(CHIP,
.vs_state = true,
.hs_state = true,
.ds_state = true,
@@ -917,9 +917,9 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
tu6_emit_xs(cs, MESA_SHADER_VERTEX, vs, &pvtmem, vs_iova);
tu6_emit_xs(cs, MESA_SHADER_FRAGMENT, fs, &pvtmem, fs_iova);
tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0());
tu_cs_emit_regs(cs, A6XX_PC_CNTL());
if (CHIP == A7XX) {
tu_cs_emit_regs(cs, A7XX_VPC_PRIMITIVE_CNTL_0());
tu_cs_emit_regs(cs, A7XX_VPC_PC_CNTL());
}
tu6_emit_vpc<CHIP>(cs, vs, NULL, NULL, NULL, fs);
@@ -927,12 +927,12 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false));
tu_cs_emit_regs(cs, A7XX_SP_RENDER_CNTL(.fs_disable = false));
}
/* REPL_MODE for varying with RECTLIST (2 vertices only) */
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_INTERP_MODE(0, 0));
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_PS_REPL_MODE(0, 2 << 2 | 1 << 0));
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_INTERP_MODE_MODE(0, 0));
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_REPLACE_MODE_0_MODE(0, 2 << 2 | 1 << 0));
tu6_emit_vs<CHIP>(cs, vs, 0);
tu6_emit_hs<CHIP>(cs, NULL);
@@ -948,11 +948,11 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
.persp_division_disable = 1,));
tu_cs_emit_regs(cs, A6XX_GRAS_SU_CNTL()); // XXX msaa enable?
tu_cs_emit_regs(cs, PC_RASTER_CNTL(CHIP));
tu_cs_emit_regs(cs, VPC_RAST_STREAM_CNTL(CHIP));
if (CHIP == A6XX) {
tu_cs_emit_regs(cs, A6XX_VPC_UNKNOWN_9107());
} else {
tu_cs_emit_regs(cs, A7XX_PC_RASTER_CNTL_V2());
tu_cs_emit_regs(cs, A7XX_VPC_RAST_STREAM_CNTL_V2());
tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP,
.raster_mode = TYPE_TILED,
@@ -975,15 +975,15 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, enum r3d_type type,
if (rts_mask) {
unsigned rts_count = util_last_bit(rts_mask);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), rts_count);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_OUTPUT_REG(0), rts_count);
unsigned rt = 0;
for (unsigned i = 0; i < rts_count; i++) {
unsigned regid = 0;
if (rts_mask & (1u << i))
regid = ir3_find_output_regid(fs, FRAG_RESULT_DATA0 + rt++);
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(regid) |
tu_cs_emit(cs, A6XX_SP_PS_OUTPUT_REG_REGID(regid) |
COND(regid & HALF_REG_ID,
A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
A6XX_SP_PS_OUTPUT_REG_HALF_PRECISION));
}
}
@@ -1147,7 +1147,7 @@ r3d_src_common(struct tu_cmd_buffer *cmd,
CP_LOAD_STATE6_0_NUM_UNIT(1));
tu_cs_emit_qw(cs, texture.iova + A6XX_TEX_CONST_DWORDS * 4);
tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_SAMP(.qword = texture.iova + A6XX_TEX_CONST_DWORDS * 4));
tu_cs_emit_regs(cs, A6XX_SP_PS_SAMPLER_BASE(.qword = texture.iova + A6XX_TEX_CONST_DWORDS * 4));
tu_cs_emit_pkt7(cs, CP_LOAD_STATE6_FRAG, 3);
tu_cs_emit(cs, CP_LOAD_STATE6_0_DST_OFF(0) |
@@ -1157,8 +1157,8 @@ r3d_src_common(struct tu_cmd_buffer *cmd,
CP_LOAD_STATE6_0_NUM_UNIT(1));
tu_cs_emit_qw(cs, texture.iova);
tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
tu_cs_emit_regs(cs, A6XX_SP_FS_TEX_COUNT(1));
tu_cs_emit_regs(cs, A6XX_SP_PS_TEXMEMOBJ_BASE(.qword = texture.iova));
tu_cs_emit_regs(cs, A6XX_SP_PS_TSIZE(1));
}
static void
@@ -1410,13 +1410,13 @@ r3d_dst(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer,
A6XX_RB_MRT_BASE_GMEM(0),
);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(0), 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_COLOR_FLAG_BUFFER(0), 3);
tu_cs_image_flag_ref(cs, iview, layer);
/* Use color format from RB_MRT_BUF_INFO. This register is relevant for
* FMT6_NV12_Y.
*/
tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUF_INFO_0(.color_format = fmt));
tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = fmt));
tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP, .flag_mrts = iview->ubwc_enabled));
tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL());
@@ -1434,7 +1434,7 @@ r3d_dst_depth(struct tu_cs *cs, const struct tu_image_view *iview, uint32_t laye
A6XX_RB_MRT_BASE_GMEM(0),
);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER(0), 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_COLOR_FLAG_BUFFER(0), 3);
tu_cs_image_flag_ref(cs, &iview->view, layer);
tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP, .flag_mrts = iview->view.ubwc_enabled));
@@ -1511,7 +1511,7 @@ r3d_dst_gmem(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
enum a6xx_format color_format = (enum a6xx_format) pkt_field_get(
A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT, RB_MRT_BUF_INFO);
tu_cs_emit_regs(cs,
A6XX_GRAS_LRZ_MRT_BUF_INFO_0(.color_format = color_format));
A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = color_format));
tu_cs_emit_regs(cs, RB_RENDER_CNTL(CHIP));
tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL());
@@ -1583,17 +1583,17 @@ r3d_setup(struct tu_cmd_buffer *cmd,
if (!(blit_param & R3D_DST_GMEM)) {
if (CHIP == A6XX) {
tu_cs_emit_regs(cs, A6XX_GRAS_BIN_CONTROL(.buffers_location = BUFFERS_IN_SYSMEM));
tu_cs_emit_regs(cs, A6XX_GRAS_SC_BIN_CNTL(.buffers_location = BUFFERS_IN_SYSMEM));
} else {
tu_cs_emit_regs(cs, A6XX_GRAS_BIN_CONTROL());
tu_cs_emit_regs(cs, A6XX_GRAS_SC_BIN_CNTL());
}
tu_cs_emit_regs(cs, RB_BIN_CONTROL(CHIP, .buffers_location = BUFFERS_IN_SYSMEM));
tu_cs_emit_regs(cs, RB_CNTL(CHIP, .buffers_location = BUFFERS_IN_SYSMEM));
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8812(0x3ff));
tu_cs_emit_regs(cs,
A7XX_RB_UNKNOWN_8E06(cmd->device->physical_device->info->a6xx.magic.RB_UNKNOWN_8E06));
A7XX_RB_CCU_DBG_ECO_CNTL(cmd->device->physical_device->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
}
}
@@ -1611,8 +1611,8 @@ r3d_setup(struct tu_cmd_buffer *cmd,
r3d_common<CHIP>(cmd, cs, type, 1, blit_param & R3D_Z_SCALE, samples);
tu_cs_emit_regs(cs, A6XX_SP_FS_OUTPUT_CNTL1(.mrt = 1));
tu_cs_emit_regs(cs, A6XX_RB_FS_OUTPUT_CNTL1(.mrt = 1));
tu_cs_emit_regs(cs, A6XX_SP_PS_MRT_CNTL(.mrt = 1));
tu_cs_emit_regs(cs, A6XX_RB_PS_MRT_CNTL(.mrt = 1));
tu_cs_emit_regs(cs, A6XX_SP_BLEND_CNTL());
tu_cs_emit_regs(cs, A6XX_RB_BLEND_CNTL(.sample_mask = 0xffff));
@@ -1620,13 +1620,13 @@ r3d_setup(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A6XX_RB_DEPTH_CNTL());
tu_cs_emit_regs(cs, A6XX_GRAS_SU_DEPTH_CNTL());
tu_cs_emit_regs(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL());
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CONTROL());
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CNTL());
tu_cs_emit_regs(cs, A6XX_GRAS_SU_STENCIL_CNTL());
tu_cs_emit_regs(cs, A6XX_RB_STENCILMASK());
tu_cs_emit_regs(cs, A6XX_RB_STENCILWRMASK());
tu_cs_emit_regs(cs, A6XX_RB_STENCILREF());
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_MASK());
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_WRITE_MASK());
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_REF_CNTL());
tu_cs_emit_regs(cs, A6XX_SP_FS_MRT_REG(0,
tu_cs_emit_regs(cs, A6XX_SP_PS_MRT_REG(0,
.color_format = fmt,
.color_sint = util_format_is_pure_sint(dst_format),
.color_uint = util_format_is_pure_uint(dst_format)));
@@ -1643,16 +1643,16 @@ r3d_setup(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CNTL2(0));
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_BUFFER_INFO());
tu_cs_emit_regs(cs, A6XX_RB_FSR_CONFIG());
tu_cs_emit_regs(cs, A7XX_SP_FSR_CONFIG());
tu_cs_emit_regs(cs, A7XX_GRAS_FSR_CONFIG());
tu_cs_emit_regs(cs, A6XX_RB_VRS_CONFIG());
tu_cs_emit_regs(cs, A7XX_SP_VRS_CONFIG());
tu_cs_emit_regs(cs, A7XX_GRAS_VRS_CONFIG());
}
tu_cs_emit_write_reg(cs, REG_A6XX_GRAS_SC_CNTL,
A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
/* Disable sample counting in order to not affect occlusion query. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = true));
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.disable = true));
tu_cs_emit_regs(cs, A6XX_RB_DITHER_CNTL());
if (CHIP >= A7XX) {
@@ -1701,7 +1701,7 @@ r3d_teardown(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
}
/* Re-enable sample counting. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = false));
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.disable = false));
if (cmd->state.prim_generated_query_running_before_rp) {
tu_emit_event_write<CHIP>(cmd, cs, FD_START_PRIMITIVE_CTRS);
@@ -1925,14 +1925,14 @@ event_blit_setup(struct tu_cs *cs,
uint32_t clear_mask)
{
tu_cs_emit_regs(
cs, A6XX_RB_BLIT_GMEM_MSAA_CNTL(tu_msaa_samples(att->samples)));
cs, A6XX_RB_RESOLVE_GMEM_BUFFER_INFO(tu_msaa_samples(att->samples)));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CNTL_0, 1);
tu_cs_emit(cs, 0);
tu_cs_emit_regs(
cs,
A6XX_RB_BLIT_INFO(.type = blit_event_type,
A6XX_RB_RESOLVE_OPERATION(.type = blit_event_type,
.sample_0 =
vk_format_is_int(att->format) ||
vk_format_is_depth_or_stencil(att->format),
@@ -1983,36 +1983,36 @@ event_blit_run(struct tu_cmd_buffer *cmd,
const event_blit_dst_view *blt_view,
bool separate_stencil)
{
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 4);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO, 4);
if (blt_view->image->vk.format == VK_FORMAT_D32_SFLOAT_S8_UINT) {
if (!separate_stencil) {
tu_cs_emit(cs, tu_fdl_view_depth(blt_view->view, RB_BLIT_DST_INFO));
tu_cs_emit(cs, tu_fdl_view_depth(blt_view->view, RB_RESOLVE_SYSTEM_BUFFER_INFO));
tu_cs_emit_qw(cs, blt_view->depth_addr);
tu_cs_emit(cs, A6XX_RB_2D_DST_PITCH(blt_view->depth_pitch).value);
tu_cs_emit(cs, A6XX_RB_A2D_DEST_BUFFER_PITCH(blt_view->depth_pitch).value);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE, 3);
tu_cs_image_flag_ref(cs, blt_view->view, blt_view->layer);
} else {
tu_cs_emit(cs, tu_fdl_view_stencil(blt_view->view, RB_BLIT_DST_INFO) &
~A6XX_RB_BLIT_DST_INFO_FLAGS);
tu_cs_emit(cs, tu_fdl_view_stencil(blt_view->view, RB_RESOLVE_SYSTEM_BUFFER_INFO) &
~A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_FLAGS);
tu_cs_emit_qw(cs, blt_view->stencil_addr);
tu_cs_emit(cs, A6XX_RB_BLIT_DST_PITCH(blt_view->stencil_pitch).value);
tu_cs_emit(cs, A6XX_RB_RESOLVE_SYSTEM_BUFFER_PITCH(blt_view->stencil_pitch).value);
}
} else {
tu_cs_emit(cs, blt_view->view->RB_BLIT_DST_INFO);
tu_cs_emit(cs, blt_view->view->RB_RESOLVE_SYSTEM_BUFFER_INFO);
tu_cs_image_ref_2d<CHIP>(cs, blt_view->view, blt_view->layer, false);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_FLAG_DST, 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE, 3);
tu_cs_image_flag_ref(cs, blt_view->view, blt_view->layer);
}
if (att) {
if (att->format == VK_FORMAT_D32_SFLOAT_S8_UINT && separate_stencil) {
tu_cs_emit_regs(
cs, A6XX_RB_BLIT_BASE_GMEM(tu_attachment_gmem_offset_stencil(
cs, A6XX_RB_RESOLVE_GMEM_BUFFER_BASE(tu_attachment_gmem_offset_stencil(
cmd, att, blt_view->layer)));
} else {
tu_cs_emit_regs(cs, A6XX_RB_BLIT_BASE_GMEM(tu_attachment_gmem_offset(
tu_cs_emit_regs(cs, A6XX_RB_RESOLVE_GMEM_BUFFER_BASE(tu_attachment_gmem_offset(
cmd, att, blt_view->layer)));
}
}
@@ -2038,7 +2038,7 @@ tu7_generic_layer_clear(struct tu_cmd_buffer *cmd,
uint32_t clear_vals[4] = {};
pack_blit_event_clear_value(value, format, clear_vals);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 4);
tu_cs_emit_array(cs, clear_vals, 4);
event_blit_dst_view blt_view = blt_view_from_tu_view(iview, layer);
@@ -2282,7 +2282,7 @@ tu6_blit_image(struct tu_cmd_buffer *cmd,
* when sampling, which is normally handled with the texture descriptor
* swizzle. The 2d path can't handle that, so use the 3d path.
*
* TODO: we could use RB_2D_BLIT_CNTL::MASK to make these formats work with
* TODO: we could use RB_A2D_BLT_CNTL::MASK to make these formats work with
* the 2d path.
*/
@@ -2319,15 +2319,15 @@ tu6_blit_image(struct tu_cmd_buffer *cmd,
r3d_coords_raw(cmd, cs, coords);
} else {
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_DST_TL(.x = MIN2(info->dstOffsets[0].x, info->dstOffsets[1].x),
A6XX_GRAS_A2D_DEST_TL(.x = MIN2(info->dstOffsets[0].x, info->dstOffsets[1].x),
.y = MIN2(info->dstOffsets[0].y, info->dstOffsets[1].y)),
A6XX_GRAS_2D_DST_BR(.x = MAX2(info->dstOffsets[0].x, info->dstOffsets[1].x) - 1,
A6XX_GRAS_A2D_DEST_BR(.x = MAX2(info->dstOffsets[0].x, info->dstOffsets[1].x) - 1,
.y = MAX2(info->dstOffsets[0].y, info->dstOffsets[1].y) - 1));
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_SRC_TL_X(MIN2(info->srcOffsets[0].x, info->srcOffsets[1].x)),
A6XX_GRAS_2D_SRC_BR_X(MAX2(info->srcOffsets[0].x, info->srcOffsets[1].x) - 1),
A6XX_GRAS_2D_SRC_TL_Y(MIN2(info->srcOffsets[0].y, info->srcOffsets[1].y)),
A6XX_GRAS_2D_SRC_BR_Y(MAX2(info->srcOffsets[0].y, info->srcOffsets[1].y) - 1));
A6XX_GRAS_A2D_SRC_XMIN(MIN2(info->srcOffsets[0].x, info->srcOffsets[1].x)),
A6XX_GRAS_A2D_SRC_XMAX(MAX2(info->srcOffsets[0].x, info->srcOffsets[1].x) - 1),
A6XX_GRAS_A2D_SRC_YMIN(MIN2(info->srcOffsets[0].y, info->srcOffsets[1].y)),
A6XX_GRAS_A2D_SRC_YMAX(MAX2(info->srcOffsets[0].y, info->srcOffsets[1].y) - 1));
}
struct fdl6_view dst, src;
@@ -3739,13 +3739,13 @@ clear_image_event_blit(struct tu_cmd_buffer *cmd,
struct tu_cs *cs = &cmd->cs;
tu_cs_emit_regs(cs,
A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_SYSMEM));
A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_SYSMEM));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CNTL_0, 1);
tu_cs_emit(cs, 0);
tu_cs_emit_regs(
cs, A6XX_RB_BLIT_INFO(
cs, A6XX_RB_RESOLVE_OPERATION(
.type = BLIT_EVENT_CLEAR,
.sample_0 = vk_format_is_int(vk_format) ||
vk_format_is_depth_or_stencil(vk_format),
@@ -3755,7 +3755,7 @@ clear_image_event_blit(struct tu_cmd_buffer *cmd,
uint32_t clear_vals[4] = {};
pack_blit_event_clear_value(clear_value, format, clear_vals);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 4);
tu_cs_emit_array(cs, clear_vals, 4);
for (unsigned level = 0; level < level_count; level++) {
@@ -3768,8 +3768,8 @@ clear_image_event_blit(struct tu_cmd_buffer *cmd,
uint32_t height =
u_minify(image->layout[0].height0, range->baseMipLevel + level);
tu_cs_emit_regs(
cs, A6XX_RB_BLIT_SCISSOR_TL(.x = 0, .y = 0),
A6XX_RB_BLIT_SCISSOR_BR(.x = width - 1, .y = height - 1));
cs, A6XX_RB_RESOLVE_CNTL_1(.x = 0, .y = 0),
A6XX_RB_RESOLVE_CNTL_2(.x = width - 1, .y = height - 1));
struct fdl6_view dst;
const VkImageSubresourceLayers subresource = {
@@ -4078,28 +4078,28 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
}
cmd->state.dirty |= TU_CMD_DIRTY_DRAW_STATE;
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 2);
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(0xfc) |
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(0xfc) |
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_OUTPUT_CNTL, 2);
tu_cs_emit(cs, A6XX_SP_PS_OUTPUT_CNTL_DEPTH_REGID(0xfc) |
A6XX_SP_PS_OUTPUT_CNTL_SAMPMASK_REGID(0xfc) |
0xfc000000);
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL1_MRT(mrt_count));
tu_cs_emit(cs, A6XX_SP_PS_MRT_CNTL_MRT(mrt_count));
r3d_common<CHIP>(cmd, cs, R3D_CLEAR, clear_rts, false, cmd->state.subpass->samples);
/* Disable sample counting in order to not affect occlusion query. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = true));
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.disable = true));
if (cmd->state.prim_generated_query_running_before_rp) {
tu_emit_event_write<CHIP>(cmd, cs, FD_STOP_PRIMITIVE_CTRS);
}
tu_cs_emit_regs(cs,
A6XX_SP_FS_RENDER_COMPONENTS(.dword = clear_components));
A6XX_SP_PS_OUTPUT_MASK(.dword = clear_components));
tu_cs_emit_regs(cs,
A6XX_RB_RENDER_COMPONENTS(.dword = clear_components));
A6XX_RB_PS_OUTPUT_MASK(.dword = clear_components));
tu_cs_emit_regs(cs,
A6XX_RB_FS_OUTPUT_CNTL1(.mrt = mrt_count));
A6XX_RB_PS_MRT_CNTL(.mrt = mrt_count));
tu_cs_emit_regs(cs, A6XX_SP_BLEND_CNTL());
tu_cs_emit_regs(cs, A6XX_RB_BLEND_CNTL(.independent_blend = 1, .sample_mask = 0xffff));
@@ -4118,14 +4118,14 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
.zfunc = FUNC_ALWAYS));
tu_cs_emit_regs(cs, A6XX_GRAS_SU_DEPTH_CNTL(z_clear));
tu_cs_emit_regs(cs, A6XX_GRAS_SU_DEPTH_PLANE_CNTL());
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CONTROL(
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CNTL(
.stencil_enable = s_clear,
.func = FUNC_ALWAYS,
.zpass = STENCIL_REPLACE));
tu_cs_emit_regs(cs, A6XX_GRAS_SU_STENCIL_CNTL(s_clear));
tu_cs_emit_regs(cs, A6XX_RB_STENCILMASK(.mask = 0xff));
tu_cs_emit_regs(cs, A6XX_RB_STENCILWRMASK(.wrmask = 0xff));
tu_cs_emit_regs(cs, A6XX_RB_STENCILREF(.ref = s_clear_val));
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_MASK(.mask = 0xff));
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_WRITE_MASK(.wrmask = 0xff));
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_REF_CNTL(.ref = s_clear_val));
tu_cs_emit_regs(cs, A6XX_GRAS_SC_CNTL(.ccusinglecachelinesize = 2));
@@ -4192,7 +4192,7 @@ tu_clear_sysmem_attachments(struct tu_cmd_buffer *cmd,
}
/* Re-enable sample counting. */
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNT_CONTROL(.disable = false));
tu_cs_emit_regs(cs, A6XX_RB_SAMPLE_COUNTER_CNTL(.disable = false));
if (cmd->state.prim_generated_query_running_before_rp) {
tu_emit_event_write<CHIP>(cmd, cs, FD_START_PRIMITIVE_CTRS);
@@ -4214,24 +4214,24 @@ clear_gmem_attachment(struct tu_cmd_buffer *cmd,
uint32_t gmem_offset,
const VkClearValue *value)
{
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_DST_INFO, 1);
tu_cs_emit(cs, A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO, 1);
tu_cs_emit(cs, A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_FORMAT(
blit_base_format<CHIP>(format, false, true)));
tu_cs_emit_regs(cs, A6XX_RB_BLIT_INFO(.type = BLIT_EVENT_CLEAR,
tu_cs_emit_regs(cs, A6XX_RB_RESOLVE_OPERATION(.type = BLIT_EVENT_CLEAR,
.clear_mask = clear_mask,
.buffer_id = buffer_id));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_GMEM_BUFFER_BASE, 1);
tu_cs_emit(cs, gmem_offset);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_UNKNOWN_88D0, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CNTL_0, 1);
tu_cs_emit(cs, 0);
uint32_t clear_vals[4] = {};
pack_blit_event_clear_value(value, format, clear_vals);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 4);
tu_cs_emit_array(cs, clear_vals, 4);
tu_emit_event_write<CHIP>(cmd, cs, FD_BLIT);
@@ -4267,11 +4267,11 @@ fdm_apply_gmem_clear_coords(struct tu_cmd_buffer *cmd,
unsigned y2 = DIV_ROUND_UP(state->rect.offset.y + state->rect.extent.height,
frag_area.height) + offset.y - 1;
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
tu_cs_emit(cs,
A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
A6XX_RB_RESOLVE_CNTL_1_X(x1) | A6XX_RB_RESOLVE_CNTL_1_Y(y1));
tu_cs_emit(cs,
A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
A6XX_RB_RESOLVE_CNTL_2_X(x2) | A6XX_RB_RESOLVE_CNTL_2_Y(y2));
}
template <chip CHIP>
@@ -4293,7 +4293,7 @@ tu_emit_clear_gmem_attachment(struct tu_cmd_buffer *cmd,
trace_start_gmem_clear(&cmd->rp_trace, cs, cmd, att->format, att->samples);
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_GMEM_MSAA_CNTL(tu_msaa_samples(att->samples)));
A6XX_RB_RESOLVE_GMEM_BUFFER_INFO(tu_msaa_samples(att->samples)));
enum pipe_format format = vk_format_to_pipe_format(att->format);
for_each_layer(i, layer_mask, layers) {
@@ -4368,9 +4368,9 @@ tu_clear_gmem_attachments(struct tu_cmd_buffer *cmd,
fdm_rect = &rects[i].rect;
}
} else {
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
tu_cs_emit(cs, A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
tu_cs_emit(cs, A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
tu_cs_emit(cs, A6XX_RB_RESOLVE_CNTL_1_X(x1) | A6XX_RB_RESOLVE_CNTL_1_Y(y1));
tu_cs_emit(cs, A6XX_RB_RESOLVE_CNTL_2_X(x2) | A6XX_RB_RESOLVE_CNTL_2_Y(y2));
}
for (unsigned j = 0; j < attachment_count; j++) {
@@ -4487,11 +4487,11 @@ tu7_clear_attachment_generic_single_rect(
unsigned y1 = rect->rect.offset.y;
unsigned x2 = x1 + rect->rect.extent.width - 1;
unsigned y2 = y1 + rect->rect.extent.height - 1;
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
tu_cs_emit(cs,
A6XX_RB_BLIT_SCISSOR_TL_X(x1) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1));
A6XX_RB_RESOLVE_CNTL_1_X(x1) | A6XX_RB_RESOLVE_CNTL_1_Y(y1));
tu_cs_emit(cs,
A6XX_RB_BLIT_SCISSOR_BR_X(x2) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2));
A6XX_RB_RESOLVE_CNTL_2_X(x2) | A6XX_RB_RESOLVE_CNTL_2_Y(y2));
}
auto value = &clear_att->clearValue;
@@ -4818,7 +4818,7 @@ tu_emit_blit(struct tu_cmd_buffer *cmd,
uint32_t clear_vals[4] = {};
pack_blit_event_clear_value(clear_value, format, clear_vals);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 4);
tu_cs_emit_array(cs, clear_vals, 4);
}
@@ -5132,7 +5132,7 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
}
tu_cs_emit_regs(cs,
SP_PS_2D_SRC_INFO(CHIP,
TPL1_A2D_SRC_TEXTURE_INFO(CHIP,
.color_format = format,
.tile_mode = TILE6_2,
.color_swap = fmt.swap,
@@ -5143,11 +5143,11 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
.unk20 = 1,
.unk22 = 1,
.mutableen = src_iview->view.is_mutable),
SP_PS_2D_SRC_SIZE(CHIP,
TPL1_A2D_SRC_TEXTURE_SIZE(CHIP,
.width = src_width,
.height = src_height),
SP_PS_2D_SRC(CHIP, .qword = cmd->device->physical_device->gmem_base + gmem_offset),
SP_PS_2D_SRC_PITCH(CHIP, .pitch = cmd->state.tiling->tile0.width * cpp));
TPL1_A2D_SRC_TEXTURE_BASE(CHIP, .qword = cmd->device->physical_device->gmem_base + gmem_offset),
TPL1_A2D_SRC_TEXTURE_PITCH(CHIP, .pitch = cmd->state.tiling->tile0.width * cpp));
/* sync GMEM writes with CACHE. */
tu_emit_event_write<CHIP>(cmd, cs, FD_CACHE_INVALIDATE);
@@ -5184,14 +5184,14 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
uint32_t gmem_offset,
uint32_t cpp)
{
/* RB_BIN_CONTROL/GRAS_BIN_CONTROL are normally only set once and they
/* RB_CNTL/GRAS_SC_BIN_CNTL are normally only set once and they
* aren't set until we know whether we're HW binning or not, and we want to
* avoid a dependence on that here to be able to store attachments before
* the end of the renderpass in the future. Use the scratch space to
* save/restore them dynamically.
*/
tu_cs_emit_pkt7(cs, CP_REG_TO_SCRATCH, 1);
tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(REG_A6XX_RB_BIN_CONTROL) |
tu_cs_emit(cs, CP_REG_TO_SCRATCH_0_REG(REG_A6XX_RB_CNTL) |
CP_REG_TO_SCRATCH_0_SCRATCH(0) |
CP_REG_TO_SCRATCH_0_CNT(1 - 1));
if (CHIP >= A7XX) {
@@ -5235,14 +5235,14 @@ store_3d_blit(struct tu_cmd_buffer *cmd,
*/
tu_emit_event_write<CHIP>(cmd, cs, FD_CCU_CLEAN_COLOR);
/* Restore RB_BIN_CONTROL/GRAS_BIN_CONTROL saved above. */
/* Restore RB_CNTL/GRAS_SC_BIN_CNTL saved above. */
tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_RB_BIN_CONTROL) |
tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_RB_CNTL) |
CP_SCRATCH_TO_REG_0_SCRATCH(0) |
CP_SCRATCH_TO_REG_0_CNT(1 - 1));
tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_GRAS_BIN_CONTROL) |
tu_cs_emit(cs, CP_SCRATCH_TO_REG_0_REG(REG_A6XX_GRAS_SC_BIN_CNTL) |
CP_SCRATCH_TO_REG_0_SCRATCH(0) |
CP_SCRATCH_TO_REG_0_CNT(1 - 1));
@@ -5377,15 +5377,15 @@ fdm_apply_store_coords(struct tu_cmd_buffer *cmd,
uint32_t scaled_height = bin.extent.height / frag_area.height;
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_DST_TL(.x = bin.offset.x,
A6XX_GRAS_A2D_DEST_TL(.x = bin.offset.x,
.y = bin.offset.y),
A6XX_GRAS_2D_DST_BR(.x = bin.offset.x + bin.extent.width - 1,
A6XX_GRAS_A2D_DEST_BR(.x = bin.offset.x + bin.extent.width - 1,
.y = bin.offset.y + bin.extent.height - 1));
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_SRC_TL_X(common_bin_offset.x),
A6XX_GRAS_2D_SRC_BR_X(common_bin_offset.x + scaled_width - 1),
A6XX_GRAS_2D_SRC_TL_Y(common_bin_offset.y),
A6XX_GRAS_2D_SRC_BR_Y(common_bin_offset.y + scaled_height - 1));
A6XX_GRAS_A2D_SRC_XMIN(common_bin_offset.x),
A6XX_GRAS_A2D_SRC_XMAX(common_bin_offset.x + scaled_width - 1),
A6XX_GRAS_A2D_SRC_YMIN(common_bin_offset.y),
A6XX_GRAS_A2D_SRC_YMAX(common_bin_offset.y + scaled_height - 1));
}
template <chip CHIP>
@@ -5508,9 +5508,9 @@ tu_store_gmem_attachment(struct tu_cmd_buffer *cmd,
* area.
*/
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = render_area->offset.x,
A6XX_GRAS_A2D_SCISSOR_TL(.x = render_area->offset.x,
.y = render_area->offset.y,),
A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = render_area->offset.x + render_area->extent.width - 1,
A6XX_GRAS_A2D_SCISSOR_BR(.x = render_area->offset.x + render_area->extent.width - 1,
.y = render_area->offset.y + render_area->extent.height - 1,));
}
src/freedreno/vulkan/tu_cmd_buffer.cc
+145 -145
View File
@@ -163,8 +163,8 @@ tu6_lazy_emit_tessfactor_addr(struct tu_cmd_buffer *cmd)
if (cmd->state.tessfactor_addr_set)
return;
tu_cs_emit_regs(&cmd->cs, PC_TESSFACTOR_ADDR(CHIP, .qword = cmd->device->tess_bo->iova));
/* Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it. */
tu_cs_emit_regs(&cmd->cs, PC_TESS_BASE(CHIP, .qword = cmd->device->tess_bo->iova));
/* Updating PC_TESS_BASE could race with the next draw which uses it. */
cmd->state.cache.flush_bits |= TU_CMD_FLAG_WAIT_FOR_IDLE;
cmd->state.tessfactor_addr_set = true;
}
@@ -217,18 +217,18 @@ tu_emit_vsc(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
if (CHIP == A6XX) {
tu_cs_emit_regs(cs,
A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.qword = cmd->vsc_draw_strm_size_va));
A6XX_VSC_SIZE_BASE(.qword = cmd->vsc_draw_strm_size_va));
tu_cs_emit_regs(cs,
A6XX_VSC_PRIM_STRM_ADDRESS(.qword = cmd->vsc_prim_strm_va));
A6XX_VSC_PIPE_DATA_PRIM_BASE(.qword = cmd->vsc_prim_strm_va));
tu_cs_emit_regs(
cs, A6XX_VSC_DRAW_STRM_ADDRESS(.qword = cmd->vsc_draw_strm_va));
cs, A6XX_VSC_PIPE_DATA_DRAW_BASE(.qword = cmd->vsc_draw_strm_va));
} else {
tu_cs_emit_pkt7(cs, CP_SET_PSEUDO_REG, 3 * 3);
tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(DRAW_STRM_ADDRESS));
tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(VSC_PIPE_DATA_DRAW_BASE));
tu_cs_emit_qw(cs, cmd->vsc_draw_strm_va);
tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(DRAW_STRM_SIZE_ADDRESS));
tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(VSC_SIZE_BASE));
tu_cs_emit_qw(cs, cmd->vsc_draw_strm_size_va);
tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(PRIM_STRM_ADDRESS));
tu_cs_emit(cs, A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(VSC_PIPE_DATA_PRIM_BASE));
tu_cs_emit_qw(cs, cmd->vsc_prim_strm_va);
}
@@ -246,10 +246,10 @@ tu_emit_rt_workaround(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit(cs, A6XX_CP_SET_MARKER_0_RT_WA_START);
tu_cs_emit_regs(cs, A7XX_SP_CS_UNKNOWN_A9BE(.dword = 0x10000));
tu_cs_emit_regs(cs, A7XX_SP_FS_UNKNOWN_A9AB(.dword = 0x10000));
tu_cs_emit_regs(cs, A7XX_SP_PS_UNKNOWN_A9AB(.dword = 0x10000));
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
tu_cs_emit_regs(cs, A7XX_SP_CS_UNKNOWN_A9BE(.dword = 0));
tu_cs_emit_regs(cs, A7XX_SP_FS_UNKNOWN_A9AB(.dword = 0));
tu_cs_emit_regs(cs, A7XX_SP_PS_UNKNOWN_A9AB(.dword = 0));
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
tu_emit_event_write<A7XX>(cmd, cs, FD_DUMMY_EVENT);
@@ -296,7 +296,7 @@ tu6_emit_flushes(struct tu_cmd_buffer *cmd_buffer,
if (flushes & TU_CMD_FLAG_CACHE_INVALIDATE)
tu_emit_event_write<CHIP>(cmd_buffer, cs, FD_CACHE_INVALIDATE);
if (flushes & TU_CMD_FLAG_BINDLESS_DESCRIPTOR_INVALIDATE) {
tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
tu_cs_emit_regs(cs, SP_UPDATE_CNTL(CHIP,
.cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
.gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,
));
@@ -388,7 +388,7 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem)
(a6xx_ccu_cache_size)(dev->physical_device->info->a6xx.gmem_ccu_color_cache_fraction);
if (CHIP == A7XX) {
tu_cs_emit_regs(cs, A7XX_RB_CCU_CNTL2(
tu_cs_emit_regs(cs, A7XX_RB_CCU_CACHE_CNTL(
.depth_offset_hi = depth_offset_hi,
.color_offset_hi = color_offset_hi,
.depth_cache_size = CCU_CACHE_SIZE_FULL,
@@ -399,16 +399,16 @@ emit_rb_ccu_cntl(struct tu_cs *cs, struct tu_device *dev, bool gmem)
if (dev->physical_device->info->a7xx.has_gmem_vpc_attr_buf) {
tu_cs_emit_regs(cs,
A7XX_VPC_ATTR_BUF_SIZE_GMEM(
A7XX_VPC_ATTR_BUF_GMEM_SIZE(
.size_gmem =
gmem ? dev->physical_device->vpc_attr_buf_size_gmem
: dev->physical_device->vpc_attr_buf_size_bypass),
A7XX_VPC_ATTR_BUF_BASE_GMEM(
A7XX_VPC_ATTR_BUF_GMEM_BASE(
.base_gmem =
gmem ? dev->physical_device->vpc_attr_buf_offset_gmem
: dev->physical_device->vpc_attr_buf_offset_bypass), );
tu_cs_emit_regs(cs,
A7XX_PC_ATTR_BUF_SIZE_GMEM(
A7XX_PC_ATTR_BUF_GMEM_SIZE(
.size_gmem =
gmem ? dev->physical_device->vpc_attr_buf_size_gmem
: dev->physical_device->vpc_attr_buf_size_bypass), );
@@ -448,7 +448,7 @@ tu_emit_cache_flush_ccu(struct tu_cmd_buffer *cmd_buffer,
* also need to flush. Also, in order to program RB_CCU_CNTL, we need to
* emit a WFI as it isn't pipelined.
*
* Note: On A7XX, with the introduction of RB_CCU_CNTL2, we no longer need
* Note: On A7XX, with the introduction of RB_CCU_CACHE_CNTL, we no longer need
* to emit a WFI when changing a subset of CCU state.
*/
if (ccu_state != cmd_buffer->state.ccu_state) {
@@ -493,12 +493,12 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd,
A6XX_RB_DEPTH_BUFFER_PITCH(0),
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
A6XX_RB_DEPTH_BUFFER_BASE(0),
A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
A6XX_RB_DEPTH_GMEM_BASE(0));
tu_cs_emit_regs(cs,
A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
tu_cs_emit_regs(cs, RB_STENCIL_INFO(CHIP, 0));
tu_cs_emit_regs(cs, RB_STENCIL_BUFFER_INFO(CHIP, 0));
return;
}
@@ -529,8 +529,8 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd,
if (attachment->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
attachment->format == VK_FORMAT_S8_UINT) {
tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_INFO, 6);
tu_cs_emit(cs, RB_STENCIL_INFO(CHIP,
tu_cs_emit_pkt4(cs, REG_A6XX_RB_STENCIL_BUFFER_INFO, 6);
tu_cs_emit(cs, RB_STENCIL_BUFFER_INFO(CHIP,
.separate_stencil = true,
.tilemode = TILE6_3,
).value);
@@ -543,7 +543,7 @@ tu6_emit_zs(struct tu_cmd_buffer *cmd,
}
} else {
tu_cs_emit_regs(cs,
RB_STENCIL_INFO(CHIP, 0));
RB_STENCIL_BUFFER_INFO(CHIP, 0));
}
}
@@ -578,13 +578,13 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd,
);
tu_cs_emit_regs(cs,
A6XX_SP_FS_MRT_REG(remapped, .dword = iview->view.SP_FS_MRT_REG));
A6XX_SP_PS_MRT_REG(remapped, .dword = iview->view.SP_PS_MRT_REG));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(remapped), 3);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_COLOR_FLAG_BUFFER_ADDR(remapped), 3);
tu_cs_image_flag_ref(cs, &iview->view, 0);
if (remapped == 0)
mrt0_format = (enum a6xx_format) (iview->view.SP_FS_MRT_REG & 0xff);
mrt0_format = (enum a6xx_format) (iview->view.SP_PS_MRT_REG & 0xff);
written |= 1u << remapped;
}
@@ -614,10 +614,10 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd,
);
tu_cs_emit_regs(cs,
A6XX_SP_FS_MRT_REG(i, .dword = 0));
A6XX_SP_PS_MRT_REG(i, .dword = 0));
}
tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUF_INFO_0(.color_format = mrt0_format));
tu_cs_emit_regs(cs, A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = mrt0_format));
const bool dither = subpass->legacy_dithering_enabled;
const uint32_t dither_cntl =
@@ -642,7 +642,7 @@ tu6_emit_mrt(struct tu_cmd_buffer *cmd,
A6XX_SP_SRGB_CNTL(.dword = subpass->srgb_cntl));
unsigned layers = MAX2(fb->layers, util_logbase2(subpass->multiview_mask) + 1);
tu_cs_emit_regs(cs, A6XX_GRAS_MAX_LAYER_INDEX(layers - 1));
tu_cs_emit_regs(cs, A6XX_GRAS_CL_ARRAY_SIZE(layers - 1));
}
struct tu_bin_size_params {
@@ -661,7 +661,7 @@ tu6_emit_bin_size(struct tu_cs *cs,
{
if (CHIP == A6XX) {
tu_cs_emit_regs(
cs, A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
cs, A6XX_GRAS_SC_BIN_CNTL(.binw = bin_w,
.binh = bin_h,
.render_mode = p.render_mode,
.force_lrz_write_dis = p.force_lrz_write_dis,
@@ -669,7 +669,7 @@ tu6_emit_bin_size(struct tu_cs *cs,
.lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, ));
} else {
tu_cs_emit_regs(cs,
A6XX_GRAS_BIN_CONTROL(.binw = bin_w,
A6XX_GRAS_SC_BIN_CNTL(.binw = bin_w,
.binh = bin_h,
.render_mode = p.render_mode,
.force_lrz_write_dis = p.force_lrz_write_dis,
@@ -677,7 +677,7 @@ tu6_emit_bin_size(struct tu_cs *cs,
p.lrz_feedback_zmode_mask, ));
}
tu_cs_emit_regs(cs, RB_BIN_CONTROL(CHIP,
tu_cs_emit_regs(cs, RB_CNTL(CHIP,
.binw = bin_w,
.binh = bin_h,
.render_mode = p.render_mode,
@@ -685,9 +685,9 @@ tu6_emit_bin_size(struct tu_cs *cs,
.buffers_location = p.buffers_location,
.lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask, ));
/* no flag for RB_BIN_CONTROL2... */
/* no flag for RB_RESOLVE_CNTL_3... */
tu_cs_emit_regs(cs,
A6XX_RB_BIN_CONTROL2(.binw = bin_w,
A6XX_RB_RESOLVE_CNTL_3(.binw = bin_w,
.binh = bin_h));
}
@@ -814,8 +814,8 @@ tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align,
*/
if (used_by_sysmem) {
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
A6XX_RB_RESOLVE_CNTL_1(.x = x1, .y = y1),
A6XX_RB_RESOLVE_CNTL_2(.x = x2, .y = y2));
tu_cond_exec_start(cs, CP_COND_REG_EXEC_0_MODE(RENDER_MODE) |
CP_COND_REG_EXEC_0_GMEM);
}
@@ -823,16 +823,16 @@ tu6_emit_blit_scissor(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool align,
x2 += tiling->tile0.width;
y2 += tiling->tile0.height;
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
A6XX_RB_RESOLVE_CNTL_1(.x = x1, .y = y1),
A6XX_RB_RESOLVE_CNTL_2(.x = x2, .y = y2));
if (used_by_sysmem) {
tu_cond_exec_end(cs);
}
} else {
tu_cs_emit_regs(cs,
A6XX_RB_BLIT_SCISSOR_TL(.x = x1, .y = y1),
A6XX_RB_BLIT_SCISSOR_BR(.x = x2, .y = y2));
A6XX_RB_RESOLVE_CNTL_1(.x = x1, .y = y1),
A6XX_RB_RESOLVE_CNTL_2(.x = x2, .y = y2));
}
}
@@ -848,8 +848,8 @@ tu6_emit_window_scissor(struct tu_cs *cs,
A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
tu_cs_emit_regs(cs,
A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
A6XX_GRAS_A2D_SCISSOR_TL(.x = x1, .y = y1),
A6XX_GRAS_A2D_SCISSOR_BR(.x = x2, .y = y2));
}
template <chip CHIP>
@@ -860,17 +860,17 @@ tu6_emit_window_offset(struct tu_cs *cs, uint32_t x1, uint32_t y1)
A6XX_RB_WINDOW_OFFSET(.x = x1, .y = y1));
tu_cs_emit_regs(cs,
A6XX_RB_WINDOW_OFFSET2(.x = x1, .y = y1));
A6XX_RB_RESOLVE_WINDOW_OFFSET(.x = x1, .y = y1));
tu_cs_emit_regs(cs,
SP_WINDOW_OFFSET(CHIP, .x = x1, .y = y1));
tu_cs_emit_regs(cs,
A6XX_SP_TP_WINDOW_OFFSET(.x = x1, .y = y1));
A6XX_TPL1_WINDOW_OFFSET(.x = x1, .y = y1));
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs,
A7XX_SP_PS_2D_WINDOW_OFFSET(.x = x1, .y = y1));
A7XX_TPL1_A2D_WINDOW_OFFSET(.x = x1, .y = y1));
}
}
@@ -1001,14 +1001,14 @@ tu6_emit_msaa(struct tu_cs *cs, VkSampleCountFlagBits vk_samples,
const enum a3xx_msaa_samples samples = tu_msaa_samples(vk_samples);
msaa_disable |= (samples == MSAA_ONE);
tu_cs_emit_regs(cs,
A6XX_SP_TP_RAS_MSAA_CNTL(samples),
A6XX_SP_TP_DEST_MSAA_CNTL(.samples = samples,
A6XX_TPL1_RAS_MSAA_CNTL(samples),
A6XX_TPL1_DEST_MSAA_CNTL(.samples = samples,
.msaa_disable = msaa_disable));
tu_cs_emit_regs(cs,
A6XX_GRAS_RAS_MSAA_CNTL(samples),
A6XX_GRAS_DEST_MSAA_CNTL(.samples = samples,
.msaa_disable = msaa_disable));
A6XX_GRAS_SC_RAS_MSAA_CNTL(samples),
A6XX_GRAS_SC_DEST_MSAA_CNTL(.samples = samples,
.msaa_disable = msaa_disable));
tu_cs_emit_regs(cs,
A6XX_RB_RAS_MSAA_CNTL(samples),
@@ -1176,7 +1176,7 @@ tu6_emit_cond_for_load_stores(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
if (vsc->binning_possible &&
cmd->state.pass->has_cond_load_store) {
tu_cs_emit_pkt7(cs, CP_REG_TEST, 1);
tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(pipe)) |
tu_cs_emit(cs, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_CHANNEL_VISIBILITY(pipe)) |
A6XX_CP_REG_TEST_0_BIT(slot) |
COND(skip_wfm, A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME));
} else {
@@ -1258,7 +1258,7 @@ tu6_emit_tile_select(struct tu_cmd_buffer *cmd,
});
tu_cs_emit_regs(cs,
A6XX_VFD_MODE_CNTL(RENDERING_PASS));
A6XX_VFD_RENDER_MODE(RENDERING_PASS));
const uint32_t x1 = tiling->tile0.width * tile->pos.x;
const uint32_t y1 = tiling->tile0.height * tile->pos.y;
@@ -1558,7 +1558,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
if (CHIP >= A7XX) {
/* On A7XX, RB_CCU_CNTL was broken into two registers, RB_CCU_CNTL which has
* static properties that can be set once, this requires a WFI to take effect.
* While the newly introduced register RB_CCU_CNTL2 has properties that may
* While the newly introduced register RB_CCU_CACHE_CNTL has properties that may
* change per-RP and don't require a WFI to take effect, only CCU inval/flush
* events are required.
*/
@@ -1599,10 +1599,10 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL,
phys_dev->info->a6xx.magic.RB_DBG_ECO_CNTL);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_NC_MODE_CNTL_2, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_DBG_ECO_CNTL,
phys_dev->info->a6xx.magic.SP_DBG_ECO_CNTL);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x3f);
if (CHIP == A6XX && !cs->device->physical_device->info->a6xx.is_a702)
tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
tu_cs_emit_write_reg(cs, REG_A6XX_TPL1_DBG_ECO_CNTL,
@@ -1622,7 +1622,7 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
}
tu_cs_emit_write_reg(cs, REG_A6XX_SP_CHICKEN_BITS,
phys_dev->info->a6xx.magic.SP_CHICKEN_BITS);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UAV_COUNT, 0); // 2 on a740 ???
tu_cs_emit_write_reg(cs, REG_A6XX_SP_GFX_USIZE, 0); // 2 on a740 ???
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B182, 0);
if (CHIP == A6XX)
tu_cs_emit_regs(cs, A6XX_HLSQ_SHARED_CONSTS(.enable = false));
@@ -1633,11 +1633,11 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8E01,
phys_dev->info->a6xx.magic.RB_UNKNOWN_8E01);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_A9A8, 0);
tu_cs_emit_regs(cs, A6XX_SP_MODE_CONTROL(.constant_demotion_enable = true,
tu_cs_emit_regs(cs, A6XX_SP_MODE_CNTL(.constant_demotion_enable = true,
.isammode = ISAMMODE_GL,
.shared_consts_enable = false));
tu_cs_emit_regs(cs, A6XX_VFD_ADD_OFFSET(.vertex = true, .instance = true));
tu_cs_emit_regs(cs, A6XX_VFD_MODE_CNTL(.vertex = true, .instance = true));
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL,
phys_dev->info->a6xx.magic.PC_MODE_CNTL);
@@ -1657,10 +1657,10 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_88F0, 0);
tu_cs_emit_regs(cs, A6XX_VPC_POINT_COORD_INVERT(false));
tu_cs_emit_regs(cs, A6XX_VPC_REPLACE_MODE_CNTL(false));
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9300, 0);
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(true));
tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_B183, 0);
@@ -1674,25 +1674,25 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
}
tu_cs_emit_write_reg(cs, REG_A6XX_VPC_UNKNOWN_9602, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9E72, 0);
tu_cs_emit_regs(cs, A6XX_SP_TP_MODE_CNTL(.isammode = ISAMMODE_GL,
tu_cs_emit_regs(cs, A6XX_TPL1_MODE_CNTL(.isammode = ISAMMODE_GL,
.texcoordroundmode = dev->instance->use_tex_coord_round_nearest_even_mode
? COORD_ROUND_NEAREST_EVEN
: COORD_TRUNCATE,
.nearestmipsnap = CLAMP_ROUND_TRUNCATE,
.destdatatypeoverride = true));
tu_cs_emit_regs(cs, HLSQ_CONTROL_5_REG(CHIP, .dword = 0xfc));
tu_cs_emit_regs(cs, SP_REG_PROG_ID_3(CHIP, .dword = 0xfc));
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_MODE_CNTL, 0x00000000);
tu_cs_emit_write_reg(cs, REG_A6XX_VFD_RENDER_MODE, 0x00000000);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, phys_dev->info->a6xx.magic.PC_MODE_CNTL);
tu_cs_emit_regs(cs, A6XX_RB_ALPHA_CONTROL()); /* always disable alpha test */
tu_cs_emit_regs(cs, A6XX_RB_ALPHA_TEST_CNTL()); /* always disable alpha test */
tu_cs_emit_regs(cs,
A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo = dev->global_bo,
A6XX_TPL1_GFX_BORDER_COLOR_BASE(.bo = dev->global_bo,
.bo_offset = gb_offset(bcolor)));
tu_cs_emit_regs(cs,
A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo = dev->global_bo,
A6XX_TPL1_CS_BORDER_COLOR_BASE(.bo = dev->global_bo,
.bo_offset = gb_offset(bcolor)));
if (CHIP == A7XX) {
@@ -1705,12 +1705,12 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
if (CHIP >= A7XX) {
/* Blob sets these two per draw. */
tu_cs_emit_regs(cs, A7XX_PC_TESS_PARAM_SIZE(TU_TESS_PARAM_SIZE));
tu_cs_emit_regs(cs, A7XX_PC_HS_BUFFER_SIZE(TU_TESS_PARAM_SIZE));
/* Blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
* but the meaning of this additional space is not known,
* so we play safe and don't add it.
*/
tu_cs_emit_regs(cs, A7XX_PC_TESS_FACTOR_SIZE(TU_TESS_FACTOR_SIZE));
tu_cs_emit_regs(cs, A7XX_PC_TF_BUFFER_SIZE(TU_TESS_FACTOR_SIZE));
}
/* There is an optimization to skip executing draw states for draws with no
@@ -1718,18 +1718,18 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
* sets a bit in PC_DRAW_INITIATOR that seemingly skips the draw. However
* there is a hardware bug where this bit does not always cause the FS
* early preamble to be skipped. Because the draw states were skipped,
* SP_FS_CTRL_REG0, SP_FS_OBJ_START and so on are never updated and a
* SP_PS_CNTL_0, SP_PS_BASE and so on are never updated and a
* random FS preamble from the last draw is executed. If the last visible
* draw is from the same submit, it shouldn't be a problem because we just
* re-execute the same preamble and preambles don't have side effects, but
* if it's from another process then we could execute a garbage preamble
* leading to hangs and faults. To make sure this doesn't happen, we reset
* SP_FS_CTRL_REG0 here, making sure that the EARLYPREAMBLE bit isn't set
* SP_PS_CNTL_0 here, making sure that the EARLYPREAMBLE bit isn't set
* so any leftover early preamble doesn't get executed. Other stages don't
* seem to be affected.
*/
if (phys_dev->info->a6xx.has_early_preamble) {
tu_cs_emit_regs(cs, A6XX_SP_FS_CTRL_REG0());
tu_cs_emit_regs(cs, A6XX_SP_PS_CNTL_0());
}
/* Workaround for draw state with constlen not being applied for
@@ -1737,8 +1737,8 @@ tu6_init_static_regs(struct tu_device *dev, struct tu_cs *cs)
* for more info.
*/
tu_cs_emit_pkt4(
cs, CHIP == A6XX ? REG_A6XX_HLSQ_VS_CNTL : REG_A7XX_HLSQ_VS_CNTL, 1);
tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(8) | A6XX_HLSQ_VS_CNTL_ENABLED);
cs, CHIP == A6XX ? REG_A6XX_SP_VS_CONST_CONFIG : REG_A7XX_SP_VS_CONST_CONFIG, 1);
tu_cs_emit(cs, A6XX_SP_VS_CONST_CONFIG_CONSTLEN(8) | A6XX_SP_VS_CONST_CONFIG_ENABLED);
}
/* Set always-identical registers used specifically for GMEM */
@@ -1748,14 +1748,14 @@ tu7_emit_tile_render_begin_regs(struct tu_cs *cs)
tu_cs_emit_regs(cs,
A7XX_RB_UNKNOWN_8812(0x0));
tu_cs_emit_regs(cs,
A7XX_RB_UNKNOWN_8E06(0x0));
A7XX_RB_CCU_DBG_ECO_CNTL(0x0));
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
tu_cs_emit_regs(cs, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_GMEM));
tu_cs_emit_regs(cs, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
}
/* Emit the bin restore preamble, which runs in between bins when L1
@@ -1791,7 +1791,7 @@ tu_emit_bin_preamble(struct tu_device *dev, struct tu_cs *cs)
* manually restore this state.
*/
tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VSC_STATE(0)) |
tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A6XX_VSC_CHANNEL_VISIBILITY(0)) |
CP_MEM_TO_REG_0_CNT(32));
tu_cs_emit_qw(cs, dev->global_bo->iova + gb_offset(vsc_state));
}
@@ -1832,7 +1832,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_wfi(cs);
}
tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
tu_cs_emit_regs(cs, SP_UPDATE_CNTL(CHIP,
.vs_state = true,
.hs_state = true,
.ds_state = true,
@@ -1920,19 +1920,19 @@ update_vsc_pipe(struct tu_cmd_buffer *cmd,
.height = tiling->tile0.height));
tu_cs_emit_regs(cs,
A6XX_VSC_BIN_COUNT(.nx = vsc->tile_count.width,
.ny = vsc->tile_count.height));
A6XX_VSC_EXPANDED_BIN_CNTL(.nx = vsc->tile_count.width,
.ny = vsc->tile_count.height));
tu_cs_emit_pkt4(cs, REG_A6XX_VSC_PIPE_CONFIG_REG(0), num_vsc_pipes);
tu_cs_emit_array(cs, vsc->pipe_config, num_vsc_pipes);
tu_cs_emit_regs(cs,
A6XX_VSC_PRIM_STRM_PITCH(cmd->vsc_prim_strm_pitch),
A6XX_VSC_PRIM_STRM_LIMIT(cmd->vsc_prim_strm_pitch - VSC_PAD));
A6XX_VSC_PIPE_DATA_PRIM_STRIDE(cmd->vsc_prim_strm_pitch),
A6XX_VSC_PIPE_DATA_PRIM_LENGTH(cmd->vsc_prim_strm_pitch - VSC_PAD));
tu_cs_emit_regs(cs,
A6XX_VSC_DRAW_STRM_PITCH(cmd->vsc_draw_strm_pitch),
A6XX_VSC_DRAW_STRM_LIMIT(cmd->vsc_draw_strm_pitch - VSC_PAD));
A6XX_VSC_PIPE_DATA_DRAW_STRIDE(cmd->vsc_draw_strm_pitch),
A6XX_VSC_PIPE_DATA_DRAW_LENGTH(cmd->vsc_draw_strm_pitch - VSC_PAD));
tu_cs_emit_regs(cs, A7XX_VSC_UNKNOWN_0D08(0));
}
@@ -1949,7 +1949,7 @@ emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PIPE_DATA_DRAW_SIZE(i)));
tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_draw_strm_pitch - VSC_PAD));
tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
@@ -1959,7 +1959,7 @@ emit_vsc_overflow_test(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_pkt7(cs, CP_COND_WRITE5, 8);
tu_cs_emit(cs, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
tu_cs_emit(cs, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PIPE_DATA_PRIM_SIZE(i)));
tu_cs_emit(cs, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
tu_cs_emit(cs, CP_COND_WRITE5_3_REF(cmd->vsc_prim_strm_pitch - VSC_PAD));
tu_cs_emit(cs, CP_COND_WRITE5_4_MASK(~0));
@@ -2049,7 +2049,7 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu_cs_emit_wfi(cs);
tu_cs_emit_regs(cs,
A6XX_VFD_MODE_CNTL(.render_mode = BINNING_PASS));
A6XX_VFD_RENDER_MODE(.render_mode = BINNING_PASS));
update_vsc_pipe(cmd, cs, phys_dev->info->num_vsc_pipes);
@@ -2068,7 +2068,7 @@ tu6_emit_binning_pass(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
A6XX_RB_WINDOW_OFFSET(.x = 0, .y = 0));
tu_cs_emit_regs(cs,
A6XX_SP_TP_WINDOW_OFFSET(.x = 0, .y = 0));
A6XX_TPL1_WINDOW_OFFSET(.x = 0, .y = 0));
trace_start_binning_ib(&cmd->trace, cs, cmd);
@@ -2261,9 +2261,9 @@ tu_emit_input_attachments(struct tu_cmd_buffer *cmd,
CP_LOAD_STATE6_0_NUM_UNIT(subpass->input_count * 2));
tu_cs_emit_qw(&cs, texture.iova);
tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_CONST(.qword = texture.iova));
tu_cs_emit_regs(&cs, A6XX_SP_PS_TEXMEMOBJ_BASE(.qword = texture.iova));
tu_cs_emit_regs(&cs, A6XX_SP_FS_TEX_COUNT(subpass->input_count * 2));
tu_cs_emit_regs(&cs, A6XX_SP_PS_TSIZE(subpass->input_count * 2));
assert(cs.cur == cs.end); /* validate draw state size */
@@ -2393,7 +2393,7 @@ tu_emit_renderpass_begin(struct tu_cmd_buffer *cmd)
*/
BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
MESA_VK_DYNAMIC_MS_RASTERIZATION_SAMPLES);
/* PC_PRIMITIVE_CNTL_0 isn't a part of a draw state and may be changed
/* PC_CNTL isn't a part of a draw state and may be changed
* by blits.
*/
BITSET_SET(cmd->vk.dynamic_graphics_state.dirty,
@@ -2430,14 +2430,14 @@ tu6_sysmem_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
tu_cs_emit_regs(cs,
A7XX_RB_UNKNOWN_8812(0x3ff)); // all buffers in sysmem
tu_cs_emit_regs(cs,
A7XX_RB_UNKNOWN_8E06(cmd->device->physical_device->info->a6xx.magic.RB_UNKNOWN_8E06));
A7XX_RB_CCU_DBG_ECO_CNTL(cmd->device->physical_device->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
tu_cs_emit_regs(cs, A7XX_GRAS_UNKNOWN_8007(0x0));
tu_cs_emit_regs(cs, A6XX_GRAS_UNKNOWN_8110(0x2));
tu_cs_emit_regs(cs, A7XX_RB_UNKNOWN_8E09(0x4));
tu_cs_emit_regs(cs, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_SYSMEM));
tu_cs_emit_regs(cs, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_SYSMEM));
}
tu_cs_emit_pkt7(cs, CP_SET_MARKER, 1);
@@ -2564,7 +2564,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
* the actual binner didn't run.
*/
int pipe_count = vsc->pipe_count.width * vsc->pipe_count.height;
tu_cs_emit_pkt4(cs, REG_A6XX_VSC_STATE_REG(0), pipe_count);
tu_cs_emit_pkt4(cs, REG_A6XX_VSC_CHANNEL_VISIBILITY(0), pipe_count);
for (int i = 0; i < pipe_count; i++)
tu_cs_emit(cs, ~0);
}
@@ -2575,7 +2575,7 @@ tu6_tile_render_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs,
* preemption.
*/
tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_VSC_STATE_REG(0)) |
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_VSC_CHANNEL_VISIBILITY(0)) |
CP_REG_TO_MEM_0_CNT(32));
tu_cs_emit_qw(cs, global_iova(cmd, vsc_state));
}
@@ -3531,8 +3531,8 @@ tu_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer,
for (uint32_t i = 0; i < cmd->state.max_vbs_bound; i++) {
tu_cs_emit_regs(&cs,
A6XX_VFD_FETCH_BASE(i, .qword = cmd->state.vb[i].base),
A6XX_VFD_FETCH_SIZE(i, cmd->state.vb[i].size));
A6XX_VFD_VERTEX_BUFFER_BASE(i, .qword = cmd->state.vb[i].base),
A6XX_VFD_VERTEX_BUFFER_SIZE(i, cmd->state.vb[i].size));
}
cmd->state.dirty |= TU_CMD_DIRTY_VERTEX_BUFFERS;
@@ -3596,7 +3596,7 @@ tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
struct tu_cs *cs, state_cs;
if (bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS) {
sp_bindless_base_reg = __SP_BINDLESS_BASE_DESCRIPTOR<CHIP>(0, {}).reg;
sp_bindless_base_reg = __SP_GFX_BINDLESS_BASE_DESCRIPTOR<CHIP>(0, {}).reg;
hlsq_bindless_base_reg = REG_A6XX_HLSQ_BINDLESS_BASE(0);
if (CHIP == A6XX) {
@@ -3640,7 +3640,7 @@ tu6_emit_descriptor_sets(struct tu_cmd_buffer *cmd,
}
}
tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
tu_cs_emit_regs(cs, SP_UPDATE_CNTL(CHIP,
.cs_bindless = bind_point == VK_PIPELINE_BIND_POINT_COMPUTE ? CHIP == A6XX ? 0x1f : 0xff : 0,
.gfx_bindless = bind_point == VK_PIPELINE_BIND_POINT_GRAPHICS ? CHIP == A6XX ? 0x1f : 0xff : 0,
));
@@ -4120,7 +4120,7 @@ tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer,
CP_COND_REG_EXEC_0_SYSMEM |
CP_COND_REG_EXEC_0_BINNING);
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(false));
tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(false));
/* TODO: only update offset for active buffers */
for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++)
@@ -4169,7 +4169,7 @@ tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer,
CP_COND_REG_EXEC_0_SYSMEM |
CP_COND_REG_EXEC_0_BINNING);
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
tu_cs_emit_regs(cs, A6XX_VPC_SO_OVERRIDE(true));
/* TODO: only flush buffers that need to be flushed */
for (uint32_t i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
@@ -5454,10 +5454,10 @@ tu7_emit_subpass_shading_rate(struct tu_cmd_buffer *cmd,
struct tu_cs *cs)
{
if (subpass->fsr_attachment == VK_ATTACHMENT_UNUSED) {
tu_cs_emit_regs(cs, A7XX_GRAS_FSR_BUFFER_DESC(),
A7XX_GRAS_FSR_BUFFER_SIZE());
tu_cs_emit_regs(cs, A7XX_GRAS_FSR_BUFFER_PITCH());
tu_cs_emit_regs(cs, A7XX_GRAS_FSR_BUFFER_BASE());
tu_cs_emit_regs(cs, A7XX_GRAS_QUALITY_BUFFER_INFO(),
A7XX_GRAS_QUALITY_BUFFER_DIMENSION());
tu_cs_emit_regs(cs, A7XX_GRAS_QUALITY_BUFFER_PITCH());
tu_cs_emit_regs(cs, A7XX_GRAS_QUALITY_BUFFER_BASE());
/* We need to invalidate cache when changing to NULL FSR attachment, but
* only once.
*/
@@ -5475,17 +5475,17 @@ tu7_emit_subpass_shading_rate(struct tu_cmd_buffer *cmd,
tu_cs_emit_regs(
cs,
A7XX_GRAS_FSR_BUFFER_DESC(.layered = true,
A7XX_GRAS_QUALITY_BUFFER_INFO(.layered = true,
.tile_mode =
(a6xx_tile_mode) iview->image->layout[0]
.tile_mode, ),
A7XX_GRAS_FSR_BUFFER_SIZE(.width = iview->view.width,
A7XX_GRAS_QUALITY_BUFFER_DIMENSION(.width = iview->view.width,
.height = iview->view.height));
tu_cs_emit_regs(
cs, A7XX_GRAS_FSR_BUFFER_PITCH(.pitch = iview->view.pitch,
cs, A7XX_GRAS_QUALITY_BUFFER_PITCH(.pitch = iview->view.pitch,
.array_pitch = iview->view.layer_size));
tu_cs_emit_regs(cs,
A7XX_GRAS_FSR_BUFFER_BASE(.qword = iview->view.base_addr));
A7XX_GRAS_QUALITY_BUFFER_BASE(.qword = iview->view.base_addr));
tu_emit_raw_event_write<A7XX>(cmd, cs, LRZ_Q_CACHE_INVALIDATE, false);
cmd->prev_fsr_is_null = false;
@@ -6105,7 +6105,7 @@ tu7_emit_shared_preamble_consts(
const struct tu_push_constant_range *shared_consts,
uint32_t *push_constants)
{
tu_cs_emit_pkt4(cs, REG_A7XX_HLSQ_SHARED_CONSTS_IMM(shared_consts->lo_dwords),
tu_cs_emit_pkt4(cs, REG_A7XX_SP_SHARED_CONSTANT_GFX_0(shared_consts->lo_dwords),
shared_consts->dwords);
tu_cs_emit_array(cs, push_constants + shared_consts->lo_dwords,
shared_consts->dwords);
@@ -6652,11 +6652,11 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
VK_PROVOKING_VERTEX_MODE_LAST_VERTEX_EXT;
uint32_t primitive_cntl_0 =
A6XX_PC_PRIMITIVE_CNTL_0(.primitive_restart = primitive_restart,
A6XX_PC_CNTL(.primitive_restart = primitive_restart,
.provoking_vtx_last = provoking_vtx_last).value;
tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(.dword = primitive_cntl_0));
tu_cs_emit_regs(cs, A6XX_PC_CNTL(.dword = primitive_cntl_0));
if (CHIP == A7XX) {
tu_cs_emit_regs(cs, A7XX_VPC_PRIMITIVE_CNTL_0(.dword = primitive_cntl_0));
tu_cs_emit_regs(cs, A7XX_VPC_PC_CNTL(.dword = primitive_cntl_0));
}
}
@@ -6668,7 +6668,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
bool tess_upper_left_domain_origin =
(VkTessellationDomainOrigin)cmd->vk.dynamic_graphics_state.ts.domain_origin ==
VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT;
tu_cs_emit_regs(cs, A6XX_PC_TESS_CNTL(
tu_cs_emit_regs(cs, A6XX_PC_DS_PARAM(
.spacing = tess_params->spacing,
.output = tess_upper_left_domain_origin ?
tess_params->output_upper_left :
@@ -6934,7 +6934,7 @@ tu6_emit_empty_vs_params(struct tu_cmd_buffer *cmd)
* indirect draws, causing problems like incorrect vertex index computation.
* VS state invalidation avoids that.
*/
tu_cs_emit_regs(&cs, HLSQ_INVALIDATE_CMD(CHIP,
tu_cs_emit_regs(&cs, SP_UPDATE_CNTL(CHIP,
.vs_state = true));
assert(cs.cur == cs.end);
} else {
@@ -6954,7 +6954,7 @@ tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
uint32_t offset = vs_params_offset(cmd);
/* Beside re-emitting params when they are changed, we should re-emit
* them after constants are invalidated via HLSQ_INVALIDATE_CMD or after we
* them after constants are invalidated via SP_UPDATE_CNTL or after we
* emit an empty vs params.
*/
if (!(cmd->state.dirty & (TU_CMD_DIRTY_DRAW_STATE | TU_CMD_DIRTY_VS_PARAMS |
@@ -7609,10 +7609,10 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
* affects all known gens. Based on various experiments it appears that the
* issue is that when prefetching a branch destination and there is a cache
* miss, when fetching from memory the HW bounds-checks the fetch against
* SP_CS_INSTRLEN, except when one of the two register contexts is active
* it accidentally fetches SP_FS_INSTRLEN from the other (inactive)
* SP_CS_INSTR_SIZE, except when one of the two register contexts is active
* it accidentally fetches SP_PS_INSTR_SIZE from the other (inactive)
* context. To workaround it we set the FS instrlen here and do a dummy
* event to roll the context (because it fetches SP_FS_INSTRLEN from the
* event to roll the context (because it fetches SP_PS_INSTR_SIZE from the
* "wrong" context). Because the bug seems to involve cache misses, we
* don't emit this if the entire CS program fits in cache, which will
* hopefully be the majority of cases.
@@ -7620,7 +7620,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
* See https://gitlab.freedesktop.org/mesa/mesa/-/issues/5892
*/
if (emit_instrlen_workaround) {
tu_cs_emit_regs(cs, A6XX_SP_FS_INSTRLEN(shader->variant->instrlen));
tu_cs_emit_regs(cs, A6XX_SP_PS_INSTR_SIZE(shader->variant->instrlen));
tu_emit_event_write<CHIP>(cmd, cs, FD_LABEL);
}
@@ -7654,7 +7654,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
/* This path is tailored for BVH building and currently only supports
* 1-dimensional dispatches with a power-of-two local size. We use
* CP_RUN_OPENCL instead of CP_EXEC_CS in order to dynamically set
* HLSQ_CS_KERNEL_GROUP_X, which is usually set implicitly by the
* SP_CS_KERNEL_GROUP_X, which is usually set implicitly by the
* packet, to the number of workgroups. The registers for Y and Z
* dimensions should be unused because we set the kernel dimension to
* 1.
@@ -7663,10 +7663,10 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
assert(util_is_power_of_two_nonzero(local_size[0]));
tu_cs_emit_regs(cs,
HLSQ_CS_NDRANGE_0(CHIP, .kerneldim = 1,
SP_CS_NDRANGE_0(CHIP, .kerneldim = 1,
.localsizex = local_size[0] - 1));
tu_cs_emit_regs(cs, HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0));
tu_cs_emit_regs(cs, SP_CS_NDRANGE_2(CHIP, .globaloff_x = 0));
/* This does:
* - waits for pending cache flushes to finish
@@ -7676,7 +7676,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
* previous dispatches to finish.
*/
tu_cs_emit_pkt7(cs, CP_MEM_TO_REG, 3);
tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A7XX_HLSQ_CS_NDRANGE_1));
tu_cs_emit(cs, CP_MEM_TO_REG_0_REG(REG_A7XX_SP_CS_NDRANGE_1));
tu_cs_emit_qw(cs, info->indirect);
tu_cs_emit_pkt7(cs, CP_SCRATCH_WRITE, 2);
@@ -7701,7 +7701,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
CP_REG_RMW_0_SKIP_WAIT_FOR_ME |
CP_REG_RMW_0_SRC0_IS_REG |
CP_REG_RMW_0_SRC1_ADD);
tu_cs_emit(cs, REG_A7XX_HLSQ_CS_NDRANGE_1); /* SRC0 */
tu_cs_emit(cs, REG_A7XX_SP_CS_NDRANGE_1); /* SRC0 */
tu_cs_emit(cs, -1); /* SRC1 */
/* scratch0 = ((scratch0 & (local_size - 1)) rot 2
@@ -7712,14 +7712,14 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
CP_REG_RMW_0_DST_REG(0) |
CP_REG_RMW_0_DST_SCRATCH |
CP_REG_RMW_0_SKIP_WAIT_FOR_ME |
CP_REG_RMW_0_ROTATE(A7XX_HLSQ_CS_LAST_LOCAL_SIZE_LOCALSIZEX__SHIFT));
CP_REG_RMW_0_ROTATE(A7XX_SP_CS_NDRANGE_7_LOCALSIZEX__SHIFT));
tu_cs_emit(cs, local_size[0] - 1); /* SRC0 */
tu_cs_emit(cs, 0); /* SRC1 */
/* write scratch0 to HLSQ_CS_LAST_LOCAL_SIZE */
/* write scratch0 to SP_CS_NDRANGE_7 */
tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
tu_cs_emit(cs,
CP_SCRATCH_TO_REG_0_REG(REG_A7XX_HLSQ_CS_LAST_LOCAL_SIZE) |
CP_SCRATCH_TO_REG_0_REG(REG_A7XX_SP_CS_NDRANGE_7) |
CP_SCRATCH_TO_REG_0_SCRATCH(0));
tu_cs_emit_pkt7(cs, CP_SCRATCH_WRITE, 2);
@@ -7737,7 +7737,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
CP_REG_RMW_0_SKIP_WAIT_FOR_ME |
CP_REG_RMW_0_SRC0_IS_REG |
CP_REG_RMW_0_SRC1_ADD);
tu_cs_emit(cs, REG_A7XX_HLSQ_CS_NDRANGE_1); /* SRC0 */
tu_cs_emit(cs, REG_A7XX_SP_CS_NDRANGE_1); /* SRC0 */
tu_cs_emit(cs, local_size[0] - 1); /* SRC1 */
unsigned local_size_log2 = util_logbase2(local_size[0]);
@@ -7756,46 +7756,46 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
tu_cs_emit(cs, ~(local_size[0] - 1)); /* SRC0 */
tu_cs_emit(cs, 0); /* SRC1 */
/* write scratch0 to HLSQ_CS_KERNEL_GROUP_X */
/* write scratch0 to SP_CS_KERNEL_GROUP_X */
tu_cs_emit_pkt7(cs, CP_SCRATCH_TO_REG, 1);
tu_cs_emit(cs,
CP_SCRATCH_TO_REG_0_REG(REG_A7XX_HLSQ_CS_KERNEL_GROUP_X) |
CP_SCRATCH_TO_REG_0_REG(REG_A7XX_SP_CS_KERNEL_GROUP_X) |
CP_SCRATCH_TO_REG_0_SCRATCH(0));
} else {
tu_cs_emit_regs(cs,
HLSQ_CS_NDRANGE_0(CHIP, .kerneldim = 3,
SP_CS_NDRANGE_0(CHIP, .kerneldim = 3,
.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1),
HLSQ_CS_NDRANGE_1(CHIP, .globalsize_x = num_groups[0]),
HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
HLSQ_CS_NDRANGE_3(CHIP, .globalsize_y = num_groups[1]),
HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
HLSQ_CS_NDRANGE_5(CHIP, .globalsize_z = num_groups[2]),
HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0));
SP_CS_NDRANGE_1(CHIP, .globalsize_x = num_groups[0]),
SP_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
SP_CS_NDRANGE_3(CHIP, .globalsize_y = num_groups[1]),
SP_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
SP_CS_NDRANGE_5(CHIP, .globalsize_z = num_groups[2]),
SP_CS_NDRANGE_6(CHIP, .globaloff_z = 0));
uint32_t last_local_size[3];
for (unsigned i = 0; i < 3; i++)
last_local_size[i] = ((num_groups[i] - 1) % local_size[i]) + 1;
tu_cs_emit_regs(cs,
A7XX_HLSQ_CS_LAST_LOCAL_SIZE(.localsizex = last_local_size[0] - 1,
A7XX_SP_CS_NDRANGE_7(.localsizex = last_local_size[0] - 1,
.localsizey = last_local_size[1] - 1,
.localsizez = last_local_size[2] - 1));
}
} else {
tu_cs_emit_regs(cs,
HLSQ_CS_NDRANGE_0(CHIP, .kerneldim = 3,
SP_CS_NDRANGE_0(CHIP, .kerneldim = 3,
.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1),
HLSQ_CS_NDRANGE_1(CHIP, .globalsize_x = local_size[0] * num_groups[0]),
HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
HLSQ_CS_NDRANGE_3(CHIP, .globalsize_y = local_size[1] * num_groups[1]),
HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
HLSQ_CS_NDRANGE_5(CHIP, .globalsize_z = local_size[2] * num_groups[2]),
HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0));
SP_CS_NDRANGE_1(CHIP, .globalsize_x = local_size[0] * num_groups[0]),
SP_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
SP_CS_NDRANGE_3(CHIP, .globalsize_y = local_size[1] * num_groups[1]),
SP_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
SP_CS_NDRANGE_5(CHIP, .globalsize_z = local_size[2] * num_groups[2]),
SP_CS_NDRANGE_6(CHIP, .globaloff_z = 0));
if (CHIP >= A7XX) {
tu_cs_emit_regs(cs,
A7XX_HLSQ_CS_LAST_LOCAL_SIZE(.localsizex = local_size[0] - 1,
A7XX_SP_CS_NDRANGE_7(.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1));
}
@@ -7856,7 +7856,7 @@ tu_dispatch(struct tu_cmd_buffer *cmd,
}
/* For the workaround above, because it's using the "wrong" context for
* SP_FS_INSTRLEN we should emit another dummy event write to avoid a
* SP_PS_INSTR_SIZE we should emit another dummy event write to avoid a
* potential race between writing the register and the CP_EXEC_CS we just
* did. We don't need to reset the register because it will be re-emitted
* anyway when the next renderpass starts.
src/freedreno/vulkan/tu_device.cc
+22 -22
View File
@@ -2420,58 +2420,58 @@ tu_init_cmdbuf_start_a725_quirk(struct tu_device *device)
struct tu_cs sub_cs;
tu_cs_begin_sub_stream(&device->sub_cs, 47, &sub_cs);
tu_cs_emit_regs(&sub_cs, HLSQ_INVALIDATE_CMD(A7XX,
tu_cs_emit_regs(&sub_cs, SP_UPDATE_CNTL(A7XX,
.vs_state = true, .hs_state = true, .ds_state = true,
.gs_state = true, .fs_state = true, .gfx_uav = true,
.cs_bindless = 0xff, .gfx_bindless = 0xff));
tu_cs_emit_regs(&sub_cs, HLSQ_CS_CNTL(A7XX,
tu_cs_emit_regs(&sub_cs, SP_CS_CONST_CONFIG(A7XX,
.constlen = 4,
.enabled = true));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_CONFIG(.enabled = true));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_CTRL_REG0(
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_CNTL_0(
.threadmode = MULTI,
.threadsize = THREAD128,
.mergedregs = true));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_CTRL_REG1(.shared_size = 1));
tu_cs_emit_regs(&sub_cs, HLSQ_CS_KERNEL_GROUP_X(A7XX, 1),
HLSQ_CS_KERNEL_GROUP_Y(A7XX, 1),
HLSQ_CS_KERNEL_GROUP_Z(A7XX, 1));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_INSTRLEN(.sp_cs_instrlen = 1));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_TEX_COUNT(0));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_UAV_COUNT(0));
tu_cs_emit_regs(&sub_cs, HLSQ_CS_CNTL_1(A7XX,
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_CNTL_1(.shared_size = 1));
tu_cs_emit_regs(&sub_cs, SP_CS_KERNEL_GROUP_X(A7XX, 1),
SP_CS_KERNEL_GROUP_Y(A7XX, 1),
SP_CS_KERNEL_GROUP_Z(A7XX, 1));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_INSTR_SIZE(.sp_cs_instr_size = 1));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_TSIZE(0));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_USIZE(0));
tu_cs_emit_regs(&sub_cs, SP_CS_WGE_CNTL(A7XX,
.linearlocalidregid = regid(63, 0),
.threadsize = THREAD128,
.workgrouprastorderzfirsten = true,
.wgtilewidth = 4,
.wgtileheight = 17));
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_CNTL_0(
tu_cs_emit_regs(&sub_cs, A6XX_SP_CS_WIE_CNTL_0(
.wgidconstid = regid(51, 3),
.wgsizeconstid = regid(48, 0),
.wgoffsetconstid = regid(63, 0),
.localidregid = regid(63, 0)));
tu_cs_emit_regs(&sub_cs, SP_CS_CNTL_1(A7XX,
tu_cs_emit_regs(&sub_cs, SP_CS_WIE_CNTL_1(A7XX,
.linearlocalidregid = regid(63, 0),
.threadsize = THREAD128,
.workitemrastorder = WORKITEMRASTORDER_TILED));
tu_cs_emit_regs(&sub_cs, A7XX_SP_CS_UNKNOWN_A9BE(0));
tu_cs_emit_regs(&sub_cs,
HLSQ_CS_NDRANGE_0(A7XX, .kerneldim = 3,
SP_CS_NDRANGE_0(A7XX, .kerneldim = 3,
.localsizex = 255,
.localsizey = 1,
.localsizez = 1),
HLSQ_CS_NDRANGE_1(A7XX, .globalsize_x = 3072),
HLSQ_CS_NDRANGE_2(A7XX, .globaloff_x = 0),
HLSQ_CS_NDRANGE_3(A7XX, .globalsize_y = 1),
HLSQ_CS_NDRANGE_4(A7XX, .globaloff_y = 0),
HLSQ_CS_NDRANGE_5(A7XX, .globalsize_z = 1),
HLSQ_CS_NDRANGE_6(A7XX, .globaloff_z = 0));
tu_cs_emit_regs(&sub_cs, A7XX_HLSQ_CS_LAST_LOCAL_SIZE(
SP_CS_NDRANGE_1(A7XX, .globalsize_x = 3072),
SP_CS_NDRANGE_2(A7XX, .globaloff_x = 0),
SP_CS_NDRANGE_3(A7XX, .globalsize_y = 1),
SP_CS_NDRANGE_4(A7XX, .globaloff_y = 0),
SP_CS_NDRANGE_5(A7XX, .globalsize_z = 1),
SP_CS_NDRANGE_6(A7XX, .globaloff_z = 0));
tu_cs_emit_regs(&sub_cs, A7XX_SP_CS_NDRANGE_7(
.localsizex = 255,
.localsizey = 0,
.localsizez = 0));
tu_cs_emit_pkt4(&sub_cs, REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET, 3);
tu_cs_emit_pkt4(&sub_cs, REG_A6XX_SP_CS_PROGRAM_COUNTER_OFFSET, 3);
tu_cs_emit(&sub_cs, 0);
tu_cs_emit_qw(&sub_cs, shader_iova);
src/freedreno/vulkan/tu_image.cc
+3 -3
View File
@@ -169,11 +169,11 @@ void
tu_cs_image_ref_2d(struct tu_cs *cs, const struct fdl6_view *iview, uint32_t layer, bool src)
{
tu_cs_emit_qw(cs, iview->base_addr + iview->layer_size * layer);
/* SP_PS_2D_SRC_PITCH has shifted pitch field */
/* TPL1_A2D_SRC_TEXTURE_PITCH has shifted pitch field */
if (src)
tu_cs_emit(cs, SP_PS_2D_SRC_PITCH(CHIP, .pitch = iview->pitch).value);
tu_cs_emit(cs, TPL1_A2D_SRC_TEXTURE_PITCH(CHIP, .pitch = iview->pitch).value);
else
tu_cs_emit(cs, A6XX_RB_2D_DST_PITCH(iview->pitch).value);
tu_cs_emit(cs, A6XX_RB_A2D_DEST_BUFFER_PITCH(iview->pitch).value);
}
TU_GENX(tu_cs_image_ref_2d);
src/freedreno/vulkan/tu_lrz.cc
+14 -14
View File
@@ -177,7 +177,7 @@ static void
tu6_disable_lrz_via_depth_view(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
/* Disable direction by writing invalid depth view. */
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_DEPTH_VIEW(
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_VIEW_INFO(
.base_layer = 0b11111111111,
.layer_count = 0b11111111111,
.base_mip_level = 0b1111,
@@ -400,7 +400,7 @@ tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
assert(lrz->gpu_dir_tracking);
tu6_write_lrz_reg(cmd, cs,
A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = lrz->image_view->view.GRAS_LRZ_DEPTH_VIEW));
A6XX_GRAS_LRZ_VIEW_INFO(.dword = lrz->image_view->view.GRAS_LRZ_VIEW_INFO));
return;
}
@@ -411,7 +411,7 @@ tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
*/
if (lrz->gpu_dir_tracking) {
tu6_disable_lrz_via_depth_view<CHIP>(cmd, cs);
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = 0));
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_VIEW_INFO(.dword = 0));
}
return;
}
@@ -419,7 +419,7 @@ tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
if (lrz->fast_clear || lrz->gpu_dir_tracking) {
if (lrz->gpu_dir_tracking) {
tu6_write_lrz_reg(cmd, cs,
A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = lrz->image_view->view.GRAS_LRZ_DEPTH_VIEW));
A6XX_GRAS_LRZ_VIEW_INFO(.dword = lrz->image_view->view.GRAS_LRZ_VIEW_INFO));
}
tu6_write_lrz_cntl<CHIP>(cmd, cs, {
@@ -433,7 +433,7 @@ tu_lrz_tiling_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
* CUR_DIR_UNSET.
*/
if (CHIP >= A7XX)
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(lrz->depth_clear_value.depthStencil.depth));
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_CLEAR(lrz->depth_clear_value.depthStencil.depth));
tu_emit_event_write<CHIP>(cmd, cs, FD_LRZ_CLEAR);
}
@@ -469,10 +469,10 @@ tu_lrz_before_tile(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
if (lrz->gpu_dir_tracking) {
if (!lrz->valid_at_start) {
/* Make sure we fail the comparison of depth views */
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = 0));
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_VIEW_INFO(.dword = 0));
} else {
tu6_write_lrz_reg(cmd, cs,
A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = lrz->image_view->view.GRAS_LRZ_DEPTH_VIEW));
A6XX_GRAS_LRZ_VIEW_INFO(.dword = lrz->image_view->view.GRAS_LRZ_VIEW_INFO));
}
}
}
@@ -488,7 +488,7 @@ tu_lrz_tiling_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
if (cmd->state.lrz.gpu_dir_tracking) {
tu6_write_lrz_reg(cmd, &cmd->cs,
A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = cmd->state.lrz.image_view->view.GRAS_LRZ_DEPTH_VIEW));
A6XX_GRAS_LRZ_VIEW_INFO(.dword = cmd->state.lrz.image_view->view.GRAS_LRZ_VIEW_INFO));
}
/* Enable flushing of LRZ fast-clear and of direction buffer */
@@ -516,7 +516,7 @@ tu_lrz_tiling_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
}
if (cmd->state.lrz.gpu_dir_tracking && disable_for_next_rp) {
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_DEPTH_VIEW(
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_VIEW_INFO(
.base_layer = 0b11111111111,
.layer_count = 0b11111111111,
.base_mip_level = 0b1111,
@@ -552,7 +552,7 @@ tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_disable_lrz<CHIP>(cmd, cs, lrz->image_view->image);
/* Make sure depth view comparison will fail. */
tu6_write_lrz_reg(cmd, cs,
A6XX_GRAS_LRZ_DEPTH_VIEW(.dword = 0));
A6XX_GRAS_LRZ_VIEW_INFO(.dword = 0));
} else {
tu6_emit_lrz_buffer<CHIP>(cs, lrz->image_view->image);
/* Even though we disable LRZ writes in sysmem mode - there is still
@@ -565,7 +565,7 @@ tu_lrz_sysmem_begin(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
});
if (CHIP >= A7XX)
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(lrz->depth_clear_value.depthStencil.depth));
tu_cs_emit_regs(cs, A7XX_GRAS_LRZ_DEPTH_CLEAR(lrz->depth_clear_value.depthStencil.depth));
tu_emit_event_write<CHIP>(cmd, &cmd->cs, FD_LRZ_CLEAR);
tu_emit_event_write<CHIP>(cmd, &cmd->cs, FD_LRZ_FLUSH);
} else {
@@ -665,7 +665,7 @@ tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
tu6_emit_lrz_buffer<CHIP>(&cmd->cs, image);
tu6_write_lrz_reg(cmd, &cmd->cs, A6XX_GRAS_LRZ_DEPTH_VIEW(
tu6_write_lrz_reg(cmd, &cmd->cs, A6XX_GRAS_LRZ_VIEW_INFO(
.base_layer = range->baseArrayLayer,
.layer_count = vk_image_subresource_layer_count(&image->vk, range),
.base_mip_level = range->baseMipLevel,
@@ -678,7 +678,7 @@ tu_lrz_clear_depth_image(struct tu_cmd_buffer *cmd,
});
if (CHIP >= A7XX)
tu_cs_emit_regs(&cmd->cs, A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(pDepthStencil->depth));
tu_cs_emit_regs(&cmd->cs, A7XX_GRAS_LRZ_DEPTH_CLEAR(pDepthStencil->depth));
tu_emit_event_write<CHIP>(cmd, &cmd->cs, FD_LRZ_CLEAR);
tu_emit_event_write<CHIP>(cmd, &cmd->cs, FD_LRZ_FLUSH);
@@ -713,7 +713,7 @@ tu_lrz_flush_valid_during_renderpass(struct tu_cmd_buffer *cmd,
if (cmd->state.lrz.valid && !cmd->state.lrz.disable_write_for_rp)
return;
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_DEPTH_VIEW(
tu6_write_lrz_reg(cmd, cs, A6XX_GRAS_LRZ_VIEW_INFO(
.base_layer = 0b11111111111,
.layer_count = 0b11111111111,
.base_mip_level = 0b1111,
src/freedreno/vulkan/tu_pipeline.cc
+144 -144
View File
@@ -346,27 +346,27 @@ template <chip CHIP>
static const xs_config<CHIP> xs_configs[] = {
[MESA_SHADER_VERTEX] = {
REG_A6XX_SP_VS_CONFIG,
CHIP == A6XX ? REG_A6XX_HLSQ_VS_CNTL : REG_A7XX_HLSQ_VS_CNTL,
CHIP == A6XX ? REG_A6XX_SP_VS_CONST_CONFIG : REG_A7XX_SP_VS_CONST_CONFIG,
},
[MESA_SHADER_TESS_CTRL] = {
REG_A6XX_SP_HS_CONFIG,
CHIP == A6XX ? REG_A6XX_HLSQ_HS_CNTL : REG_A7XX_HLSQ_HS_CNTL,
CHIP == A6XX ? REG_A6XX_SP_HS_CONST_CONFIG : REG_A7XX_SP_HS_CONST_CONFIG,
},
[MESA_SHADER_TESS_EVAL] = {
REG_A6XX_SP_DS_CONFIG,
CHIP == A6XX ? REG_A6XX_HLSQ_DS_CNTL : REG_A7XX_HLSQ_DS_CNTL,
CHIP == A6XX ? REG_A6XX_SP_DS_CONST_CONFIG : REG_A7XX_SP_DS_CONST_CONFIG,
},
[MESA_SHADER_GEOMETRY] = {
REG_A6XX_SP_GS_CONFIG,
CHIP == A6XX ? REG_A6XX_HLSQ_GS_CNTL : REG_A7XX_HLSQ_GS_CNTL,
CHIP == A6XX ? REG_A6XX_SP_GS_CONST_CONFIG : REG_A7XX_SP_GS_CONST_CONFIG,
},
[MESA_SHADER_FRAGMENT] = {
REG_A6XX_SP_FS_CONFIG,
CHIP == A6XX ? REG_A6XX_HLSQ_FS_CNTL : REG_A7XX_HLSQ_FS_CNTL,
REG_A6XX_SP_PS_CONFIG,
CHIP == A6XX ? REG_A6XX_SP_PS_CONST_CONFIG : REG_A7XX_SP_PS_CONST_CONFIG,
},
[MESA_SHADER_COMPUTE] = {
REG_A6XX_SP_CS_CONFIG,
CHIP == A6XX ? REG_A6XX_HLSQ_CS_CNTL : REG_A7XX_HLSQ_CS_CNTL,
CHIP == A6XX ? REG_A6XX_SP_CS_CONST_CONFIG : REG_A7XX_SP_CS_CONST_CONFIG,
},
};
@@ -398,10 +398,10 @@ tu6_emit_xs_config(struct tu_cs *cs,
A6XX_SP_VS_CONFIG_NSAMP(xs->num_samp));
tu_cs_emit_pkt4(cs, cfg->reg_hlsq_xs_ctrl, 1);
tu_cs_emit(cs, A6XX_HLSQ_VS_CNTL_CONSTLEN(xs->constlen) |
A6XX_HLSQ_VS_CNTL_ENABLED |
tu_cs_emit(cs, A6XX_SP_VS_CONST_CONFIG_CONSTLEN(xs->constlen) |
A6XX_SP_VS_CONST_CONFIG_ENABLED |
COND(xs->shader_options.push_consts_type == IR3_PUSH_CONSTS_SHARED_PREAMBLE,
A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS));
A7XX_SP_VS_CONST_CONFIG_READ_IMM_SHARED_CONSTS));
}
TU_GENX(tu6_emit_xs_config);
@@ -473,7 +473,7 @@ tu6_emit_shared_consts_enable(struct tu_cs *cs, bool enable)
assert(!enable);
}
tu_cs_emit_regs(cs, A6XX_SP_MODE_CONTROL(.constant_demotion_enable = true,
tu_cs_emit_regs(cs, A6XX_SP_MODE_CNTL(.constant_demotion_enable = true,
.isammode = ISAMMODE_GL,
.shared_consts_enable = enable));
}
@@ -502,13 +502,13 @@ tu6_setup_streamout(struct tu_cs *cs,
sizedw += 2;
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, sizedw);
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
tu_cs_emit(cs, REG_A6XX_VPC_SO_MAPPING_WPTR);
tu_cs_emit(cs, 0);
tu_cs_emit(cs, REG_A6XX_VPC_SO_STREAM_CNTL);
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
tu_cs_emit(cs, 0);
if (cs->device->physical_device->info->a6xx.tess_use_shared) {
tu_cs_emit(cs, REG_A6XX_PC_SO_STREAM_CNTL);
tu_cs_emit(cs, REG_A6XX_PC_DGEN_SO_CNTL);
tu_cs_emit(cs, 0);
}
@@ -541,13 +541,13 @@ tu6_setup_streamout(struct tu_cs *cs,
assert(loc < A6XX_SO_PROG_DWORDS * 2);
unsigned dword = out->stream * A6XX_SO_PROG_DWORDS + loc/2;
if (loc & 1) {
prog[dword] |= A6XX_VPC_SO_PROG_B_EN |
A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_B_OFF(off * 4);
prog[dword] |= A6XX_VPC_SO_MAPPING_PORT_B_EN |
A6XX_VPC_SO_MAPPING_PORT_B_BUF(out->output_buffer) |
A6XX_VPC_SO_MAPPING_PORT_B_OFF(off * 4);
} else {
prog[dword] |= A6XX_VPC_SO_PROG_A_EN |
A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_A_OFF(off * 4);
prog[dword] |= A6XX_VPC_SO_MAPPING_PORT_A_EN |
A6XX_VPC_SO_MAPPING_PORT_A_BUF(out->output_buffer) |
A6XX_VPC_SO_MAPPING_PORT_A_OFF(off * 4);
}
BITSET_SET(valid_dwords, dword);
}
@@ -568,16 +568,16 @@ tu6_setup_streamout(struct tu_cs *cs,
prog_count += 1;
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 10 + 2 * prog_count);
tu_cs_emit(cs, REG_A6XX_VPC_SO_STREAM_CNTL);
tu_cs_emit(cs, A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(info->streams_written) |
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
tu_cs_emit(cs, A6XX_VPC_SO_CNTL_STREAM_ENABLE(info->streams_written) |
COND(info->stride[0] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1 + info->buffer_to_stream[0])) |
A6XX_VPC_SO_CNTL_BUF0_STREAM(1 + info->buffer_to_stream[0])) |
COND(info->stride[1] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1 + info->buffer_to_stream[1])) |
A6XX_VPC_SO_CNTL_BUF1_STREAM(1 + info->buffer_to_stream[1])) |
COND(info->stride[2] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1 + info->buffer_to_stream[2])) |
A6XX_VPC_SO_CNTL_BUF2_STREAM(1 + info->buffer_to_stream[2])) |
COND(info->stride[3] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1 + info->buffer_to_stream[3])));
A6XX_VPC_SO_CNTL_BUF3_STREAM(1 + info->buffer_to_stream[3])));
for (uint32_t i = 0; i < 4; i++) {
tu_cs_emit(cs, REG_A6XX_VPC_SO_BUFFER_STRIDE(i));
tu_cs_emit(cs, info->stride[i]);
@@ -585,11 +585,11 @@ tu6_setup_streamout(struct tu_cs *cs,
bool first = true;
BITSET_FOREACH_RANGE(start, end, valid_dwords,
A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) {
tu_cs_emit(cs, REG_A6XX_VPC_SO_CNTL);
tu_cs_emit(cs, COND(first, A6XX_VPC_SO_CNTL_RESET) |
A6XX_VPC_SO_CNTL_ADDR(start));
tu_cs_emit(cs, REG_A6XX_VPC_SO_MAPPING_WPTR);
tu_cs_emit(cs, COND(first, A6XX_VPC_SO_MAPPING_WPTR_RESET) |
A6XX_VPC_SO_MAPPING_WPTR_ADDR(start));
for (unsigned i = start; i < end; i++) {
tu_cs_emit(cs, REG_A6XX_VPC_SO_PROG);
tu_cs_emit(cs, REG_A6XX_VPC_SO_MAPPING_PORT);
tu_cs_emit(cs, prog[i]);
}
first = false;
@@ -599,8 +599,8 @@ tu6_setup_streamout(struct tu_cs *cs,
/* Possibly not tess_use_shared related, but the combination of
* tess + xfb fails some tests if we don't emit this.
*/
tu_cs_emit(cs, REG_A6XX_PC_SO_STREAM_CNTL);
tu_cs_emit(cs, A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(info->streams_written));
tu_cs_emit(cs, REG_A6XX_PC_DGEN_SO_CNTL);
tu_cs_emit(cs, A6XX_PC_DGEN_SO_CNTL_STREAM_ENABLE(info->streams_written));
}
}
@@ -786,10 +786,10 @@ tu6_emit_vpc_varying_modes(struct tu_cs *cs,
}
if (interp_regs) {
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE(0), interp_regs);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_INTERP_MODE_MODE(0), interp_regs);
tu_cs_emit_array(cs, interp_modes, interp_regs);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), interp_regs);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_REPLACE_MODE_0_MODE(0), interp_regs);
tu_cs_emit_array(cs, ps_repl_modes, interp_regs);
}
}
@@ -818,17 +818,17 @@ tu6_emit_vpc(struct tu_cs *cs,
uint16_t reg_gras_xs_layer_cntl;
} reg_config[] = {
[MESA_SHADER_VERTEX] = {
REG_A6XX_SP_VS_OUT_REG(0),
REG_A6XX_SP_VS_VPC_DST_REG(0),
REG_A6XX_VPC_VS_PACK,
REG_A6XX_VPC_VS_CLIP_CNTL,
REG_A6XX_VPC_VS_CLIP_CNTL_V2,
REG_A6XX_GRAS_VS_CL_CNTL,
REG_A6XX_PC_VS_OUT_CNTL,
REG_A6XX_SP_VS_PRIMITIVE_CNTL,
REG_A6XX_VPC_VS_LAYER_CNTL,
REG_A6XX_VPC_VS_LAYER_CNTL_V2,
REG_A6XX_GRAS_VS_LAYER_CNTL
REG_A6XX_SP_VS_OUTPUT_REG(0),
REG_A6XX_SP_VS_VPC_DEST_REG(0),
REG_A6XX_VPC_VS_CNTL,
REG_A6XX_VPC_VS_CLIP_CULL_CNTL,
REG_A6XX_VPC_VS_CLIP_CULL_CNTL_V2,
REG_A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE,
REG_A6XX_PC_VS_CNTL,
REG_A6XX_SP_VS_OUTPUT_CNTL,
REG_A6XX_VPC_VS_SIV_CNTL,
REG_A6XX_VPC_VS_SIV_CNTL_V2,
REG_A6XX_GRAS_SU_VS_SIV_CNTL,
},
[MESA_SHADER_TESS_CTRL] = {
0,
@@ -837,36 +837,36 @@ tu6_emit_vpc(struct tu_cs *cs,
0,
0,
0,
REG_A6XX_PC_HS_OUT_CNTL,
REG_A6XX_PC_HS_CNTL,
0,
0,
0
},
[MESA_SHADER_TESS_EVAL] = {
REG_A6XX_SP_DS_OUT_REG(0),
REG_A6XX_SP_DS_VPC_DST_REG(0),
REG_A6XX_VPC_DS_PACK,
REG_A6XX_VPC_DS_CLIP_CNTL,
REG_A6XX_VPC_DS_CLIP_CNTL_V2,
REG_A6XX_GRAS_DS_CL_CNTL,
REG_A6XX_PC_DS_OUT_CNTL,
REG_A6XX_SP_DS_PRIMITIVE_CNTL,
REG_A6XX_VPC_DS_LAYER_CNTL,
REG_A6XX_VPC_DS_LAYER_CNTL_V2,
REG_A6XX_GRAS_DS_LAYER_CNTL
REG_A6XX_SP_DS_OUTPUT_REG(0),
REG_A6XX_SP_DS_VPC_DEST_REG(0),
REG_A6XX_VPC_DS_CNTL,
REG_A6XX_VPC_DS_CLIP_CULL_CNTL,
REG_A6XX_VPC_DS_CLIP_CULL_CNTL_V2,
REG_A6XX_GRAS_CL_DS_CLIP_CULL_DISTANCE,
REG_A6XX_PC_DS_CNTL,
REG_A6XX_SP_DS_OUTPUT_CNTL,
REG_A6XX_VPC_DS_SIV_CNTL,
REG_A6XX_VPC_DS_SIV_CNTL_V2,
REG_A6XX_GRAS_SU_DS_SIV_CNTL,
},
[MESA_SHADER_GEOMETRY] = {
REG_A6XX_SP_GS_OUT_REG(0),
REG_A6XX_SP_GS_VPC_DST_REG(0),
REG_A6XX_VPC_GS_PACK,
REG_A6XX_VPC_GS_CLIP_CNTL,
REG_A6XX_VPC_GS_CLIP_CNTL_V2,
REG_A6XX_GRAS_GS_CL_CNTL,
REG_A6XX_PC_GS_OUT_CNTL,
REG_A6XX_SP_GS_PRIMITIVE_CNTL,
REG_A6XX_VPC_GS_LAYER_CNTL,
REG_A6XX_VPC_GS_LAYER_CNTL_V2,
REG_A6XX_GRAS_GS_LAYER_CNTL
REG_A6XX_SP_GS_OUTPUT_REG(0),
REG_A6XX_SP_GS_VPC_DEST_REG(0),
REG_A6XX_VPC_GS_CNTL,
REG_A6XX_VPC_GS_CLIP_CULL_CNTL,
REG_A6XX_VPC_GS_CLIP_CULL_CNTL_V2,
REG_A6XX_GRAS_CL_GS_CLIP_CULL_DISTANCE,
REG_A6XX_PC_GS_CNTL,
REG_A6XX_SP_GS_OUTPUT_CNTL,
REG_A6XX_VPC_GS_SIV_CNTL,
REG_A6XX_VPC_GS_SIV_CNTL_V2,
REG_A6XX_GRAS_SU_GS_SIV_CNTL,
},
};
@@ -990,10 +990,10 @@ tu6_emit_vpc(struct tu_cs *cs,
uint32_t sp_vpc_dst[8] = {0};
for (uint32_t i = 0; i < linkage.cnt; i++) {
((uint16_t *) sp_out)[i] =
A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
A6XX_SP_VS_OUTPUT_REG_A_REGID(linkage.var[i].regid) |
A6XX_SP_VS_OUTPUT_REG_A_COMPMASK(linkage.var[i].compmask);
((uint8_t *) sp_vpc_dst)[i] =
A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
A6XX_SP_VS_VPC_DEST_REG_OUTLOC0(linkage.var[i].loc);
}
tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_out_reg, sp_out_count);
@@ -1003,23 +1003,23 @@ tu6_emit_vpc(struct tu_cs *cs,
tu_cs_emit_array(cs, sp_vpc_dst, sp_vpc_dst_count);
tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_pack, 1);
tu_cs_emit(cs, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc) |
A6XX_VPC_VS_PACK_EXTRAPOS(extra_pos));
tu_cs_emit(cs, A6XX_VPC_VS_CNTL_POSITIONLOC(position_loc) |
A6XX_VPC_VS_CNTL_PSIZELOC(pointsize_loc) |
A6XX_VPC_VS_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
A6XX_VPC_VS_CNTL_EXTRAPOS(extra_pos));
tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl, 1);
tu_cs_emit(cs, A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
tu_cs_emit(cs, A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC(clip1_loc));
tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_clip_cntl_v2, 1);
tu_cs_emit(cs, A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
tu_cs_emit(cs, A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC(clip1_loc));
tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_cl_cntl, 1);
tu_cs_emit(cs, A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(last_shader->clip_mask) |
A6XX_GRAS_VS_CL_CNTL_CULL_MASK(last_shader->cull_mask));
tu_cs_emit(cs, A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CLIP_MASK(last_shader->clip_mask) |
A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CULL_MASK(last_shader->cull_mask));
const struct ir3_shader_variant *geom_shaders[] = { vs, hs, ds, gs };
@@ -1033,15 +1033,15 @@ tu6_emit_vpc(struct tu_cs *cs,
tu_cs_emit_pkt4(cs, reg_config[shader->type].reg_pc_xs_out_cntl, 1);
if (shader == last_shader) {
tu_cs_emit(cs, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
CONDREG(view_regid, A6XX_PC_VS_OUT_CNTL_VIEW) |
COND(primid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID) |
A6XX_PC_VS_OUT_CNTL_CLIP_MASK(clip_cull_mask) |
CONDREG(shading_rate_regid, A6XX_PC_VS_OUT_CNTL_SHADINGRATE));
tu_cs_emit(cs, A6XX_PC_VS_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
CONDREG(pointsize_regid, A6XX_PC_VS_CNTL_PSIZE) |
CONDREG(layer_regid, A6XX_PC_VS_CNTL_LAYER) |
CONDREG(view_regid, A6XX_PC_VS_CNTL_VIEW) |
COND(primid, A6XX_PC_VS_CNTL_PRIMITIVE_ID) |
A6XX_PC_VS_CNTL_CLIP_MASK(clip_cull_mask) |
CONDREG(shading_rate_regid, A6XX_PC_VS_CNTL_SHADINGRATE));
} else {
tu_cs_emit(cs, COND(primid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
tu_cs_emit(cs, COND(primid, A6XX_PC_VS_CNTL_PRIMITIVE_ID));
}
}
@@ -1050,21 +1050,21 @@ tu6_emit_vpc(struct tu_cs *cs,
assert(flags_regid != INVALID_REG);
tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_primitive_cntl, 1);
tu_cs_emit(cs, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
tu_cs_emit(cs, A6XX_SP_VS_OUTPUT_CNTL_OUT(linkage.cnt) |
A6XX_SP_GS_OUTPUT_CNTL_FLAGS_REGID(flags_regid));
tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl, 1);
tu_cs_emit(cs, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(shading_rate_loc));
tu_cs_emit(cs, A6XX_VPC_VS_SIV_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_SIV_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_SIV_CNTL_SHADINGRATELOC(shading_rate_loc));
tu_cs_emit_pkt4(cs, cfg->reg_vpc_xs_layer_cntl_v2, 1);
tu_cs_emit(cs, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(shading_rate_loc));
tu_cs_emit(cs, A6XX_VPC_VS_SIV_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_SIV_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_SIV_CNTL_SHADINGRATELOC(shading_rate_loc));
tu_cs_emit_pkt4(cs, cfg->reg_gras_xs_layer_cntl, 1);
tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER) |
CONDREG(view_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW));
tu_cs_emit(cs, CONDREG(layer_regid, A6XX_GRAS_SU_VS_SIV_CNTL_WRITES_LAYER) |
CONDREG(view_regid, A6XX_GRAS_SU_VS_SIV_CNTL_WRITES_VIEW));
tu6_emit_vpc_varying_modes(cs, fs, last_shader);
}
@@ -1180,7 +1180,7 @@ tu6_emit_patch_control_points(struct tu_cs *cs,
patch_control_points * vs->variant->output_size / 4;
/* Total attribute slots in HS incoming patch. */
tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_INPUT_SIZE, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_PARAM_1, 1);
tu_cs_emit(cs, patch_local_mem_size_16b);
const uint32_t wavesize = 64;
@@ -1207,7 +1207,7 @@ tu6_emit_patch_control_points(struct tu_cs *cs,
uint32_t wave_input_size = DIV_ROUND_UP(
patches_per_wave * patch_local_mem_size_16b * 16, 256);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_WAVE_INPUT_SIZE, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_CNTL_1, 1);
tu_cs_emit(cs, wave_input_size);
/* maximum number of patches that can fit in tess factor/param buffers */
@@ -1281,7 +1281,7 @@ tu6_emit_program_config(struct tu_cs *cs,
prog->shared_consts.type == IR3_PUSH_CONSTS_SHARED;
tu6_emit_shared_consts_enable<CHIP>(cs, shared_consts_enable);
tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
tu_cs_emit_regs(cs, SP_UPDATE_CNTL(CHIP,
.vs_state = true,
.hs_state = true,
.ds_state = true,
@@ -1334,7 +1334,7 @@ tu6_emit_program_config(struct tu_cs *cs,
prim_size = 64;
else if (prim_size == 64)
prim_size = 63;
tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_PRIM_SIZE, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_GS_CNTL_1, 1);
tu_cs_emit(cs, prim_size);
}
@@ -2340,7 +2340,7 @@ tu6_emit_vertex_input(struct tu_cs *cs,
{
unsigned attr_count = util_last_bit(vi->attributes_valid);
if (attr_count != 0)
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_DECODE_INSTR(0), attr_count * 2);
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_FETCH_INSTR_INSTR(0), attr_count * 2);
for (uint32_t loc = 0; loc < attr_count; loc++) {
const struct vk_vertex_attribute_state *attr = &vi->attributes[loc];
@@ -2351,7 +2351,7 @@ tu6_emit_vertex_input(struct tu_cs *cs,
enum pipe_format pipe_format = vk_format_to_pipe_format(attr->format);
const struct tu_native_format format = tu6_format_vtx(pipe_format);
tu_cs_emit(cs, A6XX_VFD_DECODE_INSTR(0,
tu_cs_emit(cs, A6XX_VFD_FETCH_INSTR_INSTR(0,
.idx = attr->binding,
.offset = attr->offset,
.instanced = binding->input_rate == VK_VERTEX_INPUT_RATE_INSTANCE,
@@ -2359,7 +2359,7 @@ tu6_emit_vertex_input(struct tu_cs *cs,
.swap = format.swap,
.unk30 = 1,
._float = !util_format_is_pure_integer(pipe_format)).value);
tu_cs_emit(cs, A6XX_VFD_DECODE_STEP_RATE(0, binding->divisor).value);
tu_cs_emit(cs, A6XX_VFD_FETCH_INSTR_STEP_RATE(0, binding->divisor).value);
} else {
tu_cs_emit(cs, 0);
tu_cs_emit(cs, 0);
@@ -2388,7 +2388,7 @@ tu6_emit_vertex_stride(struct tu_cs *cs, const struct vk_vertex_input_state *vi)
unsigned bindings_count = util_last_bit(vi->bindings_valid);
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 2 * bindings_count);
for (unsigned i = 0; i < bindings_count; i++) {
tu_cs_emit(cs, REG_A6XX_VFD_FETCH_STRIDE(i));
tu_cs_emit(cs, REG_A6XX_VFD_VERTEX_BUFFER_STRIDE(i));
tu_cs_emit(cs, vi->bindings[i].stride);
}
}
@@ -2412,7 +2412,7 @@ tu6_emit_vertex_stride_dyn(struct tu_cs *cs, const uint16_t *vi_binding_stride,
unsigned bindings_count = util_last_bit(bindings_valid);
tu_cs_emit_pkt7(cs, CP_CONTEXT_REG_BUNCH, 2 * bindings_count);
for (unsigned i = 0; i < bindings_count; i++) {
tu_cs_emit(cs, REG_A6XX_VFD_FETCH_STRIDE(i));
tu_cs_emit(cs, REG_A6XX_VFD_VERTEX_BUFFER_STRIDE(i));
tu_cs_emit(cs, vi_binding_stride[i]);
}
}
@@ -2443,7 +2443,7 @@ tu6_emit_viewport(struct tu_cs *cs,
{
VkExtent2D guardband = {511, 511};
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VPORT_XOFFSET(0), vp->viewport_count * 6);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VIEWPORT_XOFFSET(0), vp->viewport_count * 6);
for (uint32_t i = 0; i < vp->viewport_count; i++) {
const VkViewport *viewport = &vp->viewports[i];
float offsets[3];
@@ -2516,7 +2516,7 @@ tu6_emit_viewport(struct tu_cs *cs,
*/
bool zero_one_depth_clamp = CHIP >= A7XX && !rs->depth_clamp_enable;
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_Z_CLAMP(0), vp->viewport_count * 2);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_VIEWPORT_ZCLAMP(0), vp->viewport_count * 2);
for (uint32_t i = 0; i < vp->viewport_count; i++) {
const VkViewport *viewport = &vp->viewports[i];
if (zero_one_depth_clamp) {
@@ -2540,8 +2540,8 @@ tu6_emit_viewport(struct tu_cs *cs,
}
tu_cs_emit_regs(cs,
A6XX_RB_Z_CLAMP_MIN(z_clamp_min),
A6XX_RB_Z_CLAMP_MAX(z_clamp_max));
A6XX_RB_VIEWPORT_ZCLAMP_MIN(z_clamp_min),
A6XX_RB_VIEWPORT_ZCLAMP_MAX(z_clamp_max));
}
struct apply_viewport_state {
@@ -2788,15 +2788,15 @@ tu6_emit_sample_locations(struct tu_cs *cs, bool enable,
const struct vk_sample_locations_state *samp_loc)
{
uint32_t sample_config =
COND(enable, A6XX_RB_SAMPLE_CONFIG_LOCATION_ENABLE);
COND(enable, A6XX_RB_MSAA_SAMPLE_POS_CNTL_LOCATION_ENABLE);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CONFIG, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL, 1);
tu_cs_emit(cs, sample_config);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CONFIG, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_MSAA_SAMPLE_POS_CNTL, 1);
tu_cs_emit(cs, sample_config);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_CONFIG, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_TPL1_MSAA_SAMPLE_POS_CNTL, 1);
tu_cs_emit(cs, sample_config);
if (!enable)
@@ -2820,17 +2820,17 @@ tu6_emit_sample_locations(struct tu_cs *cs, bool enable,
SAMPLE_LOCATION_MAX);
sample_locations |=
((uint64_t)(A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(x) |
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(y))) << i*8;
((uint64_t)(A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X(x) |
A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y(y))) << i*8;
}
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_LOCATION_0, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0, 2);
tu_cs_emit_qw(cs, sample_locations);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_LOCATION_0, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_PROGRAMMABLE_MSAA_POS_0, 2);
tu_cs_emit_qw(cs, sample_locations);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_TP_SAMPLE_LOCATION_0, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0, 2);
tu_cs_emit_qw(cs, sample_locations);
}
@@ -3094,8 +3094,8 @@ tu6_emit_blend(struct tu_cs *cs,
bool dual_src_blend = tu_blend_state_is_dual_src(cb);
tu_cs_emit_regs(cs, A6XX_SP_FS_OUTPUT_CNTL1(.mrt = num_rts));
tu_cs_emit_regs(cs, A6XX_RB_FS_OUTPUT_CNTL1(.mrt = num_rts));
tu_cs_emit_regs(cs, A6XX_SP_PS_MRT_CNTL(.mrt = num_rts));
tu_cs_emit_regs(cs, A6XX_RB_PS_MRT_CNTL(.mrt = num_rts));
tu_cs_emit_regs(cs, A6XX_SP_BLEND_CNTL(.enable_blend = blend_enable_mask,
.unk8 = true,
.dual_color_in_enable =
@@ -3182,7 +3182,7 @@ template <chip CHIP>
static void
tu6_emit_blend_constants(struct tu_cs *cs, const struct vk_color_blend_state *cb)
{
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_RED_F32, 4);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_BLEND_CONSTANT_RED_FP32, 4);
tu_cs_emit_array(cs, (const uint32_t *) cb->blend_constants, 4);
}
@@ -3258,24 +3258,24 @@ tu6_emit_rast(struct tu_cs *cs,
enum a6xx_polygon_mode polygon_mode = tu6_polygon_mode(rs->polygon_mode);
tu_cs_emit_regs(cs,
A6XX_VPC_POLYGON_MODE(polygon_mode));
A6XX_VPC_RAST_CNTL(polygon_mode));
tu_cs_emit_regs(cs,
PC_POLYGON_MODE(CHIP, polygon_mode));
PC_DGEN_RAST_CNTL(CHIP, polygon_mode));
if (CHIP == A7XX || cs->device->physical_device->info->a6xx.is_a702) {
tu_cs_emit_regs(cs,
A6XX_VPC_POLYGON_MODE2(polygon_mode));
A6XX_VPC_PS_RAST_CNTL(polygon_mode));
}
tu_cs_emit_regs(cs, PC_RASTER_CNTL(CHIP,
tu_cs_emit_regs(cs, VPC_RAST_STREAM_CNTL(CHIP,
.stream = rs->rasterization_stream,
.discard = rs->rasterizer_discard_enable));
if (CHIP == A6XX) {
tu_cs_emit_regs(cs, A6XX_VPC_UNKNOWN_9107(
.raster_discard = rs->rasterizer_discard_enable));
} else {
tu_cs_emit_regs(cs, A7XX_PC_RASTER_CNTL_V2(
tu_cs_emit_regs(cs, A7XX_VPC_RAST_STREAM_CNTL_V2(
.stream = rs->rasterization_stream,
.discard = rs->rasterizer_discard_enable));
@@ -3296,7 +3296,7 @@ tu6_emit_rast(struct tu_cs *cs,
.raster_direction = LR_TB,
.conservativerasen = conservative_ras_en));
tu_cs_emit_regs(cs, A7XX_GRAS_SU_RENDER_CNTL(.fs_disable = disable_fs));
tu_cs_emit_regs(cs, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = disable_fs));
tu_cs_emit_regs(cs, A7XX_SP_RENDER_CNTL(.fs_disable = disable_fs));
tu_cs_emit_regs(cs,
A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL(conservative_ras_en));
@@ -3374,7 +3374,7 @@ tu6_emit_ds(struct tu_cs *cs,
* https://gitlab.freedesktop.org/anholt/mesa/-/commits/tu-s-reads
*/
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CONTROL(
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_CNTL(
.stencil_enable = stencil_test_enable,
.stencil_enable_bf = stencil_test_enable,
.stencil_read = stencil_test_enable,
@@ -3388,21 +3388,21 @@ tu6_emit_ds(struct tu_cs *cs,
.zfail_bf = tu6_stencil_op((VkStencilOp)ds->stencil.back.op.depth_fail)));
tu_cs_emit_regs(cs, A6XX_GRAS_SU_STENCIL_CNTL(stencil_test_enable));
tu_cs_emit_regs(cs, A6XX_RB_STENCILMASK(
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_MASK(
.mask = ds->stencil.front.compare_mask,
.bfmask = ds->stencil.back.compare_mask));
tu_cs_emit_regs(cs, A6XX_RB_STENCILWRMASK(
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_WRITE_MASK(
.wrmask = ds->stencil.front.write_mask,
.bfwrmask = ds->stencil.back.write_mask));
tu_cs_emit_regs(cs, A6XX_RB_STENCILREF(
tu_cs_emit_regs(cs, A6XX_RB_STENCIL_REF_CNTL(
.ref = ds->stencil.front.reference,
.bfref = ds->stencil.back.reference));
tu_cs_emit_regs(cs,
A6XX_RB_Z_BOUNDS_MIN(ds->depth.bounds_test.min),
A6XX_RB_Z_BOUNDS_MAX(ds->depth.bounds_test.max));
A6XX_RB_DEPTH_BOUND_MIN(ds->depth.bounds_test.min),
A6XX_RB_DEPTH_BOUND_MAX(ds->depth.bounds_test.max));
}
static const enum mesa_vk_dynamic_graphics_state tu_rb_depth_cntl_state[] = {
@@ -3544,9 +3544,9 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
* if it is read - we have to emit the config.
*/
if (!fsr || (!fs_reads_fsr && vk_fragment_shading_rate_is_disabled(fsr))) {
tu_cs_emit_regs(cs, A6XX_RB_FSR_CONFIG());
tu_cs_emit_regs(cs, A7XX_SP_FSR_CONFIG());
tu_cs_emit_regs(cs, A7XX_GRAS_FSR_CONFIG());
tu_cs_emit_regs(cs, A6XX_RB_VRS_CONFIG());
tu_cs_emit_regs(cs, A7XX_SP_VRS_CONFIG());
tu_cs_emit_regs(cs, A7XX_GRAS_VRS_CONFIG());
return;
}
@@ -3585,15 +3585,15 @@ tu6_emit_fragment_shading_rate(struct tu_cs *cs,
tu_cs_emit_regs(
cs,
A6XX_RB_FSR_CONFIG(.unk2 = true, .pipeline_fsr_enable = enable_draw_fsr,
A6XX_RB_VRS_CONFIG(.unk2 = true, .pipeline_fsr_enable = enable_draw_fsr,
.attachment_fsr_enable = enable_att_fsr,
.primitive_fsr_enable = enable_prim_fsr));
tu_cs_emit_regs(
cs, A7XX_SP_FSR_CONFIG(.pipeline_fsr_enable = enable_draw_fsr,
cs, A7XX_SP_VRS_CONFIG(.pipeline_fsr_enable = enable_draw_fsr,
.attachment_fsr_enable = enable_att_fsr,
.primitive_fsr_enable = enable_prim_fsr));
tu_cs_emit_regs(
cs, A7XX_GRAS_FSR_CONFIG(
cs, A7XX_GRAS_VRS_CONFIG(
.pipeline_fsr_enable = enable_draw_fsr,
.frag_size_x = util_logbase2(frag_width),
.frag_size_y = util_logbase2(frag_height),
src/freedreno/vulkan/tu_query_pool.cc
+11 -11
View File
@@ -27,7 +27,7 @@
#define NSEC_PER_SEC 1000000000ull
#define WAIT_TIMEOUT 5
#define STAT_COUNT ((REG_A6XX_RBBM_PRIMCTR_10 - REG_A6XX_RBBM_PRIMCTR_0) / 2 + 1)
#define STAT_COUNT ((REG_A6XX_RBBM_PIPESTAT_CSINVOCATIONS - REG_A6XX_RBBM_PIPESTAT_IAVERTICES) / 2 + 1)
struct PACKED query_slot {
uint64_t available;
@@ -1045,11 +1045,11 @@ emit_begin_occlusion_query(struct tu_cmd_buffer *cmdbuf,
uint64_t begin_iova = occlusion_query_iova(pool, query, begin);
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNT_CONTROL(.copy = true));
A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (!cmdbuf->device->physical_device->info->a7xx.has_event_write_sample_count) {
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNT_ADDR(.qword = begin_iova));
A6XX_RB_SAMPLE_COUNTER_BASE(.qword = begin_iova));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, ZPASS_DONE);
if (CHIP == A7XX) {
@@ -1130,7 +1130,7 @@ emit_begin_stat_query(struct tu_cmd_buffer *cmdbuf,
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0) |
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PIPESTAT_IAVERTICES) |
CP_REG_TO_MEM_0_CNT(STAT_COUNT * 2) |
CP_REG_TO_MEM_0_64B);
tu_cs_emit_qw(cs, begin_iova);
@@ -1304,7 +1304,7 @@ emit_begin_xfb_query(struct tu_cmd_buffer *cmdbuf,
struct tu_cs *cs = cmdbuf->state.pass ? &cmdbuf->draw_cs : &cmdbuf->cs;
uint64_t begin_iova = primitive_query_iova(pool, query, begin, 0, 0);
tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = begin_iova));
tu_cs_emit_regs(cs, A6XX_VPC_SO_QUERY_BASE(.qword = begin_iova));
tu_emit_event_write<CHIP>(cmdbuf, cs, FD_WRITE_PRIMITIVE_COUNTS);
}
@@ -1339,7 +1339,7 @@ emit_begin_prim_generated_query(struct tu_cmd_buffer *cmdbuf,
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7) |
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PIPESTAT_CINVOCATIONS) |
CP_REG_TO_MEM_0_CNT(2) |
CP_REG_TO_MEM_0_64B);
tu_cs_emit_qw(cs, begin_iova);
@@ -1440,11 +1440,11 @@ emit_end_occlusion_query(struct tu_cmd_buffer *cmdbuf,
}
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNT_CONTROL(.copy = true));
A6XX_RB_SAMPLE_COUNTER_CNTL(.copy = true));
if (!cmdbuf->device->physical_device->info->a7xx.has_event_write_sample_count) {
tu_cs_emit_regs(cs,
A6XX_RB_SAMPLE_COUNT_ADDR(.qword = end_iova));
A6XX_RB_SAMPLE_COUNTER_BASE(.qword = end_iova));
tu_cs_emit_pkt7(cs, CP_EVENT_WRITE, 1);
tu_cs_emit(cs, ZPASS_DONE);
if (CHIP == A7XX) {
@@ -1592,7 +1592,7 @@ emit_end_stat_query(struct tu_cmd_buffer *cmdbuf,
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_0) |
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PIPESTAT_IAVERTICES) |
CP_REG_TO_MEM_0_CNT(STAT_COUNT * 2) |
CP_REG_TO_MEM_0_64B);
tu_cs_emit_qw(cs, end_iova);
@@ -1814,7 +1814,7 @@ emit_end_xfb_query(struct tu_cmd_buffer *cmdbuf,
uint64_t end_generated_iova = primitive_query_iova(pool, query, end, stream_id, 1);
uint64_t available_iova = query_available_iova(pool, query);
tu_cs_emit_regs(cs, A6XX_VPC_SO_STREAM_COUNTS(.qword = end_iova));
tu_cs_emit_regs(cs, A6XX_VPC_SO_QUERY_BASE(.qword = end_iova));
tu_emit_event_write<CHIP>(cmdbuf, cs, FD_WRITE_PRIMITIVE_COUNTS);
tu_cs_emit_wfi(cs);
@@ -1872,7 +1872,7 @@ emit_end_prim_generated_query(struct tu_cmd_buffer *cmdbuf,
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt7(cs, CP_REG_TO_MEM, 3);
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PRIMCTR_7) |
tu_cs_emit(cs, CP_REG_TO_MEM_0_REG(REG_A6XX_RBBM_PIPESTAT_CINVOCATIONS) |
CP_REG_TO_MEM_0_CNT(2) |
CP_REG_TO_MEM_0_64B);
tu_cs_emit_qw(cs, end_iova);
src/freedreno/vulkan/tu_shader.cc
+166 -166
View File
@@ -866,7 +866,7 @@ tu_lower_io(nir_shader *shader, struct tu_device *dev,
/* Disable pushing constants for this stage if none were loaded in the
* shader. If all stages don't load their declared push constants, as
* is often the case under zink, then we could additionally skip
* emitting REG_A7XX_HLSQ_SHARED_CONSTS_IMM entirely.
* emitting REG_A7XX_SP_SHARED_CONSTANT_GFX_0 entirely.
*/
if (!shader_uses_push_consts(shader))
const_state->push_consts = (struct tu_push_constant_range) {};
@@ -1238,45 +1238,45 @@ static const struct xs_config {
} xs_config[] = {
[MESA_SHADER_VERTEX] = {
REG_A6XX_SP_VS_CONFIG,
REG_A6XX_SP_VS_INSTRLEN,
REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_VS_VGPR_CONFIG,
REG_A6XX_SP_VS_INSTR_SIZE,
REG_A6XX_SP_VS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_VS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_VS_VGS_CNTL,
},
[MESA_SHADER_TESS_CTRL] = {
REG_A6XX_SP_HS_CONFIG,
REG_A6XX_SP_HS_INSTRLEN,
REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_HS_VGPR_CONFIG,
REG_A6XX_SP_HS_INSTR_SIZE,
REG_A6XX_SP_HS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_HS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_HS_VGS_CNTL,
},
[MESA_SHADER_TESS_EVAL] = {
REG_A6XX_SP_DS_CONFIG,
REG_A6XX_SP_DS_INSTRLEN,
REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_DS_VGPR_CONFIG,
REG_A6XX_SP_DS_INSTR_SIZE,
REG_A6XX_SP_DS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_DS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_DS_VGS_CNTL,
},
[MESA_SHADER_GEOMETRY] = {
REG_A6XX_SP_GS_CONFIG,
REG_A6XX_SP_GS_INSTRLEN,
REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_GS_VGPR_CONFIG,
REG_A6XX_SP_GS_INSTR_SIZE,
REG_A6XX_SP_GS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_GS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_GS_VGS_CNTL,
},
[MESA_SHADER_FRAGMENT] = {
REG_A6XX_SP_FS_CONFIG,
REG_A6XX_SP_FS_INSTRLEN,
REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_FS_VGPR_CONFIG,
REG_A6XX_SP_PS_CONFIG,
REG_A6XX_SP_PS_INSTR_SIZE,
REG_A6XX_SP_PS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_PS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_PS_VGS_CNTL,
},
[MESA_SHADER_COMPUTE] = {
REG_A6XX_SP_CS_CONFIG,
REG_A6XX_SP_CS_INSTRLEN,
REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_CS_VGPR_CONFIG,
REG_A6XX_SP_CS_INSTR_SIZE,
REG_A6XX_SP_CS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_CS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_CS_VGS_CNTL,
},
};
@@ -1298,7 +1298,7 @@ tu6_emit_xs(struct tu_cs *cs,
xs->info.double_threadsize ? THREAD128 : THREAD64;
switch (stage) {
case MESA_SHADER_VERTEX:
tu_cs_emit_regs(cs, A6XX_SP_VS_CTRL_REG0(
tu_cs_emit_regs(cs, A6XX_SP_VS_CNTL_0(
.halfregfootprint = xs->info.max_half_reg + 1,
.fullregfootprint = xs->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(xs),
@@ -1307,7 +1307,7 @@ tu6_emit_xs(struct tu_cs *cs,
));
break;
case MESA_SHADER_TESS_CTRL:
tu_cs_emit_regs(cs, A6XX_SP_HS_CTRL_REG0(
tu_cs_emit_regs(cs, A6XX_SP_HS_CNTL_0(
.halfregfootprint = xs->info.max_half_reg + 1,
.fullregfootprint = xs->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(xs),
@@ -1315,7 +1315,7 @@ tu6_emit_xs(struct tu_cs *cs,
));
break;
case MESA_SHADER_TESS_EVAL:
tu_cs_emit_regs(cs, A6XX_SP_DS_CTRL_REG0(
tu_cs_emit_regs(cs, A6XX_SP_DS_CNTL_0(
.halfregfootprint = xs->info.max_half_reg + 1,
.fullregfootprint = xs->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(xs),
@@ -1323,7 +1323,7 @@ tu6_emit_xs(struct tu_cs *cs,
));
break;
case MESA_SHADER_GEOMETRY:
tu_cs_emit_regs(cs, A6XX_SP_GS_CTRL_REG0(
tu_cs_emit_regs(cs, A6XX_SP_GS_CNTL_0(
.halfregfootprint = xs->info.max_half_reg + 1,
.fullregfootprint = xs->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(xs),
@@ -1331,7 +1331,7 @@ tu6_emit_xs(struct tu_cs *cs,
));
break;
case MESA_SHADER_FRAGMENT:
tu_cs_emit_regs(cs, A6XX_SP_FS_CTRL_REG0(
tu_cs_emit_regs(cs, A6XX_SP_PS_CNTL_0(
.halfregfootprint = xs->info.max_half_reg + 1,
.fullregfootprint = xs->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(xs),
@@ -1350,7 +1350,7 @@ tu6_emit_xs(struct tu_cs *cs,
case MESA_SHADER_COMPUTE:
thrsz = cs->device->physical_device->info->a6xx
.supports_double_threadsize ? thrsz : THREAD128;
tu_cs_emit_regs(cs, A6XX_SP_CS_CTRL_REG0(
tu_cs_emit_regs(cs, A6XX_SP_CS_CNTL_0(
.halfregfootprint = xs->info.max_half_reg + 1,
.fullregfootprint = xs->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(xs),
@@ -1383,7 +1383,7 @@ tu6_emit_xs(struct tu_cs *cs,
COND(pvtmem->per_wave, A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT));
tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_pvt_mem_hw_stack_offset, 1);
tu_cs_emit(cs, A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(pvtmem->per_sp_size));
tu_cs_emit(cs, A6XX_SP_VS_PVT_MEM_STACK_OFFSET_OFFSET(pvtmem->per_sp_size));
if (cs->device->physical_device->info->chip >= A7XX) {
tu_cs_emit_pkt4(cs, cfg->reg_sp_xs_vgpr_config, 1);
@@ -1524,7 +1524,7 @@ tu6_emit_cs_config(struct tu_cs *cs,
ir3_const_state(v)->push_consts_type == IR3_PUSH_CONSTS_SHARED;
tu6_emit_shared_consts_enable<CHIP>(cs, shared_consts_enable);
tu_cs_emit_regs(cs, HLSQ_INVALIDATE_CMD(CHIP,
tu_cs_emit_regs(cs, SP_UPDATE_CNTL(CHIP,
.cs_state = true,
.cs_uav = true,
.cs_shared_const = shared_consts_enable));
@@ -1537,9 +1537,9 @@ tu6_emit_cs_config(struct tu_cs *cs,
v->constlen > 256 ? CONSTLEN_512 :
(v->constlen > 192 ? CONSTLEN_256 :
(v->constlen > 128 ? CONSTLEN_192 : CONSTLEN_128));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CTRL_REG1, 1);
tu_cs_emit(cs, A6XX_SP_CS_CTRL_REG1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_CTRL_REG1_CONSTANTRAMMODE(mode));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CNTL_1, 1);
tu_cs_emit(cs, A6XX_SP_CS_CNTL_1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_CNTL_1_CONSTANTRAMMODE(mode));
if (CHIP == A6XX && cs->device->physical_device->info->a6xx.has_lpac) {
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CTRL_REG1, 1);
@@ -1554,35 +1554,35 @@ tu6_emit_cs_config(struct tu_cs *cs,
/*
* Devices that do not support double threadsize take the threadsize from
* A6XX_HLSQ_FS_CNTL_0_THREADSIZE instead of A6XX_HLSQ_CS_CNTL_1_THREADSIZE
* A6XX_SP_PS_WAVE_CNTL_THREADSIZE instead of A6XX_SP_CS_WGE_CNTL_THREADSIZE
* which is always set to THREAD128.
*/
enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
enum a6xx_threadsize thrsz_cs = cs->device->physical_device->info->a6xx
.supports_double_threadsize ? thrsz : THREAD128;
if (CHIP == A6XX) {
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_CS_CNTL_0, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CONST_CONFIG_0, 2);
tu_cs_emit(cs,
A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
tu_cs_emit(cs, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz_cs));
A6XX_SP_CS_CONST_CONFIG_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_CONST_CONFIG_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_CONST_CONFIG_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_CONST_CONFIG_0_LOCALIDREGID(local_invocation_id));
tu_cs_emit(cs, A6XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_WGE_CNTL_THREADSIZE(thrsz_cs));
if (!cs->device->physical_device->info->a6xx.supports_double_threadsize) {
tu_cs_emit_pkt4(cs, REG_A6XX_HLSQ_FS_CNTL_0, 1);
tu_cs_emit(cs, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(thrsz));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_WAVE_CNTL, 1);
tu_cs_emit(cs, A6XX_SP_PS_WAVE_CNTL_THREADSIZE(thrsz));
}
if (cs->device->physical_device->info->a6xx.has_lpac) {
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CNTL_0, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_WIE_CNTL_0, 2);
tu_cs_emit(cs,
A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
tu_cs_emit(cs, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_CNTL_1_THREADSIZE(thrsz));
A6XX_SP_CS_WIE_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_WIE_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_LOCALIDREGID(local_invocation_id));
tu_cs_emit(cs, A6XX_SP_CS_WIE_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_1_THREADSIZE(thrsz));
}
} else {
unsigned tile_height = (v->local_size[1] % 8 == 0) ? 3
@@ -1590,21 +1590,21 @@ tu6_emit_cs_config(struct tu_cs *cs,
: (v->local_size[1] % 2 == 0) ? 9
: 17;
tu_cs_emit_regs(
cs, HLSQ_CS_CNTL_1(CHIP,
cs, SP_CS_WGE_CNTL(CHIP,
.linearlocalidregid = regid(63, 0), .threadsize = thrsz_cs,
.workgrouprastorderzfirsten = true,
.wgtilewidth = 4, .wgtileheight = tile_height));
tu_cs_emit_regs(cs, HLSQ_FS_CNTL_0(CHIP, .threadsize = THREAD64));
tu_cs_emit_regs(cs, SP_PS_WAVE_CNTL(CHIP, .threadsize = THREAD64));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_CNTL_0, 1);
tu_cs_emit(cs, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_CS_WIE_CNTL_0, 1);
tu_cs_emit(cs, A6XX_SP_CS_WIE_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_WIE_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_LOCALIDREGID(local_invocation_id));
tu_cs_emit_regs(cs,
SP_CS_CNTL_1(CHIP,
SP_CS_WIE_CNTL_1(CHIP,
.linearlocalidregid = regid(63, 0),
.threadsize = thrsz_cs,
.workitemrastorder =
@@ -1639,7 +1639,7 @@ tu6_emit_vfd_dest(struct tu_cs *cs,
}
tu_cs_emit_regs(cs,
A6XX_VFD_CONTROL_0(
A6XX_VFD_CNTL_0(
.fetch_cnt = attr_count, /* decode_cnt for binning pass ? */
.decode_cnt = attr_count));
@@ -1697,18 +1697,18 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
ij_regid[fs->prefetch_bary_type] == regid(0, 0));
}
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
tu_cs_emit(cs, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
COND(CHIP >= A7XX, A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(0x1ff)) |
COND(CHIP >= A7XX, A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(0x1ff)) |
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL, 1 + fs->num_sampler_prefetch);
tu_cs_emit(cs, A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_COUNT(fs->num_sampler_prefetch) |
COND(CHIP >= A7XX, A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID(0x1ff)) |
COND(CHIP >= A7XX, A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID4COORD(0x1ff)) |
COND(!VALIDREG(ij_regid[IJ_PERSP_PIXEL]),
A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE) |
A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_IJ_WRITE_DISABLE) |
COND(fs->prefetch_end_of_quad,
A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD));
A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_ENDOFQUAD));
for (int i = 0; i < fs->num_sampler_prefetch; i++) {
const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
tu_cs_emit(
cs, SP_FS_PREFETCH_CMD(
cs, SP_PS_INITIAL_TEX_LOAD_CMD(
CHIP, i, .src = prefetch->src, .samp_id = prefetch->samp_id,
.tex_id = prefetch->tex_id, .dst = prefetch->dst,
.wrmask = prefetch->wrmask, .half = prefetch->half_precision,
@@ -1717,32 +1717,32 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
}
if (fs->num_sampler_prefetch > 0) {
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(0), fs->num_sampler_prefetch);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_INITIAL_TEX_INDEX_CMD(0), fs->num_sampler_prefetch);
for (int i = 0; i < fs->num_sampler_prefetch; i++) {
const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
tu_cs_emit(cs,
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID(prefetch->samp_bindless_id) |
A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(prefetch->tex_bindless_id));
A6XX_SP_PS_INITIAL_TEX_INDEX_CMD_SAMP_ID(prefetch->samp_bindless_id) |
A6XX_SP_PS_INITIAL_TEX_INDEX_CMD_TEX_ID(prefetch->tex_bindless_id));
}
}
tu_cs_emit_regs(cs,
HLSQ_CONTROL_1_REG(CHIP,
SP_LB_PARAM_LIMIT(CHIP,
.primallocthreshold =
cs->device->physical_device->info->a6xx.prim_alloc_threshold),
HLSQ_CONTROL_2_REG(CHIP, .faceregid = face_regid,
SP_REG_PROG_ID_0(CHIP, .faceregid = face_regid,
.sampleid = samp_id_regid,
.samplemask = smask_in_regid,
.centerrhw = ij_regid[IJ_PERSP_CENTER_RHW]),
HLSQ_CONTROL_3_REG(CHIP, .ij_persp_pixel = ij_regid[IJ_PERSP_PIXEL],
SP_REG_PROG_ID_1(CHIP, .ij_persp_pixel = ij_regid[IJ_PERSP_PIXEL],
.ij_linear_pixel = ij_regid[IJ_LINEAR_PIXEL],
.ij_persp_centroid = ij_regid[IJ_PERSP_CENTROID],
.ij_linear_centroid = ij_regid[IJ_LINEAR_CENTROID]),
HLSQ_CONTROL_4_REG(CHIP, .ij_persp_sample = ij_regid[IJ_PERSP_SAMPLE],
SP_REG_PROG_ID_2(CHIP, .ij_persp_sample = ij_regid[IJ_PERSP_SAMPLE],
.ij_linear_sample = ij_regid[IJ_LINEAR_SAMPLE],
.xycoordregid = coord_regid,
.zwcoordregid = zwcoord_regid),
HLSQ_CONTROL_5_REG(CHIP, .linelengthregid = 0xfc,
SP_REG_PROG_ID_3(CHIP, .linelengthregid = 0xfc,
.foveationqualityregid = shading_rate_regid), );
if (CHIP >= A7XX) {
@@ -1767,13 +1767,13 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
sysval_regs += 2;
}
tu_cs_emit_regs(cs, A7XX_HLSQ_UNKNOWN_A9AE(.sysval_regs_count = sysval_regs,
tu_cs_emit_regs(cs, A7XX_SP_PS_CNTL_1(.sysval_regs_count = sysval_regs,
.unk8 = 1,
.unk9 = 1));
}
enum a6xx_threadsize thrsz = fs->info.double_threadsize ? THREAD128 : THREAD64;
tu_cs_emit_regs(cs, HLSQ_FS_CNTL_0(CHIP, .threadsize = thrsz, .varyings = enable_varyings));
tu_cs_emit_regs(cs, SP_PS_WAVE_CNTL(CHIP, .threadsize = thrsz, .varyings = enable_varyings));
bool need_size = fs->frag_face || fs->fragcoord_compmask != 0;
bool need_size_persamp = false;
@@ -1784,51 +1784,51 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
need_size = true;
}
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CNTL, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_CL_INTERP_CNTL, 1);
tu_cs_emit(cs,
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
COND(need_size_persamp, A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_PIXEL) |
COND(need_size_persamp, A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(fs->fragcoord_compmask != 0, A6XX_GRAS_CL_INTERP_CNTL_COORD_MASK(fs->fragcoord_compmask)));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_RENDER_CONTROL0, 2);
tu_cs_emit_pkt4(cs, REG_A6XX_RB_INTERP_CNTL, 2);
tu_cs_emit(cs,
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_INTERP_CNTL_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_INTERP_CNTL_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_INTERP_CNTL_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_RB_INTERP_CNTL_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_RB_INTERP_CNTL_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_RB_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_RB_INTERP_CNTL_IJ_LINEAR_PIXEL) |
COND(enable_varyings, A6XX_RB_INTERP_CNTL_UNK10) |
COND(need_size_persamp, A6XX_RB_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(fs->fragcoord_compmask != 0,
A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
A6XX_RB_INTERP_CNTL_COORD_MASK(fs->fragcoord_compmask)));
tu_cs_emit(cs,
A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(
A6XX_RB_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER) |
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_CENTERRHW) |
COND(fs->post_depth_coverage, A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE) |
COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS) |
CONDREG(shading_rate_regid, A6XX_RB_RENDER_CONTROL1_FOVEATION));
CONDREG(smask_in_regid, A6XX_RB_PS_INPUT_CNTL_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_PS_INPUT_CNTL_SAMPLEID) |
CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_PS_INPUT_CNTL_CENTERRHW) |
COND(fs->post_depth_coverage, A6XX_RB_PS_INPUT_CNTL_POSTDEPTHCOVERAGE) |
COND(fs->frag_face, A6XX_RB_PS_INPUT_CNTL_FACENESS) |
CONDREG(shading_rate_regid, A6XX_RB_PS_INPUT_CNTL_FOVEATION));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);
tu_cs_emit(cs, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_PS_SAMPLEFREQ_CNTL, 1);
tu_cs_emit(cs, COND(sample_shading, A6XX_RB_PS_SAMPLEFREQ_CNTL_PER_SAMP_MODE));
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 1);
tu_cs_emit(cs, CONDREG(samp_id_regid, A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID) |
A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER));
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
tu_cs_emit_pkt4(cs, REG_A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL, 1);
tu_cs_emit(cs, COND(sample_shading, A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL_PER_SAMP_MODE));
uint32_t varmask[4] = { 0 };
@@ -1844,7 +1844,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
}
}
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VAR_DISABLE(0), 4);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_VARYING_LM_TRANSFER_CNTL_0_DISABLE(0), 4);
tu_cs_emit(cs, ~varmask[0]);
tu_cs_emit(cs, ~varmask[1]);
tu_cs_emit(cs, ~varmask[2]);
@@ -1853,11 +1853,11 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
unsigned primid_loc = ir3_find_input_loc(fs, VARYING_SLOT_PRIMITIVE_ID);
unsigned viewid_loc = ir3_find_input_loc(fs, VARYING_SLOT_VIEW_INDEX);
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_CNTL_0, 1);
tu_cs_emit(cs, A6XX_VPC_CNTL_0_NUMNONPOSVAR(fs->total_in) |
COND(fs && fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
A6XX_VPC_CNTL_0_PRIMIDLOC(primid_loc) |
A6XX_VPC_CNTL_0_VIEWIDLOC(viewid_loc));
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_PS_CNTL, 1);
tu_cs_emit(cs, A6XX_VPC_PS_CNTL_NUMNONPOSVAR(fs->total_in) |
COND(fs && fs->total_in, A6XX_VPC_PS_CNTL_VARYING) |
A6XX_VPC_PS_CNTL_PRIMIDLOC(primid_loc) |
A6XX_VPC_PS_CNTL_VIEWIDLOC(viewid_loc));
}
template <chip CHIP>
@@ -1899,11 +1899,11 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
}
}
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
COND(fs->dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_OUTPUT_CNTL, 1);
tu_cs_emit(cs, A6XX_SP_PS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
A6XX_SP_PS_OUTPUT_CNTL_SAMPMASK_REGID(smask_regid) |
A6XX_SP_PS_OUTPUT_CNTL_STENCILREF_REGID(stencilref_regid) |
COND(fs->dual_src_blend, A6XX_SP_PS_OUTPUT_CNTL_DUAL_COLOR_IN_ENABLE));
/* There is no point in having component enabled which is not written
* by the shader. Per VK spec it is an UB, however a few apps depend on
@@ -1911,11 +1911,11 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
*/
uint32_t fs_render_components = 0;
tu_cs_emit_pkt4(cs, REG_A6XX_SP_FS_OUTPUT_REG(0), output_reg_count);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_PS_OUTPUT_REG(0), output_reg_count);
for (uint32_t i = 0; i < output_reg_count; i++) {
tu_cs_emit(cs, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
tu_cs_emit(cs, A6XX_SP_PS_OUTPUT_REG_REGID(fragdata_regid[i]) |
(COND(fragdata_regid[i] & HALF_REG_ID,
A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION)));
A6XX_SP_PS_OUTPUT_REG_HALF_PRECISION)));
if (VALIDREG(fragdata_regid[i]) ||
(fragdata_aliased_components & (0xf << (i * 4)))) {
@@ -1924,26 +1924,26 @@ tu6_emit_fs_outputs(struct tu_cs *cs,
}
tu_cs_emit_regs(cs,
A6XX_SP_FS_RENDER_COMPONENTS(.dword = fs_render_components));
A6XX_SP_PS_OUTPUT_MASK(.dword = fs_render_components));
if (CHIP >= A7XX) {
tu_cs_emit_regs(
cs,
A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL(
A7XX_SP_PS_OUTPUT_CONST_CNTL(
.enabled = fragdata_aliased_components != 0),
A7XX_SP_PS_ALIASED_COMPONENTS(.dword = fragdata_aliased_components));
A7XX_SP_PS_OUTPUT_CONST_MASK(.dword = fragdata_aliased_components));
} else {
assert(fragdata_aliased_components == 0);
}
tu_cs_emit_pkt4(cs, REG_A6XX_RB_FS_OUTPUT_CNTL0, 1);
tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
COND(fs->writes_smask, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
COND(fs->writes_stencilref, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
COND(fs->dual_src_blend, A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_PS_OUTPUT_CNTL, 1);
tu_cs_emit(cs, COND(fs->writes_pos, A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_Z) |
COND(fs->writes_smask, A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_SAMPMASK) |
COND(fs->writes_stencilref, A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_STENCILREF) |
COND(fs->dual_src_blend, A6XX_RB_PS_OUTPUT_CNTL_DUAL_COLOR_IN_ENABLE));
tu_cs_emit_regs(cs,
A6XX_RB_RENDER_COMPONENTS(.dword = fs_render_components));
A6XX_RB_PS_OUTPUT_MASK(.dword = fs_render_components));
}
template <chip CHIP>
@@ -1956,9 +1956,9 @@ tu6_emit_vs(struct tu_cs *cs,
uint32_t multiview_views = util_logbase2(view_mask) + 1;
uint32_t multiview_cntl = view_mask ?
A6XX_PC_MULTIVIEW_CNTL_ENABLE |
A6XX_PC_MULTIVIEW_CNTL_VIEWS(multiview_views) |
COND(!multi_pos_output, A6XX_PC_MULTIVIEW_CNTL_DISABLEMULTIPOS)
A6XX_PC_STEREO_RENDERING_CNTL_ENABLE |
A6XX_PC_STEREO_RENDERING_CNTL_VIEWS(multiview_views) |
COND(!multi_pos_output, A6XX_PC_STEREO_RENDERING_CNTL_DISABLEMULTIPOS)
: 0;
/* Copy what the blob does here. This will emit an extra 0x3f
@@ -1968,26 +1968,26 @@ tu6_emit_vs(struct tu_cs *cs,
if (cs->device->physical_device->info->a6xx.has_cp_reg_write) {
tu_cs_emit_pkt7(cs, CP_REG_WRITE, 3);
tu_cs_emit(cs, CP_REG_WRITE_0_TRACKER(UNK_EVENT_WRITE));
tu_cs_emit(cs, REG_A6XX_PC_MULTIVIEW_CNTL);
tu_cs_emit(cs, REG_A6XX_PC_STEREO_RENDERING_CNTL);
} else {
tu_cs_emit_pkt4(cs, REG_A6XX_PC_MULTIVIEW_CNTL, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_STEREO_RENDERING_CNTL, 1);
}
tu_cs_emit(cs, multiview_cntl);
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_MULTIVIEW_CNTL, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_STEREO_RENDERING_CNTL, 1);
tu_cs_emit(cs, multiview_cntl);
if (multiview_cntl &&
cs->device->physical_device->info->a6xx.supports_multiview_mask) {
tu_cs_emit_pkt4(cs, REG_A6XX_PC_MULTIVIEW_MASK, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_STEREO_RENDERING_VIEWMASK, 1);
tu_cs_emit(cs, view_mask);
}
if (CHIP >= A7XX) {
tu_cs_emit_pkt4(cs, REG_A7XX_VPC_MULTIVIEW_CNTL, 1);
tu_cs_emit_pkt4(cs, REG_A7XX_VPC_STEREO_RENDERING_CNTL, 1);
tu_cs_emit(cs, multiview_cntl);
tu_cs_emit_pkt4(cs, REG_A7XX_VPC_MULTIVIEW_MASK, 1);
tu_cs_emit_pkt4(cs, REG_A7XX_VPC_STEREO_RENDERING_VIEWMASK, 1);
tu_cs_emit(cs, view_mask);
}
@@ -2008,11 +2008,11 @@ tu6_emit_vs(struct tu_cs *cs,
const uint32_t vs_primitiveid_regid =
ir3_find_sysval_regid(vs, SYSTEM_VALUE_PRIMITIVE_ID);
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_1, 1);
tu_cs_emit(cs, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
A6XX_VFD_CONTROL_1_REGID4PRIMID(vs_primitiveid_regid) |
A6XX_VFD_CONTROL_1_REGID4VIEWID(viewid_regid));
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CNTL_1, 1);
tu_cs_emit(cs, A6XX_VFD_CNTL_1_REGID4VTX(vertexid_regid) |
A6XX_VFD_CNTL_1_REGID4INST(instanceid_regid) |
A6XX_VFD_CNTL_1_REGID4PRIMID(vs_primitiveid_regid) |
A6XX_VFD_CNTL_1_REGID4VIEWID(viewid_regid));
}
TU_GENX(tu6_emit_vs);
@@ -2026,12 +2026,12 @@ tu6_emit_hs(struct tu_cs *cs,
const uint32_t hs_invocation_regid =
ir3_find_sysval_regid(hs, SYSTEM_VALUE_TCS_HEADER_IR3);
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_2, 1);
tu_cs_emit(cs, A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(hs_rel_patch_regid) |
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CNTL_2, 1);
tu_cs_emit(cs, A6XX_VFD_CNTL_2_REGID_HSRELPATCHID(hs_rel_patch_regid) |
A6XX_VFD_CNTL_2_REGID_INVOCATIONID(hs_invocation_regid));
if (hs) {
tu_cs_emit_pkt4(cs, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_PARAM_0, 1);
tu_cs_emit(cs, hs->tess.tcs_vertices_out);
}
}
@@ -2052,12 +2052,12 @@ tu6_emit_ds(struct tu_cs *cs,
const uint32_t ds_primitiveid_regid =
ir3_find_sysval_regid(ds, SYSTEM_VALUE_PRIMITIVE_ID);
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_3, 2);
tu_cs_emit(cs, A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(ds_rel_patch_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
A6XX_VFD_CONTROL_3_REGID_DSPRIMID(ds_primitiveid_regid));
tu_cs_emit(cs, 0x000000fc); /* VFD_CONTROL_4 */
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CNTL_3, 2);
tu_cs_emit(cs, A6XX_VFD_CNTL_3_REGID_DSRELPATCHID(ds_rel_patch_regid) |
A6XX_VFD_CNTL_3_REGID_TESSX(tess_coord_x_regid) |
A6XX_VFD_CNTL_3_REGID_TESSY(tess_coord_y_regid) |
A6XX_VFD_CNTL_3_REGID_DSPRIMID(ds_primitiveid_regid));
tu_cs_emit(cs, 0x000000fc); /* VFD_CNTL_4 */
}
TU_GENX(tu6_emit_ds);
@@ -2083,8 +2083,8 @@ tu6_emit_gs(struct tu_cs *cs,
const uint32_t gsheader_regid =
ir3_find_sysval_regid(gs, SYSTEM_VALUE_GS_HEADER_IR3);
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_5, 1);
tu_cs_emit(cs, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CNTL_5, 1);
tu_cs_emit(cs, A6XX_VFD_CNTL_5_REGID_GSHEADER(gsheader_regid) |
0xfc00);
if (gs) {
@@ -2095,15 +2095,15 @@ tu6_emit_gs(struct tu_cs *cs,
invocations = gs->gs.invocations - 1;
uint32_t primitive_cntl =
A6XX_PC_PRIMITIVE_CNTL_5(.gs_vertices_out = vertices_out,
A6XX_PC_GS_PARAM_0(.gs_vertices_out = vertices_out,
.gs_invocations = invocations,
.gs_output = output,).value;
tu_cs_emit_pkt4(cs, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_GS_PARAM_0, 1);
tu_cs_emit(cs, primitive_cntl);
if (CHIP >= A7XX) {
tu_cs_emit_pkt4(cs, REG_A7XX_VPC_PRIMITIVE_CNTL_5, 1);
tu_cs_emit_pkt4(cs, REG_A7XX_VPC_GS_PARAM_0, 1);
tu_cs_emit(cs, primitive_cntl);
} else {
tu_cs_emit_pkt4(cs, REG_A6XX_VPC_GS_PARAM, 1);
@@ -2118,8 +2118,8 @@ void
tu6_emit_fs(struct tu_cs *cs,
const struct ir3_shader_variant *fs)
{
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CONTROL_6, 1);
tu_cs_emit(cs, COND(fs && fs->reads_primid, A6XX_VFD_CONTROL_6_PRIMID4PSEN));
tu_cs_emit_pkt4(cs, REG_A6XX_VFD_CNTL_6, 1);
tu_cs_emit(cs, COND(fs && fs->reads_primid, A6XX_VFD_CNTL_6_PRIMID4PSEN));
tu_cs_emit_regs(cs, A6XX_PC_PS_CNTL(.primitiveiden = fs && fs->reads_primid));
src/freedreno/vulkan/tu_util.cc
+1 -1
View File
@@ -240,7 +240,7 @@ tu_tiling_config_update_tile_layout(struct tu_framebuffer *fb,
uint32_t layers = MAX2(fb->layers, pass->num_views);
/* If there is more than one layer, we need to make sure that the layer
* stride is expressible as an offset in RB_BLIT_BASE_GMEM which ignores
* stride is expressible as an offset in RB_RESOLVE_GMEM_BUFFER_BASE which ignores
* the low 12 bits. The layer stride seems to be implicitly calculated from
* the tile width and height so we need to adjust one of them.
*/
src/gallium/drivers/freedreno/a6xx/fd6_blitter.cc
+88 -88
View File
@@ -309,21 +309,21 @@ emit_blit_setup(struct fd_ringbuffer *ring, enum pipe_format pfmt,
ifmt = R2D_UNORM8_SRGB;
}
uint32_t blit_cntl = A6XX_RB_2D_BLIT_CNTL_MASK(0xf) |
A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(fmt) |
A6XX_RB_2D_BLIT_CNTL_IFMT(ifmt) |
A6XX_RB_2D_BLIT_CNTL_ROTATE(rotate) |
COND(color, A6XX_RB_2D_BLIT_CNTL_SOLID_COLOR) |
COND(scissor_enable, A6XX_RB_2D_BLIT_CNTL_SCISSOR);
uint32_t blit_cntl = A6XX_RB_A2D_BLT_CNTL_MASK(0xf) |
A6XX_RB_A2D_BLT_CNTL_COLOR_FORMAT(fmt) |
A6XX_RB_A2D_BLT_CNTL_IFMT(ifmt) |
A6XX_RB_A2D_BLT_CNTL_ROTATE(rotate) |
COND(color, A6XX_RB_A2D_BLT_CNTL_SOLID_COLOR) |
COND(scissor_enable, A6XX_RB_A2D_BLT_CNTL_SCISSOR);
OUT_PKT4(ring, REG_A6XX_RB_2D_BLIT_CNTL, 1);
OUT_PKT4(ring, REG_A6XX_RB_A2D_BLT_CNTL, 1);
OUT_RING(ring, blit_cntl);
OUT_PKT4(ring, REG_A6XX_GRAS_2D_BLIT_CNTL, 1);
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_BLT_CNTL, 1);
OUT_RING(ring, blit_cntl);
if (CHIP >= A7XX) {
OUT_REG(ring, A7XX_TPL1_2D_SRC_CNTL(
OUT_REG(ring, A7XX_TPL1_A2D_BLT_CNTL(
.raw_copy = false,
.start_offset_texels = 0,
.type = A6XX_TEX_2D,
@@ -337,7 +337,7 @@ emit_blit_setup(struct fd_ringbuffer *ring, enum pipe_format pfmt,
* controlling the internal/accumulator format or something like
* that. It's certainly not tied to only the src format.
*/
OUT_REG(ring, SP_2D_DST_FORMAT(
OUT_REG(ring, SP_A2D_OUTPUT_INFO(
CHIP,
.sint = util_format_is_pure_sint(pfmt),
.uint = util_format_is_pure_uint(pfmt),
@@ -346,7 +346,7 @@ emit_blit_setup(struct fd_ringbuffer *ring, enum pipe_format pfmt,
.mask = 0xf,
));
OUT_PKT4(ring, REG_A6XX_RB_2D_UNKNOWN_8C01, 1);
OUT_PKT4(ring, REG_A6XX_RB_A2D_PIXEL_CNTL, 1);
OUT_RING(ring, unknown_8c01);
}
@@ -355,16 +355,16 @@ emit_blit_buffer_dst(struct fd_ringbuffer *ring, struct fd_resource *dst,
unsigned off, unsigned size, a6xx_format color_format)
{
OUT_REG(ring,
A6XX_RB_2D_DST_INFO(
A6XX_RB_A2D_DEST_BUFFER_INFO(
.color_format = color_format,
.tile_mode = TILE6_LINEAR,
.color_swap = WZYX,
),
A6XX_RB_2D_DST(
A6XX_RB_A2D_DEST_BUFFER_BASE(
.bo = dst->bo,
.bo_offset = off,
),
A6XX_RB_2D_DST_PITCH(size),
A6XX_RB_A2D_DEST_BUFFER_PITCH(size),
);
}
@@ -439,7 +439,7 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
* Emit source:
*/
OUT_REG(ring,
SP_PS_2D_SRC_INFO(
TPL1_A2D_SRC_TEXTURE_INFO(
CHIP,
.color_format = FMT6_8_UNORM,
.tile_mode = TILE6_LINEAR,
@@ -447,17 +447,17 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
.unk20 = true,
.unk22 = true,
),
SP_PS_2D_SRC_SIZE(
TPL1_A2D_SRC_TEXTURE_SIZE(
CHIP,
.width = sshift + w,
.height = 1,
),
SP_PS_2D_SRC(
TPL1_A2D_SRC_TEXTURE_BASE(
CHIP,
.bo = src->bo,
.bo_offset = soff,
),
SP_PS_2D_SRC_PITCH(
TPL1_A2D_SRC_TEXTURE_PITCH(
CHIP,
.pitch = p,
),
@@ -472,16 +472,16 @@ emit_blit_buffer(struct fd_context *ctx, struct fd_ringbuffer *ring,
* Blit command:
*/
OUT_REG(ring,
A6XX_GRAS_2D_SRC_TL_X(sshift),
A6XX_GRAS_2D_SRC_BR_X(sshift + w - 1),
A6XX_GRAS_2D_SRC_TL_Y(0),
A6XX_GRAS_2D_SRC_BR_Y(0),
A6XX_GRAS_A2D_SRC_XMIN(sshift),
A6XX_GRAS_A2D_SRC_XMAX(sshift + w - 1),
A6XX_GRAS_A2D_SRC_YMIN(0),
A6XX_GRAS_A2D_SRC_YMAX(0),
);
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dshift) | A6XX_GRAS_2D_DST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dshift + w - 1) |
A6XX_GRAS_2D_DST_BR_Y(0));
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_DEST_TL, 2);
OUT_RING(ring, A6XX_GRAS_A2D_DEST_TL_X(dshift) | A6XX_GRAS_A2D_DEST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_A2D_DEST_BR_X(dshift + w - 1) |
A6XX_GRAS_A2D_DEST_BR_Y(0));
emit_blit_fini<CHIP>(ctx, ring);
}
@@ -497,23 +497,23 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt
emit_blit_setup<CHIP>(ring, PIPE_FORMAT_R8_UNORM, false, &color, 0, ROTATE_0);
OUT_REG(ring,
SP_PS_2D_SRC_INFO(CHIP),
SP_PS_2D_SRC_SIZE(CHIP),
SP_PS_2D_SRC(CHIP),
SP_PS_2D_SRC_PITCH(CHIP),
TPL1_A2D_SRC_TEXTURE_INFO(CHIP),
TPL1_A2D_SRC_TEXTURE_SIZE(CHIP),
TPL1_A2D_SRC_TEXTURE_BASE(CHIP),
TPL1_A2D_SRC_TEXTURE_PITCH(CHIP),
);
OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
OUT_PKT4(ring, REG_A6XX_RB_A2D_CLEAR_COLOR_DW0, 4);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
OUT_REG(ring,
A6XX_GRAS_2D_SRC_TL_X(0),
A6XX_GRAS_2D_SRC_BR_X(0),
A6XX_GRAS_2D_SRC_TL_Y(0),
A6XX_GRAS_2D_SRC_BR_Y(0),
A6XX_GRAS_A2D_SRC_XMIN(0),
A6XX_GRAS_A2D_SRC_XMAX(0),
A6XX_GRAS_A2D_SRC_YMIN(0),
A6XX_GRAS_A2D_SRC_YMAX(0),
);
unsigned size = rsc->layout.slices[0].offset;
@@ -544,10 +544,10 @@ fd6_clear_ubwc(struct fd_batch *batch, struct fd_resource *rsc) assert_dt
* Blit command:
*/
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_DEST_TL, 2);
OUT_RING(ring, A6XX_GRAS_A2D_DEST_TL_X(0) | A6XX_GRAS_A2D_DEST_TL_Y(0));
OUT_RING(ring,
A6XX_GRAS_2D_DST_BR_X(w - 1) | A6XX_GRAS_2D_DST_BR_Y(h - 1));
A6XX_GRAS_A2D_DEST_BR_X(w - 1) | A6XX_GRAS_A2D_DEST_BR_Y(h - 1));
emit_blit_fini<CHIP>(batch->ctx, ring);
offset += w * h;
@@ -581,22 +581,22 @@ emit_blit_dst(struct fd_ringbuffer *ring, struct pipe_resource *prsc,
fmt = FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8;
OUT_REG(ring,
A6XX_RB_2D_DST_INFO(
A6XX_RB_A2D_DEST_BUFFER_INFO(
.color_format = fmt,
.tile_mode = tile,
.color_swap = swap,
.flags = ubwc_enabled,
.srgb = util_format_is_srgb(pfmt),
),
A6XX_RB_2D_DST(
A6XX_RB_A2D_DEST_BUFFER_BASE(
.bo = dst->bo,
.bo_offset = off,
),
A6XX_RB_2D_DST_PITCH(pitch),
A6XX_RB_A2D_DEST_BUFFER_PITCH(pitch),
);
if (ubwc_enabled) {
OUT_PKT4(ring, REG_A6XX_RB_2D_DST_FLAGS, 6);
OUT_PKT4(ring, REG_A6XX_RB_A2D_DEST_FLAG_BUFFER_BASE, 6);
fd6_emit_flag_reference(ring, dst, level, layer);
OUT_RING(ring, 0x00000000);
OUT_RING(ring, 0x00000000);
@@ -627,7 +627,7 @@ emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info,
sfmt = FMT6_A8_UNORM;
OUT_REG(ring,
SP_PS_2D_SRC_INFO(
TPL1_A2D_SRC_TEXTURE_INFO(
CHIP,
.color_format = sfmt,
.tile_mode = stile,
@@ -640,17 +640,17 @@ emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info,
.unk20 = true,
.unk22 = true,
),
SP_PS_2D_SRC_SIZE(
TPL1_A2D_SRC_TEXTURE_SIZE(
CHIP,
.width = width,
.height = height,
),
SP_PS_2D_SRC(
TPL1_A2D_SRC_TEXTURE_BASE(
CHIP,
.bo = src->bo,
.bo_offset = soff,
),
SP_PS_2D_SRC_PITCH(
TPL1_A2D_SRC_TEXTURE_PITCH(
CHIP,
.pitch = pitch,
),
@@ -658,12 +658,12 @@ emit_blit_src(struct fd_ringbuffer *ring, const struct pipe_blit_info *info,
if (subwc_enabled && fd_resource_ubwc_enabled(src, info->src.level)) {
OUT_REG(ring,
SP_PS_2D_SRC_FLAGS(
TPL1_A2D_SRC_TEXTURE_FLAG_BASE(
CHIP,
.bo = src->bo,
.bo_offset = fd_resource_ubwc_offset(src, info->src.level, layer),
),
SP_PS_2D_SRC_FLAGS_PITCH(
TPL1_A2D_SRC_TEXTURE_FLAG_PITCH(
CHIP, fdl_ubwc_pitch(&src->layout, info->src.level)),
);
}
@@ -709,25 +709,25 @@ emit_blit_texture(struct fd_context *ctx, struct fd_ringbuffer *ring,
enum a6xx_rotation rotate = rotates[mirror_y][mirror_x];
OUT_REG(ring,
A6XX_GRAS_2D_SRC_TL_X(MIN2(sx1, sx2)),
A6XX_GRAS_2D_SRC_BR_X(MAX2(sx1, sx2) - 1),
A6XX_GRAS_2D_SRC_TL_Y(MIN2(sy1, sy2)),
A6XX_GRAS_2D_SRC_BR_Y(MAX2(sy1, sy2) - 1),
A6XX_GRAS_A2D_SRC_XMIN(MIN2(sx1, sx2)),
A6XX_GRAS_A2D_SRC_XMAX(MAX2(sx1, sx2) - 1),
A6XX_GRAS_A2D_SRC_YMIN(MIN2(sy1, sy2)),
A6XX_GRAS_A2D_SRC_YMAX(MAX2(sy1, sy2) - 1),
);
OUT_REG(ring,
A6XX_GRAS_2D_DST_TL(.x = MIN2(dx1, dx2),
A6XX_GRAS_A2D_DEST_TL(.x = MIN2(dx1, dx2),
.y = MIN2(dy1, dy2)),
A6XX_GRAS_2D_DST_BR(.x = MAX2(dx1, dx2) - 1,
A6XX_GRAS_A2D_DEST_BR(.x = MAX2(dx1, dx2) - 1,
.y = MAX2(dy1, dy2) - 1),
);
if (info->scissor_enable) {
OUT_PKT4(ring, REG_A6XX_GRAS_2D_RESOLVE_CNTL_1, 2);
OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.minx) |
A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.miny));
OUT_RING(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1_X(info->scissor.maxx - 1) |
A6XX_GRAS_2D_RESOLVE_CNTL_1_Y(info->scissor.maxy - 1));
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_SCISSOR_TL, 2);
OUT_RING(ring, A6XX_GRAS_A2D_SCISSOR_TL_X(info->scissor.minx) |
A6XX_GRAS_A2D_SCISSOR_TL_Y(info->scissor.miny));
OUT_RING(ring, A6XX_GRAS_A2D_SCISSOR_TL_X(info->scissor.maxx - 1) |
A6XX_GRAS_A2D_SCISSOR_TL_Y(info->scissor.maxy - 1));
}
emit_blit_setup<CHIP>(ring, info->dst.format, info->scissor_enable, NULL, 0, rotate);
@@ -762,7 +762,7 @@ emit_clear_color(struct fd_ringbuffer *ring, enum pipe_format pfmt,
break;
}
OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
OUT_PKT4(ring, REG_A6XX_RB_A2D_CLEAR_COLOR_DW0, 4);
switch (fd6_ifmt(fd6_color_format(pfmt, TILE6_LINEAR))) {
case R2D_UNORM8:
case R2D_UNORM8_SRGB:
@@ -812,10 +812,10 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf,
fprintf(stderr, "\n");
}
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(zsbuf->lrz_layout.lrz_pitch - 1) |
A6XX_GRAS_2D_DST_BR_Y(zsbuf->lrz_layout.lrz_height - 1));
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_DEST_TL, 2);
OUT_RING(ring, A6XX_GRAS_A2D_DEST_TL_X(0) | A6XX_GRAS_A2D_DEST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_A2D_DEST_BR_X(zsbuf->lrz_layout.lrz_pitch - 1) |
A6XX_GRAS_A2D_DEST_BR_Y(zsbuf->lrz_layout.lrz_height - 1));
union pipe_color_union clear_color = { .f = {depth} };
@@ -823,15 +823,15 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf,
emit_blit_setup<CHIP>(ring, PIPE_FORMAT_Z16_UNORM, false, &clear_color, 0, ROTATE_0);
OUT_REG(ring,
A6XX_RB_2D_DST_INFO(
A6XX_RB_A2D_DEST_BUFFER_INFO(
.color_format = FMT6_16_UNORM,
.tile_mode = TILE6_LINEAR,
.color_swap = WZYX,
),
A6XX_RB_2D_DST(
A6XX_RB_A2D_DEST_BUFFER_BASE(
.bo = lrz,
),
A6XX_RB_2D_DST_PITCH(zsbuf->lrz_layout.lrz_pitch * 2),
A6XX_RB_A2D_DEST_BUFFER_PITCH(zsbuf->lrz_layout.lrz_pitch * 2),
);
/*
@@ -985,10 +985,10 @@ fd6_clear_buffer(struct pipe_context *pctx,
emit_blit_buffer_dst(ring, rsc, doff, 0, fmt);
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(dst_x) | A6XX_GRAS_2D_DST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(dst_x + width - 1) |
A6XX_GRAS_2D_DST_BR_Y(0));
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_DEST_TL, 2);
OUT_RING(ring, A6XX_GRAS_A2D_DEST_TL_X(dst_x) | A6XX_GRAS_A2D_DEST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_A2D_DEST_BR_X(dst_x + width - 1) |
A6XX_GRAS_A2D_DEST_BR_Y(0));
emit_blit_fini<CHIP>(ctx, ring);
@@ -1024,11 +1024,11 @@ fd6_clear_surface(struct fd_context *ctx, struct fd_ringbuffer *ring,
}
uint32_t nr_samples = fd_resource_nr_samples(psurf->texture);
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(box2d->x * nr_samples) |
A6XX_GRAS_2D_DST_TL_Y(box2d->y));
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X((box2d->x + box2d->width) * nr_samples - 1) |
A6XX_GRAS_2D_DST_BR_Y(box2d->y + box2d->height - 1));
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_DEST_TL, 2);
OUT_RING(ring, A6XX_GRAS_A2D_DEST_TL_X(box2d->x * nr_samples) |
A6XX_GRAS_A2D_DEST_TL_Y(box2d->y));
OUT_RING(ring, A6XX_GRAS_A2D_DEST_BR_X((box2d->x + box2d->width) * nr_samples - 1) |
A6XX_GRAS_A2D_DEST_BR_Y(box2d->y + box2d->height - 1));
union pipe_color_union clear_color = convert_color(psurf->format, color);
@@ -1142,16 +1142,16 @@ fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring,
unsigned width = pipe_surface_width(psurf);
unsigned height = pipe_surface_height(psurf);
OUT_PKT4(ring, REG_A6XX_GRAS_2D_DST_TL, 2);
OUT_RING(ring, A6XX_GRAS_2D_DST_TL_X(0) | A6XX_GRAS_2D_DST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_2D_DST_BR_X(width - 1) |
A6XX_GRAS_2D_DST_BR_Y(height - 1));
OUT_PKT4(ring, REG_A6XX_GRAS_A2D_DEST_TL, 2);
OUT_RING(ring, A6XX_GRAS_A2D_DEST_TL_X(0) | A6XX_GRAS_A2D_DEST_TL_Y(0));
OUT_RING(ring, A6XX_GRAS_A2D_DEST_BR_X(width - 1) |
A6XX_GRAS_A2D_DEST_BR_Y(height - 1));
OUT_REG(ring,
A6XX_GRAS_2D_SRC_TL_X(0),
A6XX_GRAS_2D_SRC_BR_X(pipe_surface_width(psurf) - 1),
A6XX_GRAS_2D_SRC_TL_Y(0),
A6XX_GRAS_2D_SRC_BR_Y(pipe_surface_height(psurf) - 1),
A6XX_GRAS_A2D_SRC_XMIN(0),
A6XX_GRAS_A2D_SRC_XMAX(pipe_surface_width(psurf) - 1),
A6XX_GRAS_A2D_SRC_YMIN(0),
A6XX_GRAS_A2D_SRC_YMAX(pipe_surface_height(psurf) - 1),
);
/* Enable scissor bit, which will take into account the window scissor
@@ -1169,7 +1169,7 @@ fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring,
enum a3xx_msaa_samples samples = fd_msaa_samples(batch->framebuffer.samples);
OUT_REG(ring,
SP_PS_2D_SRC_INFO(
TPL1_A2D_SRC_TEXTURE_INFO(
CHIP,
.color_format = sfmt,
.tile_mode = TILE6_2,
@@ -1180,16 +1180,16 @@ fd6_resolve_tile(struct fd_batch *batch, struct fd_ringbuffer *ring,
.unk20 = true,
.unk22 = true,
),
SP_PS_2D_SRC_SIZE(
TPL1_A2D_SRC_TEXTURE_SIZE(
CHIP,
.width = pipe_surface_width(psurf),
.height = pipe_surface_height(psurf),
),
SP_PS_2D_SRC(
TPL1_A2D_SRC_TEXTURE_BASE(
CHIP,
.qword = gmem_base,
),
SP_PS_2D_SRC_PITCH(
TPL1_A2D_SRC_TEXTURE_PITCH(
CHIP,
.pitch = gmem_pitch,
),
src/gallium/drivers/freedreno/a6xx/fd6_compute.cc
+42 -42
View File
@@ -30,7 +30,7 @@ cs_program_emit_local_size(struct fd_context *ctx, struct fd_ringbuffer *ring,
{
/*
* Devices that do not support double threadsize take the threadsize from
* A6XX_HLSQ_FS_CNTL_0_THREADSIZE instead of A6XX_HLSQ_CS_CNTL_1_THREADSIZE
* A6XX_SP_PS_WAVE_CNTL_THREADSIZE instead of A6XX_SP_CS_WGE_CNTL_THREADSIZE
* which is always set to THREAD128.
*/
enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
@@ -44,7 +44,7 @@ cs_program_emit_local_size(struct fd_context *ctx, struct fd_ringbuffer *ring,
: 17;
OUT_REG(ring,
HLSQ_CS_CNTL_1(
SP_CS_WGE_CNTL(
CHIP,
.linearlocalidregid = INVALID_REG,
.threadsize = thrsz_cs,
@@ -55,7 +55,7 @@ cs_program_emit_local_size(struct fd_context *ctx, struct fd_ringbuffer *ring,
);
OUT_REG(ring,
A7XX_HLSQ_CS_LAST_LOCAL_SIZE(
A7XX_SP_CS_NDRANGE_7(
.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1,
@@ -70,12 +70,12 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
struct ir3_shader_variant *v)
assert_dt
{
OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
OUT_REG(ring, SP_UPDATE_CNTL(CHIP, .vs_state = true, .hs_state = true,
.ds_state = true, .gs_state = true,
.fs_state = true, .cs_state = true,
.cs_uav = true, .gfx_uav = true, ));
OUT_REG(ring, HLSQ_CS_CNTL(
OUT_REG(ring, SP_CS_CONST_CONFIG(
CHIP,
.constlen = v->constlen,
.enabled = true,
@@ -96,7 +96,7 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
/*
* Devices that do not support double threadsize take the threadsize from
* A6XX_HLSQ_FS_CNTL_0_THREADSIZE instead of A6XX_HLSQ_CS_CNTL_1_THREADSIZE
* A6XX_SP_PS_WAVE_CNTL_THREADSIZE instead of A6XX_SP_CS_WGE_CNTL_THREADSIZE
* which is always set to THREAD128.
*/
enum a6xx_threadsize thrsz = v->info.double_threadsize ? THREAD128 : THREAD64;
@@ -104,31 +104,31 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
.supports_double_threadsize ? thrsz : THREAD128;
if (CHIP == A6XX) {
OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CNTL_0, 2);
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_HLSQ_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
OUT_RING(ring, A6XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_HLSQ_CS_CNTL_1_THREADSIZE(thrsz_cs));
OUT_PKT4(ring, REG_A6XX_SP_CS_CONST_CONFIG_0, 2);
OUT_RING(ring, A6XX_SP_CS_CONST_CONFIG_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_CONST_CONFIG_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_CONST_CONFIG_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_CONST_CONFIG_0_LOCALIDREGID(local_invocation_id));
OUT_RING(ring, A6XX_SP_CS_WGE_CNTL_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_WGE_CNTL_THREADSIZE(thrsz_cs));
if (!ctx->screen->info->a6xx.supports_double_threadsize) {
OUT_PKT4(ring, REG_A6XX_HLSQ_FS_CNTL_0, 1);
OUT_RING(ring, A6XX_HLSQ_FS_CNTL_0_THREADSIZE(thrsz));
OUT_PKT4(ring, REG_A6XX_SP_PS_WAVE_CNTL, 1);
OUT_RING(ring, A6XX_SP_PS_WAVE_CNTL_THREADSIZE(thrsz));
}
if (ctx->screen->info->a6xx.has_lpac) {
OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_0, 2);
OUT_RING(ring, A6XX_SP_CS_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_CNTL_0_LOCALIDREGID(local_invocation_id));
OUT_RING(ring, A6XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_CNTL_1_THREADSIZE(thrsz));
OUT_PKT4(ring, REG_A6XX_SP_CS_WIE_CNTL_0, 2);
OUT_RING(ring, A6XX_SP_CS_WIE_CNTL_0_WGIDCONSTID(work_group_id) |
A6XX_SP_CS_WIE_CNTL_0_WGSIZECONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_WGOFFSETCONSTID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_0_LOCALIDREGID(local_invocation_id));
OUT_RING(ring, A6XX_SP_CS_WIE_CNTL_1_LINEARLOCALIDREGID(regid(63, 0)) |
A6XX_SP_CS_WIE_CNTL_1_THREADSIZE(thrsz));
}
} else {
OUT_REG(ring, HLSQ_FS_CNTL_0(CHIP, .threadsize = THREAD64));
OUT_REG(ring, SP_PS_WAVE_CNTL(CHIP, .threadsize = THREAD64));
OUT_REG(ring,
A6XX_SP_CS_CNTL_0(
A6XX_SP_CS_WIE_CNTL_0(
.wgidconstid = work_group_id,
.wgsizeconstid = INVALID_REG,
.wgoffsetconstid = INVALID_REG,
@@ -136,7 +136,7 @@ cs_program_emit(struct fd_context *ctx, struct fd_ringbuffer *ring,
)
);
OUT_REG(ring,
SP_CS_CNTL_1(
SP_CS_WIE_CNTL_1(
CHIP,
.linearlocalidregid = INVALID_REG,
.threadsize = thrsz_cs,
@@ -191,10 +191,10 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
* affects all known gens. Based on various experiments it appears that the
* issue is that when prefetching a branch destination and there is a cache
* miss, when fetching from memory the HW bounds-checks the fetch against
* SP_CS_INSTRLEN, except when one of the two register contexts is active
* it accidentally fetches SP_FS_INSTRLEN from the other (inactive)
* SP_CS_INSTR_SIZE, except when one of the two register contexts is active
* it accidentally fetches SP_PS_INSTR_SIZE from the other (inactive)
* context. To workaround it we set the FS instrlen here and do a dummy
* event to roll the context (because it fetches SP_FS_INSTRLEN from the
* event to roll the context (because it fetches SP_PS_INSTR_SIZE from the
* "wrong" context). Because the bug seems to involve cache misses, we
* don't emit this if the entire CS program fits in cache, which will
* hopefully be the majority of cases.
@@ -202,7 +202,7 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
* See https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19023
*/
if (emit_instrlen_workaround) {
OUT_REG(ring, A6XX_SP_FS_INSTRLEN(cs->v->instrlen));
OUT_REG(ring, A6XX_SP_PS_INSTR_SIZE(cs->v->instrlen));
fd6_event_write<CHIP>(ctx, ring, FD_LABEL);
}
@@ -224,9 +224,9 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
cs->v->constlen > 256 ? CONSTLEN_512 :
(cs->v->constlen > 192 ? CONSTLEN_256 :
(cs->v->constlen > 128 ? CONSTLEN_192 : CONSTLEN_128));
OUT_PKT4(ring, REG_A6XX_SP_CS_CTRL_REG1, 1);
OUT_RING(ring, A6XX_SP_CS_CTRL_REG1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_CTRL_REG1_CONSTANTRAMMODE(mode));
OUT_PKT4(ring, REG_A6XX_SP_CS_CNTL_1, 1);
OUT_RING(ring, A6XX_SP_CS_CNTL_1_SHARED_SIZE(shared_size) |
A6XX_SP_CS_CNTL_1_CONSTANTRAMMODE(mode));
if (CHIP == A6XX && ctx->screen->info->a6xx.has_lpac) {
OUT_PKT4(ring, REG_A6XX_HLSQ_CS_CTRL_REG1, 1);
@@ -246,34 +246,34 @@ fd6_launch_grid(struct fd_context *ctx, const struct pipe_grid_info *info) in_dt
}
OUT_REG(ring,
HLSQ_CS_NDRANGE_0(
SP_CS_NDRANGE_0(
CHIP,
.kerneldim = work_dim,
.localsizex = local_size[0] - 1,
.localsizey = local_size[1] - 1,
.localsizez = local_size[2] - 1,
),
HLSQ_CS_NDRANGE_1(
SP_CS_NDRANGE_1(
CHIP,
.globalsize_x = local_size[0] * num_groups[0],
),
HLSQ_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
HLSQ_CS_NDRANGE_3(
SP_CS_NDRANGE_2(CHIP, .globaloff_x = 0),
SP_CS_NDRANGE_3(
CHIP,
.globalsize_y = local_size[1] * num_groups[1],
),
HLSQ_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
HLSQ_CS_NDRANGE_5(
SP_CS_NDRANGE_4(CHIP, .globaloff_y = 0),
SP_CS_NDRANGE_5(
CHIP,
.globalsize_z = local_size[2] * num_groups[2],
),
HLSQ_CS_NDRANGE_6(CHIP, .globaloff_z = 0),
SP_CS_NDRANGE_6(CHIP, .globaloff_z = 0),
);
OUT_REG(ring,
HLSQ_CS_KERNEL_GROUP_X(CHIP, 1),
HLSQ_CS_KERNEL_GROUP_Y(CHIP, 1),
HLSQ_CS_KERNEL_GROUP_Z(CHIP, 1),
SP_CS_KERNEL_GROUP_X(CHIP, 1),
SP_CS_KERNEL_GROUP_Y(CHIP, 1),
SP_CS_KERNEL_GROUP_Z(CHIP, 1),
);
if (info->indirect) {
src/gallium/drivers/freedreno/a6xx/fd6_context.cc
+13 -13
View File
@@ -78,7 +78,7 @@ fd6_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
fd_ringbuffer_new_object(ctx->pipe, 4 * (num_elements * 4 + 1));
struct fd_ringbuffer *ring = state->stateobj;
OUT_PKT4(ring, REG_A6XX_VFD_DECODE(0), 2 * num_elements);
OUT_PKT4(ring, REG_A6XX_VFD_FETCH_INSTR(0), 2 * num_elements);
for (int32_t i = 0; i < num_elements; i++) {
const struct pipe_vertex_element *elem = &elements[i];
enum pipe_format pfmt = (enum pipe_format)elem->src_format;
@@ -86,22 +86,22 @@ fd6_vertex_state_create(struct pipe_context *pctx, unsigned num_elements,
bool isint = util_format_is_pure_integer(pfmt);
assert(fmt != FMT6_NONE);
OUT_RING(ring, A6XX_VFD_DECODE_INSTR_IDX(elem->vertex_buffer_index) |
A6XX_VFD_DECODE_INSTR_OFFSET(elem->src_offset) |
A6XX_VFD_DECODE_INSTR_FORMAT(fmt) |
OUT_RING(ring, A6XX_VFD_FETCH_INSTR_INSTR_IDX(elem->vertex_buffer_index) |
A6XX_VFD_FETCH_INSTR_INSTR_OFFSET(elem->src_offset) |
A6XX_VFD_FETCH_INSTR_INSTR_FORMAT(fmt) |
COND(elem->instance_divisor,
A6XX_VFD_DECODE_INSTR_INSTANCED) |
A6XX_VFD_DECODE_INSTR_SWAP(fd6_vertex_swap(pfmt)) |
A6XX_VFD_DECODE_INSTR_UNK30 |
COND(!isint, A6XX_VFD_DECODE_INSTR_FLOAT));
A6XX_VFD_FETCH_INSTR_INSTR_INSTANCED) |
A6XX_VFD_FETCH_INSTR_INSTR_SWAP(fd6_vertex_swap(pfmt)) |
A6XX_VFD_FETCH_INSTR_INSTR_UNK30 |
COND(!isint, A6XX_VFD_FETCH_INSTR_INSTR_FLOAT));
OUT_RING(ring,
MAX2(1, elem->instance_divisor)); /* VFD_DECODE[j].STEP_RATE */
MAX2(1, elem->instance_divisor)); /* VFD_FETCH_INSTR[j].STEP_RATE */
}
for (int32_t i = 0; i < num_elements; i++) {
const struct pipe_vertex_element *elem = &elements[i];
OUT_PKT4(ring, REG_A6XX_VFD_FETCH_STRIDE(elem->vertex_buffer_index), 1);
OUT_PKT4(ring, REG_A6XX_VFD_VERTEX_BUFFER_STRIDE(elem->vertex_buffer_index), 1);
OUT_RING(ring, elem->src_stride);
}
@@ -311,9 +311,9 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv,
struct fd_ringbuffer *ring =
fd_ringbuffer_new_object(fd6_ctx->base.pipe, 6 * 4);
OUT_REG(ring, A6XX_GRAS_SAMPLE_CONFIG());
OUT_REG(ring, A6XX_RB_SAMPLE_CONFIG());
OUT_REG(ring, A6XX_SP_TP_SAMPLE_CONFIG());
OUT_REG(ring, A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL());
OUT_REG(ring, A6XX_RB_MSAA_SAMPLE_POS_CNTL());
OUT_REG(ring, A6XX_TPL1_MSAA_SAMPLE_POS_CNTL());
fd6_ctx->sample_locations_disable_stateobj = ring;
src/gallium/drivers/freedreno/a6xx/fd6_emit.cc
+71 -71
View File
@@ -58,7 +58,7 @@ build_vbo_state(struct fd6_emit *emit) assert_dt
emit->ctx->batch->submit, 4 * dwords, FD_RINGBUFFER_STREAMING);
for (int32_t j = 0; j < cnt; j++) {
OUT_PKT4(ring, REG_A6XX_VFD_FETCH(j), 3);
OUT_PKT4(ring, REG_A6XX_VFD_VERTEX_BUFFER(j), 3);
const struct pipe_vertex_buffer *vb = &vtx->vertexbuf.vb[j];
struct fd_resource *rsc = fd_resource(vb->buffer.resource);
if (rsc == NULL) {
@@ -70,7 +70,7 @@ build_vbo_state(struct fd6_emit *emit) assert_dt
uint32_t size = vb->buffer.resource->width0 - off;
OUT_RELOC(ring, rsc->bo, off, 0, 0);
OUT_RING(ring, size); /* VFD_FETCH[j].SIZE */
OUT_RING(ring, size); /* VFD_VERTEX_BUFFER[j].SIZE */
}
}
@@ -314,18 +314,18 @@ build_prog_fb_rast(struct fd6_emit *emit) assert_dt
if (blend->use_dual_src_blend)
nr++;
OUT_PKT4(ring, REG_A6XX_RB_FS_OUTPUT_CNTL0, 2);
OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_Z) |
OUT_PKT4(ring, REG_A6XX_RB_PS_OUTPUT_CNTL, 2);
OUT_RING(ring, COND(fs->writes_pos, A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_Z) |
COND(fs->writes_smask && pfb->samples > 1,
A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_SAMPMASK) |
A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_SAMPMASK) |
COND(fs->writes_stencilref,
A6XX_RB_FS_OUTPUT_CNTL0_FRAG_WRITES_STENCILREF) |
A6XX_RB_PS_OUTPUT_CNTL_FRAG_WRITES_STENCILREF) |
COND(blend->use_dual_src_blend,
A6XX_RB_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
OUT_RING(ring, A6XX_RB_FS_OUTPUT_CNTL1_MRT(nr));
A6XX_RB_PS_OUTPUT_CNTL_DUAL_COLOR_IN_ENABLE));
OUT_RING(ring, A6XX_RB_PS_MRT_CNTL_MRT(nr));
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL1, 1);
OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL1_MRT(nr));
OUT_PKT4(ring, REG_A6XX_SP_PS_MRT_CNTL, 1);
OUT_RING(ring, A6XX_SP_PS_MRT_CNTL_MRT(nr));
unsigned mrt_components = 0;
for (unsigned i = 0; i < pfb->nr_cbufs; i++) {
@@ -340,8 +340,8 @@ build_prog_fb_rast(struct fd6_emit *emit) assert_dt
mrt_components &= prog->mrt_components;
OUT_REG(ring, A6XX_SP_FS_RENDER_COMPONENTS(.dword = mrt_components));
OUT_REG(ring, A6XX_RB_RENDER_COMPONENTS(.dword = mrt_components));
OUT_REG(ring, A6XX_SP_PS_OUTPUT_MASK(.dword = mrt_components));
OUT_REG(ring, A6XX_RB_PS_OUTPUT_MASK(.dword = mrt_components));
return ring;
}
@@ -354,10 +354,10 @@ build_blend_color(struct fd6_emit *emit) assert_dt
struct fd_ringbuffer *ring = fd_submit_new_ringbuffer(
ctx->batch->submit, 5 * 4, FD_RINGBUFFER_STREAMING);
OUT_REG(ring, A6XX_RB_BLEND_RED_F32(bcolor->color[0]),
A6XX_RB_BLEND_GREEN_F32(bcolor->color[1]),
A6XX_RB_BLEND_BLUE_F32(bcolor->color[2]),
A6XX_RB_BLEND_ALPHA_F32(bcolor->color[3]));
OUT_REG(ring, A6XX_RB_BLEND_CONSTANT_RED_FP32(bcolor->color[0]),
A6XX_RB_BLEND_CONSTANT_GREEN_FP32(bcolor->color[1]),
A6XX_RB_BLEND_CONSTANT_BLUE_FP32(bcolor->color[2]),
A6XX_RB_BLEND_CONSTANT_ALPHA_FP32(bcolor->color[3]));
return ring;
}
@@ -385,18 +385,18 @@ build_sample_locations(struct fd6_emit *emit)
y = CLAMP(y, 0.0f, 0.9375f);
sample_locations |=
(A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(x) |
A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(y)) << i*8;
(A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_X(x) |
A6XX_RB_PROGRAMMABLE_MSAA_POS_0_SAMPLE_0_Y(y)) << i*8;
}
OUT_REG(ring, A6XX_GRAS_SAMPLE_CONFIG(.location_enable = true),
A6XX_GRAS_SAMPLE_LOCATION_0(.dword = sample_locations));
OUT_REG(ring, A6XX_GRAS_SC_MSAA_SAMPLE_POS_CNTL(.location_enable = true),
A6XX_GRAS_SC_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations));
OUT_REG(ring, A6XX_RB_SAMPLE_CONFIG(.location_enable = true),
A6XX_RB_SAMPLE_LOCATION_0(.dword = sample_locations));
OUT_REG(ring, A6XX_RB_MSAA_SAMPLE_POS_CNTL(.location_enable = true),
A6XX_RB_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations));
OUT_REG(ring, A6XX_SP_TP_SAMPLE_CONFIG(.location_enable = true),
A6XX_SP_TP_SAMPLE_LOCATION_0(.dword = sample_locations));
OUT_REG(ring, A6XX_TPL1_MSAA_SAMPLE_POS_CNTL(.location_enable = true),
A6XX_TPL1_PROGRAMMABLE_MSAA_POS_0(.dword = sample_locations));
return ring;
}
@@ -501,9 +501,9 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
if (dirty & FD_DIRTY_STENCIL_REF) {
struct pipe_stencil_ref *sr = &ctx->stencil_ref;
OUT_PKT4(ring, REG_A6XX_RB_STENCILREF, 1);
OUT_RING(ring, A6XX_RB_STENCILREF_REF(sr->ref_value[0]) |
A6XX_RB_STENCILREF_BFREF(sr->ref_value[1]));
OUT_PKT4(ring, REG_A6XX_RB_STENCIL_REF_CNTL, 1);
OUT_RING(ring, A6XX_RB_STENCIL_REF_CNTL_REF(sr->ref_value[0]) |
A6XX_RB_STENCIL_REF_CNTL_BFREF(sr->ref_value[1]));
}
if (dirty & (FD_DIRTY_VIEWPORT | FD_DIRTY_PROG)) {
@@ -511,12 +511,12 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
struct pipe_scissor_state *scissor = &ctx->viewport_scissor[i];
struct pipe_viewport_state *vp = & ctx->viewport[i];
OUT_REG(ring, A6XX_GRAS_CL_VPORT_XOFFSET(i, vp->translate[0]),
A6XX_GRAS_CL_VPORT_XSCALE(i, vp->scale[0]),
A6XX_GRAS_CL_VPORT_YOFFSET(i, vp->translate[1]),
A6XX_GRAS_CL_VPORT_YSCALE(i, vp->scale[1]),
A6XX_GRAS_CL_VPORT_ZOFFSET(i, vp->translate[2]),
A6XX_GRAS_CL_VPORT_ZSCALE(i, vp->scale[2]));
OUT_REG(ring, A6XX_GRAS_CL_VIEWPORT_XOFFSET(i, vp->translate[0]),
A6XX_GRAS_CL_VIEWPORT_XSCALE(i, vp->scale[0]),
A6XX_GRAS_CL_VIEWPORT_YOFFSET(i, vp->translate[1]),
A6XX_GRAS_CL_VIEWPORT_YSCALE(i, vp->scale[1]),
A6XX_GRAS_CL_VIEWPORT_ZOFFSET(i, vp->translate[2]),
A6XX_GRAS_CL_VIEWPORT_ZSCALE(i, vp->scale[2]));
OUT_REG(
ring,
@@ -544,12 +544,12 @@ fd6_emit_non_ring(struct fd_ringbuffer *ring, struct fd6_emit *emit) assert_dt
util_viewport_zmin_zmax(vp, ctx->rasterizer->clip_halfz,
&zmin, &zmax);
OUT_REG(ring, A6XX_GRAS_CL_Z_CLAMP_MIN(i, zmin),
A6XX_GRAS_CL_Z_CLAMP_MAX(i, zmax));
OUT_REG(ring, A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MIN(i, zmin),
A6XX_GRAS_CL_VIEWPORT_ZCLAMP_MAX(i, zmax));
/* TODO: what to do about this and multi viewport ? */
if (i == 0)
OUT_REG(ring, A6XX_RB_Z_CLAMP_MIN(zmin), A6XX_RB_Z_CLAMP_MAX(zmax));
OUT_REG(ring, A6XX_RB_VIEWPORT_ZCLAMP_MIN(zmin), A6XX_RB_VIEWPORT_ZCLAMP_MAX(zmax));
}
}
}
@@ -804,7 +804,7 @@ fd6_emit_ccu_cntl(struct fd_ringbuffer *ring, struct fd_screen *screen, bool gme
if (CHIP == A7XX) {
OUT_REG(ring,
A7XX_RB_CCU_CNTL2(
A7XX_RB_CCU_CACHE_CNTL(
.depth_offset_hi = depth_offset_hi,
.color_offset_hi = color_offset_hi,
.depth_cache_size = CCU_CACHE_SIZE_FULL,
@@ -816,11 +816,11 @@ fd6_emit_ccu_cntl(struct fd_ringbuffer *ring, struct fd_screen *screen, bool gme
if (screen->info->a7xx.has_gmem_vpc_attr_buf) {
OUT_REG(ring,
A7XX_VPC_ATTR_BUF_SIZE_GMEM(.size_gmem = cfg->vpc_attr_buf_size),
A7XX_VPC_ATTR_BUF_BASE_GMEM(.base_gmem = cfg->vpc_attr_buf_offset)
A7XX_VPC_ATTR_BUF_GMEM_SIZE(.size_gmem = cfg->vpc_attr_buf_size),
A7XX_VPC_ATTR_BUF_GMEM_BASE(.base_gmem = cfg->vpc_attr_buf_offset)
);
OUT_REG(ring,
A7XX_PC_ATTR_BUF_SIZE_GMEM(.size_gmem = cfg->vpc_attr_buf_size)
A7XX_PC_ATTR_BUF_GMEM_SIZE(.size_gmem = cfg->vpc_attr_buf_size)
);
}
} else {
@@ -865,7 +865,7 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
if (CHIP >= A7XX) {
/* On A7XX, RB_CCU_CNTL was broken into two registers, RB_CCU_CNTL which has
* static properties that can be set once, this requires a WFI to take effect.
* While the newly introduced register RB_CCU_CNTL2 has properties that may
* While the newly introduced register RB_CCU_CACHE_CNTL has properties that may
* change per-RP and don't require a WFI to take effect, only CCU inval/flush
* events are required.
*/
@@ -897,9 +897,9 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
}
WRITE(REG_A6XX_RB_DBG_ECO_CNTL, screen->info->a6xx.magic.RB_DBG_ECO_CNTL);
WRITE(REG_A6XX_SP_FLOAT_CNTL, A6XX_SP_FLOAT_CNTL_F16_NO_INF);
WRITE(REG_A6XX_SP_NC_MODE_CNTL_2, A6XX_SP_NC_MODE_CNTL_2_F16_NO_INF);
WRITE(REG_A6XX_SP_DBG_ECO_CNTL, screen->info->a6xx.magic.SP_DBG_ECO_CNTL);
WRITE(REG_A6XX_SP_PERFCTR_ENABLE, 0x3f);
WRITE(REG_A6XX_SP_PERFCTR_SHADER_MASK, 0x3f);
if (CHIP == A6XX && !screen->info->a6xx.is_a702)
WRITE(REG_A6XX_TPL1_UNKNOWN_B605, 0x44);
WRITE(REG_A6XX_TPL1_DBG_ECO_CNTL, screen->info->a6xx.magic.TPL1_DBG_ECO_CNTL);
@@ -913,7 +913,7 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
if (CHIP == A6XX)
WRITE(REG_A6XX_HLSQ_DBG_ECO_CNTL, screen->info->a6xx.magic.HLSQ_DBG_ECO_CNTL);
WRITE(REG_A6XX_SP_CHICKEN_BITS, screen->info->a6xx.magic.SP_CHICKEN_BITS);
WRITE(REG_A6XX_SP_UAV_COUNT, 0);
WRITE(REG_A6XX_SP_GFX_USIZE, 0);
WRITE(REG_A6XX_SP_UNKNOWN_B182, 0);
if (CHIP == A6XX)
WRITE(REG_A6XX_HLSQ_SHARED_CONSTS, 0);
@@ -922,19 +922,19 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
WRITE(REG_A6XX_RB_UNKNOWN_8E01, screen->info->a6xx.magic.RB_UNKNOWN_8E01);
WRITE(REG_A6XX_SP_UNKNOWN_A9A8, 0);
OUT_REG(ring,
A6XX_SP_MODE_CONTROL(
A6XX_SP_MODE_CNTL(
.constant_demotion_enable = true,
.isammode = ISAMMODE_GL,
.shared_consts_enable = false,
)
);
OUT_REG(ring, A6XX_VFD_ADD_OFFSET(.vertex = true, .instance = true));
OUT_REG(ring, A6XX_VFD_MODE_CNTL(.vertex = true, .instance = true));
WRITE(REG_A6XX_VPC_UNKNOWN_9107, 0);
WRITE(REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
WRITE(REG_A6XX_PC_MODE_CNTL, screen->info->a6xx.magic.PC_MODE_CNTL);
WRITE(REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 0);
WRITE(REG_A6XX_GRAS_SAMPLE_CNTL, 0);
WRITE(REG_A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL, 0);
WRITE(REG_A6XX_GRAS_UNKNOWN_8110, 0x2);
WRITE(REG_A6XX_RB_UNKNOWN_8818, 0);
@@ -950,22 +950,22 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
WRITE(REG_A6XX_RB_UNKNOWN_88F0, 0);
WRITE(REG_A6XX_VPC_POINT_COORD_INVERT, A6XX_VPC_POINT_COORD_INVERT(0).value);
WRITE(REG_A6XX_VPC_REPLACE_MODE_CNTL, A6XX_VPC_REPLACE_MODE_CNTL(0).value);
WRITE(REG_A6XX_VPC_UNKNOWN_9300, 0);
WRITE(REG_A6XX_VPC_SO_DISABLE, A6XX_VPC_SO_DISABLE(true).value);
WRITE(REG_A6XX_VPC_SO_OVERRIDE, A6XX_VPC_SO_OVERRIDE(true).value);
OUT_REG(ring, PC_RASTER_CNTL(CHIP));
OUT_REG(ring, VPC_RAST_STREAM_CNTL(CHIP));
if (CHIP == A7XX)
OUT_REG(ring, A7XX_PC_RASTER_CNTL_V2());
OUT_REG(ring, A7XX_VPC_RAST_STREAM_CNTL_V2());
WRITE(REG_A6XX_PC_MULTIVIEW_CNTL, 0);
WRITE(REG_A6XX_PC_STEREO_RENDERING_CNTL, 0);
WRITE(REG_A6XX_SP_UNKNOWN_B183, 0);
WRITE(REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 0);
WRITE(REG_A6XX_GRAS_VS_LAYER_CNTL, 0);
WRITE(REG_A6XX_GRAS_SU_VS_SIV_CNTL, 0);
WRITE(REG_A6XX_GRAS_SC_CNTL, A6XX_GRAS_SC_CNTL_CCUSINGLECACHELINESIZE(2));
WRITE(REG_A6XX_GRAS_UNKNOWN_80AF, 0);
if (CHIP == A6XX) {
@@ -974,17 +974,17 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
}
WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
/* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_MODE_CNTL
/* NOTE blob seems to (mostly?) use 0xb2 for TPL1_MODE_CNTL
* but this seems to kill texture gather offsets.
*/
OUT_REG(ring,
A6XX_SP_TP_MODE_CNTL(
A6XX_TPL1_MODE_CNTL(
.isammode = ISAMMODE_GL,
.texcoordroundmode = COORD_TRUNCATE,
.nearestmipsnap = CLAMP_ROUND_TRUNCATE,
.destdatatypeoverride = true));
OUT_REG(ring, HLSQ_CONTROL_5_REG(
OUT_REG(ring, SP_REG_PROG_ID_3(
CHIP,
.linelengthregid = INVALID_REG,
.foveationqualityregid = INVALID_REG,
@@ -992,9 +992,9 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
emit_marker6(ring, 7);
OUT_REG(ring, A6XX_VFD_MODE_CNTL(RENDERING_PASS));
OUT_REG(ring, A6XX_VFD_RENDER_MODE(RENDERING_PASS));
WRITE(REG_A6XX_VFD_MULTIVIEW_CNTL, 0);
WRITE(REG_A6XX_VFD_STEREO_RENDERING_CNTL, 0);
/* Clear any potential pending state groups to be safe: */
OUT_PKT7(ring, CP_SET_DRAW_STATE, 3);
@@ -1004,8 +1004,8 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
OUT_RING(ring, CP_SET_DRAW_STATE__1_ADDR_LO(0));
OUT_RING(ring, CP_SET_DRAW_STATE__2_ADDR_HI(0));
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_CNTL, 1);
OUT_RING(ring, 0x00000000); /* VPC_SO_STREAM_CNTL */
OUT_PKT4(ring, REG_A6XX_VPC_SO_CNTL, 1);
OUT_RING(ring, 0x00000000); /* VPC_SO_CNTL */
if (CHIP >= A7XX) {
OUT_REG(ring, A6XX_GRAS_LRZ_CNTL());
@@ -1024,22 +1024,22 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
OUT_PKT4(ring, REG_A6XX_RB_LRZ_CNTL, 1);
OUT_RING(ring, 0x00000000);
/* Initialize VFD_FETCH[n].SIZE to zero to avoid iova faults trying
* to fetch from a VFD_FETCH[n].BASE which we've potentially inherited
/* Initialize VFD_VERTEX_BUFFER[n].SIZE to zero to avoid iova faults trying
* to fetch from a VFD_VERTEX_BUFFER[n].BASE which we've potentially inherited
* from another process:
*/
for (int32_t i = 0; i < 32; i++) {
OUT_PKT4(ring, REG_A6XX_VFD_FETCH_SIZE(i), 1);
OUT_PKT4(ring, REG_A6XX_VFD_VERTEX_BUFFER_SIZE(i), 1);
OUT_RING(ring, 0);
}
struct fd6_context *fd6_ctx = fd6_context(ctx);
struct fd_bo *bcolor_mem = fd6_ctx->bcolor_mem;
OUT_PKT4(ring, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR, 2);
OUT_PKT4(ring, REG_A6XX_TPL1_GFX_BORDER_COLOR_BASE, 2);
OUT_RELOC(ring, bcolor_mem, 0, 0, 0);
OUT_PKT4(ring, REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR, 2);
OUT_PKT4(ring, REG_A6XX_TPL1_CS_BORDER_COLOR_BASE, 2);
OUT_RELOC(ring, bcolor_mem, 0, 0, 0);
OUT_REG(ring, A6XX_PC_DGEN_SU_CONSERVATIVE_RAS_CNTL());
@@ -1057,12 +1057,12 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
if (CHIP >= A7XX) {
/* Blob sets these two per draw. */
OUT_REG(ring, A7XX_PC_TESS_PARAM_SIZE(FD6_TESS_PARAM_SIZE));
OUT_REG(ring, A7XX_PC_HS_BUFFER_SIZE(FD6_TESS_PARAM_SIZE));
/* Blob adds a bit more space ({0x10, 0x20, 0x30, 0x40} bytes)
* but the meaning of this additional space is not known,
* so we play safe and don't add it.
*/
OUT_REG(ring, A7XX_PC_TESS_FACTOR_SIZE(FD6_TESS_FACTOR_SIZE));
OUT_REG(ring, A7XX_PC_TF_BUFFER_SIZE(FD6_TESS_FACTOR_SIZE));
}
/* There is an optimization to skip executing draw states for draws with no
@@ -1070,18 +1070,18 @@ fd6_emit_static_regs(struct fd_context *ctx, struct fd_ringbuffer *ring)
* sets a bit in PC_DRAW_INITIATOR that seemingly skips the draw. However
* there is a hardware bug where this bit does not always cause the FS
* early preamble to be skipped. Because the draw states were skipped,
* SP_FS_CTRL_REG0, SP_FS_OBJ_START and so on are never updated and a
* SP_PS_CNTL_0, SP_PS_BASE and so on are never updated and a
* random FS preamble from the last draw is executed. If the last visible
* draw is from the same submit, it shouldn't be a problem because we just
* re-execute the same preamble and preambles don't have side effects, but
* if it's from another process then we could execute a garbage preamble
* leading to hangs and faults. To make sure this doesn't happen, we reset
* SP_FS_CTRL_REG0 here, making sure that the EARLYPREAMBLE bit isn't set
* SP_PS_CNTL_0 here, making sure that the EARLYPREAMBLE bit isn't set
* so any leftover early preamble doesn't get executed. Other stages don't
* seem to be affected.
*/
if (screen->info->a6xx.has_early_preamble) {
WRITE(REG_A6XX_SP_FS_CTRL_REG0, 0);
WRITE(REG_A6XX_SP_PS_CNTL_0, 0);
}
}
FD_GENX(fd6_emit_static_regs);
@@ -1126,7 +1126,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
}
OUT_REG(ring,
HLSQ_INVALIDATE_CMD(CHIP,
SP_UPDATE_CNTL(CHIP,
.vs_state = true, .hs_state = true,
.ds_state = true, .gs_state = true,
.fs_state = true, .cs_state = true,
src/gallium/drivers/freedreno/a6xx/fd6_gmem.cc
+134 -134
View File
@@ -34,8 +34,8 @@
#include "fd6_zsa.h"
/**
* Emits the flags registers, suitable for RB_MRT_FLAG_BUFFER,
* RB_DEPTH_FLAG_BUFFER, SP_PS_2D_SRC_FLAGS, and RB_BLIT_FLAG_DST.
* Emits the flags registers, suitable for RB_COLOR_FLAG_BUFFER,
* RB_DEPTH_FLAG_BUFFER, TPL1_A2D_SRC_TEXTURE_FLAG_BASE, and RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE.
*/
void
fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
@@ -44,13 +44,13 @@ fd6_emit_flag_reference(struct fd_ringbuffer *ring, struct fd_resource *rsc,
if (fd_resource_ubwc_enabled(rsc, level)) {
OUT_RELOC(ring, rsc->bo, fd_resource_ubwc_offset(rsc, level, layer), 0,
0);
OUT_RING(ring, A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(
OUT_RING(ring, A6XX_RB_COLOR_FLAG_BUFFER_PITCH_PITCH(
fdl_ubwc_pitch(&rsc->layout, level)) |
A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(
A6XX_RB_COLOR_FLAG_BUFFER_PITCH_ARRAY_PITCH(
rsc->layout.ubwc_layer_size >> 2));
} else {
OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_LO */
OUT_RING(ring, 0x00000000); /* RB_MRT_FLAG_BUFFER[i].ADDR_HI */
OUT_RING(ring, 0x00000000); /* RB_COLOR_FLAG_BUFFER[i].ADDR_LO */
OUT_RING(ring, 0x00000000); /* RB_COLOR_FLAG_BUFFER[i].ADDR_HI */
OUT_RING(ring, 0x00000000);
}
}
@@ -123,10 +123,10 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
A6XX_RB_MRT_BASE(i, .bo = rsc->bo, .bo_offset = offset),
A6XX_RB_MRT_BASE_GMEM(i, base));
OUT_REG(ring, A6XX_SP_FS_MRT_REG(i, .color_format = format,
OUT_REG(ring, A6XX_SP_PS_MRT_REG(i, .color_format = format,
.color_sint = sint, .color_uint = uint));
OUT_PKT4(ring, REG_A6XX_RB_MRT_FLAG_BUFFER(i), 3);
OUT_PKT4(ring, REG_A6XX_RB_COLOR_FLAG_BUFFER(i), 3);
fd6_emit_flag_reference(ring, rsc, psurf->level,
psurf->first_layer);
@@ -136,12 +136,12 @@ emit_mrt(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb,
if (pfb->zsbuf.texture)
max_layer_index = pfb->zsbuf.last_layer - pfb->zsbuf.first_layer;
OUT_REG(ring, A6XX_GRAS_LRZ_MRT_BUF_INFO_0(.color_format = mrt0_format));
OUT_REG(ring, A6XX_GRAS_LRZ_MRT_BUFFER_INFO_0(.color_format = mrt0_format));
OUT_REG(ring, A6XX_RB_SRGB_CNTL(.dword = srgb_cntl));
OUT_REG(ring, A6XX_SP_SRGB_CNTL(.dword = srgb_cntl));
OUT_REG(ring, A6XX_GRAS_MAX_LAYER_INDEX(max_layer_index));
OUT_REG(ring, A6XX_GRAS_CL_ARRAY_SIZE(max_layer_index));
}
template <chip CHIP>
@@ -177,7 +177,7 @@ emit_zs(struct fd_context *ctx, struct fd_ringbuffer *ring,
A6XX_RB_DEPTH_BUFFER_PITCH(0),
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
A6XX_RB_DEPTH_BUFFER_BASE(.qword = 0),
A6XX_RB_DEPTH_BUFFER_BASE_GMEM(base));
A6XX_RB_DEPTH_GMEM_BASE(base));
OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
@@ -194,7 +194,7 @@ emit_zs(struct fd_context *ctx, struct fd_ringbuffer *ring,
A6XX_RB_DEPTH_BUFFER_PITCH(stride),
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(array_stride),
A6XX_RB_DEPTH_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
A6XX_RB_DEPTH_BUFFER_BASE_GMEM(base));
A6XX_RB_DEPTH_GMEM_BASE(base));
OUT_REG(ring, A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = fmt));
@@ -213,7 +213,7 @@ emit_zs(struct fd_context *ctx, struct fd_ringbuffer *ring,
fd_ringbuffer_attach_bo(ring, stencil->bo);
OUT_REG(ring,
RB_STENCIL_INFO(
RB_STENCIL_BUFFER_INFO(
CHIP,
.separate_stencil = true,
.tilemode = TILE6_3,
@@ -221,10 +221,10 @@ emit_zs(struct fd_context *ctx, struct fd_ringbuffer *ring,
A6XX_RB_STENCIL_BUFFER_PITCH(stride),
A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(array_stride),
A6XX_RB_STENCIL_BUFFER_BASE(.bo = stencil->bo, .bo_offset = offset),
A6XX_RB_STENCIL_BUFFER_BASE_GMEM(base)
A6XX_RB_STENCIL_GMEM_BASE(base)
);
} else {
OUT_REG(ring, RB_STENCIL_INFO(CHIP, 0));
OUT_REG(ring, RB_STENCIL_BUFFER_INFO(CHIP, 0));
}
} else {
OUT_REG(ring,
@@ -235,13 +235,13 @@ emit_zs(struct fd_context *ctx, struct fd_ringbuffer *ring,
A6XX_RB_DEPTH_BUFFER_PITCH(),
A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(),
A6XX_RB_DEPTH_BUFFER_BASE(),
A6XX_RB_DEPTH_BUFFER_BASE_GMEM(),
A6XX_RB_DEPTH_GMEM_BASE(),
);
OUT_REG(ring,
A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format = DEPTH6_NONE));
OUT_REG(ring, RB_STENCIL_INFO(CHIP, 0));
OUT_REG(ring, RB_STENCIL_BUFFER_INFO(CHIP, 0));
}
}
@@ -569,7 +569,7 @@ update_vsc_pipe(struct fd_batch *batch)
* frame:
*/
fd6_ctx->vsc_draw_strm_pitch = align(batch->draw_strm_bits / 8, 0x4000);
mesa_logd("pre-resize VSC_DRAW_STRM_PITCH to: 0x%x",
mesa_logd("pre-resize to: 0x%x",
fd6_ctx->vsc_draw_strm_pitch);
}
@@ -584,8 +584,8 @@ update_vsc_pipe(struct fd_batch *batch)
if (!fd6_ctx->vsc_draw_strm) {
/* We also use four bytes per vsc pipe at the end of the draw
* stream buffer for VSC_DRAW_STRM_SIZE written back by hw
* (see VSC_DRAW_STRM_SIZE_ADDRESS)
* stream buffer for VSC_PIPE_DATA_DRAW_SIZE written back by hw
* (see VSC_SIZE_BASE)
*/
unsigned sz = (max_vsc_pipes * fd6_ctx->vsc_draw_strm_pitch) +
(max_vsc_pipes * 4);
@@ -603,11 +603,11 @@ update_vsc_pipe(struct fd_batch *batch)
fd_ringbuffer_attach_bo(ring, fd6_ctx->vsc_prim_strm);
OUT_REG(ring, A6XX_VSC_BIN_SIZE(.width = gmem->bin_w, .height = gmem->bin_h),
A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo = fd6_ctx->vsc_draw_strm,
.bo_offset = max_vsc_pipes *
fd6_ctx->vsc_draw_strm_pitch));
A6XX_VSC_SIZE_BASE(.bo = fd6_ctx->vsc_draw_strm,
.bo_offset = max_vsc_pipes *
fd6_ctx->vsc_draw_strm_pitch));
OUT_REG(ring, A6XX_VSC_BIN_COUNT(.nx = gmem->nbins_x, .ny = gmem->nbins_y));
OUT_REG(ring, A6XX_VSC_EXPANDED_BIN_CNTL(.nx = gmem->nbins_x, .ny = gmem->nbins_y));
OUT_PKT4(ring, REG_A6XX_VSC_PIPE_CONFIG_REG(0), max_vsc_pipes);
for (i = 0; i < max_vsc_pipes; i++) {
@@ -619,14 +619,14 @@ update_vsc_pipe(struct fd_batch *batch)
}
OUT_REG(
ring, A6XX_VSC_PRIM_STRM_ADDRESS(.bo = fd6_ctx->vsc_prim_strm),
A6XX_VSC_PRIM_STRM_PITCH(.dword = fd6_ctx->vsc_prim_strm_pitch),
A6XX_VSC_PRIM_STRM_LIMIT(.dword = fd6_ctx->vsc_prim_strm_pitch - 64));
ring, A6XX_VSC_PIPE_DATA_PRIM_BASE(.bo = fd6_ctx->vsc_prim_strm),
A6XX_VSC_PIPE_DATA_PRIM_STRIDE(.dword = fd6_ctx->vsc_prim_strm_pitch),
A6XX_VSC_PIPE_DATA_PRIM_LENGTH(.dword = fd6_ctx->vsc_prim_strm_pitch - 64));
OUT_REG(
ring, A6XX_VSC_DRAW_STRM_ADDRESS(.bo = fd6_ctx->vsc_draw_strm),
A6XX_VSC_DRAW_STRM_PITCH(.dword = fd6_ctx->vsc_draw_strm_pitch),
A6XX_VSC_DRAW_STRM_LIMIT(.dword = fd6_ctx->vsc_draw_strm_pitch - 64));
ring, A6XX_VSC_PIPE_DATA_DRAW_BASE(.bo = fd6_ctx->vsc_draw_strm),
A6XX_VSC_PIPE_DATA_DRAW_STRIDE(.dword = fd6_ctx->vsc_draw_strm_pitch),
A6XX_VSC_PIPE_DATA_DRAW_LENGTH(.dword = fd6_ctx->vsc_draw_strm_pitch - 64));
}
/*
@@ -654,7 +654,7 @@ emit_vsc_overflow_test(struct fd_batch *batch)
OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(
REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i)));
REG_A6XX_VSC_PIPE_DATA_DRAW_SIZE(i)));
OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_draw_strm_pitch - 64));
OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
@@ -667,7 +667,7 @@ emit_vsc_overflow_test(struct fd_batch *batch)
OUT_RING(ring, CP_COND_WRITE5_0_FUNCTION(WRITE_GE) |
CP_COND_WRITE5_0_WRITE_MEMORY);
OUT_RING(ring, CP_COND_WRITE5_1_POLL_ADDR_LO(
REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i)));
REG_A6XX_VSC_PIPE_DATA_PRIM_SIZE(i)));
OUT_RING(ring, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
OUT_RING(ring, CP_COND_WRITE5_3_REF(fd6_ctx->vsc_prim_strm_pitch - 64));
OUT_RING(ring, CP_COND_WRITE5_4_MASK(~0));
@@ -712,7 +712,7 @@ check_vsc_overflow(struct fd_context *ctx)
fd6_ctx->vsc_draw_strm = NULL;
fd6_ctx->vsc_draw_strm_pitch *= 2;
mesa_logd("resized VSC_DRAW_STRM_PITCH to: 0x%x",
mesa_logd("resized VSC_PIPE_DATA_DRAW_STRIDE to: 0x%x",
fd6_ctx->vsc_draw_strm_pitch);
} else if (buffer == 0x3) {
@@ -727,7 +727,7 @@ check_vsc_overflow(struct fd_context *ctx)
fd6_ctx->vsc_prim_strm = NULL;
fd6_ctx->vsc_prim_strm_pitch *= 2;
mesa_logd("resized VSC_PRIM_STRM_PITCH to: 0x%x",
mesa_logd("resized VSC_PIPE_DATA_PRIM_STRIDE to: 0x%x",
fd6_ctx->vsc_prim_strm_pitch);
} else {
@@ -755,11 +755,11 @@ emit_common_init(struct fd_batch *batch)
fd_ringbuffer_attach_bo(ring, at->results_mem);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_CNTL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNTER_CNTL_COPY);
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_BASE, 2);
OUT_RELOC(ring, results_ptr(at, result[result->idx].samples_start));
fd6_event_write<CHIP>(ctx, ring, FD_ZPASS_DONE);
@@ -797,11 +797,11 @@ emit_common_fini(struct fd_batch *batch)
fd_ringbuffer_attach_bo(ring, at->results_mem);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_CNTL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNTER_CNTL_COPY);
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_BASE, 2);
OUT_RELOC(ring, results_ptr(at, result[result->idx].samples_end));
fd6_event_write<CHIP>(batch->ctx, ring, FD_ZPASS_DONE);
@@ -823,8 +823,8 @@ emit_common_fini(struct fd_batch *batch)
}
/*
* Emit conditional CP_INDIRECT_BRANCH based on VSC_STATE[p], ie. the IB
* is skipped for tiles that have no visible geometry.
* Emit conditional CP_INDIRECT_BRANCH based on VSC_CHANNEL_VISIBILITY[p],
* ie. the IB is skipped for tiles that have no visible geometry.
*
* If we aren't using binning pass, this just emits a normal IB.
*/
@@ -853,7 +853,7 @@ emit_conditional_ib(struct fd_batch *batch, const struct fd_tile *tile,
BEGIN_RING(ring, 5 + 4 * count); /* ensure conditional doesn't get split */
OUT_PKT7(ring, CP_REG_TEST, 1);
OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_STATE_REG(tile->p)) |
OUT_RING(ring, A6XX_CP_REG_TEST_0_REG(REG_A6XX_VSC_CHANNEL_VISIBILITY(tile->p)) |
A6XX_CP_REG_TEST_0_BIT(tile->n) |
A6XX_CP_REG_TEST_0_SKIP_WAIT_FOR_ME);
@@ -879,8 +879,8 @@ set_scissor(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1, uint32_t x2,
OUT_REG(ring, A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x = x1, .y = y1),
A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x = x2, .y = y2));
OUT_REG(ring, A6XX_GRAS_2D_RESOLVE_CNTL_1(.x = x1, .y = y1),
A6XX_GRAS_2D_RESOLVE_CNTL_2(.x = x2, .y = y2));
OUT_REG(ring, A6XX_GRAS_A2D_SCISSOR_TL(.x = x1, .y = y1),
A6XX_GRAS_A2D_SCISSOR_BR(.x = x2, .y = y2));
}
template <chip CHIP>
@@ -897,8 +897,8 @@ set_tessfactor_bo(struct fd_ringbuffer *ring, struct fd_batch *batch)
assert(screen->tess_bo);
fd_ringbuffer_attach_bo(ring, screen->tess_bo);
OUT_REG(ring, PC_TESSFACTOR_ADDR(CHIP, screen->tess_bo));
/* Updating PC_TESSFACTOR_ADDR could race with the next draw which uses it. */
OUT_REG(ring, PC_TESS_BASE(CHIP, screen->tess_bo));
/* Updating PC_TESS_BASE could race with the next draw which uses it. */
OUT_WFI5(ring);
}
@@ -918,7 +918,7 @@ set_bin_size(struct fd_ringbuffer *ring, const struct fd_gmem_stateobj *gmem,
unsigned h = gmem ? gmem->bin_h : 0;
if (CHIP == A6XX) {
OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(
OUT_REG(ring, A6XX_GRAS_SC_BIN_CNTL(
.binw = w, .binh = h,
.render_mode = p.render_mode,
.force_lrz_write_dis = p.force_lrz_write_dis,
@@ -926,14 +926,14 @@ set_bin_size(struct fd_ringbuffer *ring, const struct fd_gmem_stateobj *gmem,
.lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask,
));
} else {
OUT_REG(ring, A6XX_GRAS_BIN_CONTROL(
OUT_REG(ring, A6XX_GRAS_SC_BIN_CNTL(
.binw = w, .binh = h,
.render_mode = p.render_mode,
.force_lrz_write_dis = p.force_lrz_write_dis,
.lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask,
));
}
OUT_REG(ring, RB_BIN_CONTROL(
OUT_REG(ring, RB_CNTL(
CHIP,
.binw = w, .binh = h,
.render_mode = p.render_mode,
@@ -941,8 +941,8 @@ set_bin_size(struct fd_ringbuffer *ring, const struct fd_gmem_stateobj *gmem,
.buffers_location = p.buffers_location,
.lrz_feedback_zmode_mask = p.lrz_feedback_zmode_mask,
));
/* no flag for RB_BIN_CONTROL2... */
OUT_REG(ring, A6XX_RB_BIN_CONTROL2(.binw = w, .binh = h));
/* no flag for RB_RESOLVE_CNTL_3... */
OUT_REG(ring, A6XX_RB_RESOLVE_CNTL_3(.binw = w, .binh = h));
}
template <chip CHIP>
@@ -970,7 +970,7 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
OUT_WFI5(ring);
OUT_REG(ring, A6XX_VFD_MODE_CNTL(.render_mode = BINNING_PASS));
OUT_REG(ring, A6XX_VFD_RENDER_MODE(.render_mode = BINNING_PASS));
update_vsc_pipe(batch);
@@ -985,9 +985,9 @@ emit_binning_pass(struct fd_batch *batch) assert_dt
OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(0) | A6XX_RB_WINDOW_OFFSET_Y(0));
OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
OUT_PKT4(ring, REG_A6XX_TPL1_WINDOW_OFFSET, 1);
OUT_RING(ring,
A6XX_SP_TP_WINDOW_OFFSET_X(0) | A6XX_SP_TP_WINDOW_OFFSET_Y(0));
A6XX_TPL1_WINDOW_OFFSET_X(0) | A6XX_TPL1_WINDOW_OFFSET_Y(0));
/* emit IB to binning drawcmds: */
trace_start_binning_ib(&batch->trace, ring);
@@ -1038,17 +1038,17 @@ emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
{
enum a3xx_msaa_samples samples = fd_msaa_samples(nr);
OUT_PKT4(ring, REG_A6XX_SP_TP_RAS_MSAA_CNTL, 2);
OUT_RING(ring, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples));
OUT_RING(ring, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples) |
OUT_PKT4(ring, REG_A6XX_TPL1_RAS_MSAA_CNTL, 2);
OUT_RING(ring, A6XX_TPL1_RAS_MSAA_CNTL_SAMPLES(samples));
OUT_RING(ring, A6XX_TPL1_DEST_MSAA_CNTL_SAMPLES(samples) |
COND(samples == MSAA_ONE,
A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE));
A6XX_TPL1_DEST_MSAA_CNTL_MSAA_DISABLE));
OUT_PKT4(ring, REG_A6XX_GRAS_RAS_MSAA_CNTL, 2);
OUT_RING(ring, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples));
OUT_RING(ring, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples) |
OUT_PKT4(ring, REG_A6XX_GRAS_SC_RAS_MSAA_CNTL, 2);
OUT_RING(ring, A6XX_GRAS_SC_RAS_MSAA_CNTL_SAMPLES(samples));
OUT_RING(ring, A6XX_GRAS_SC_DEST_MSAA_CNTL_SAMPLES(samples) |
COND(samples == MSAA_ONE,
A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE));
A6XX_GRAS_SC_DEST_MSAA_CNTL_MSAA_DISABLE));
OUT_PKT4(ring, REG_A6XX_RB_RAS_MSAA_CNTL, 2);
OUT_RING(ring, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples));
@@ -1056,8 +1056,8 @@ emit_msaa(struct fd_ringbuffer *ring, unsigned nr)
A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples) |
COND(samples == MSAA_ONE, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_GMEM_MSAA_CNTL, 1);
OUT_RING(ring, A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(samples));
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_GMEM_BUFFER_INFO, 1);
OUT_RING(ring, A6XX_RB_RESOLVE_GMEM_BUFFER_INFO_SAMPLES(samples));
}
template <chip CHIP>
@@ -1069,11 +1069,11 @@ static void
fd7_emit_static_binning_regs(struct fd_ringbuffer *ring)
{
OUT_REG(ring, A7XX_RB_UNKNOWN_8812(0x0));
OUT_REG(ring, A7XX_RB_UNKNOWN_8E06(0x0));
OUT_REG(ring, A7XX_RB_CCU_DBG_ECO_CNTL(0x0));
OUT_REG(ring, A7XX_GRAS_UNKNOWN_8007(0x0));
OUT_REG(ring, A6XX_GRAS_UNKNOWN_8110(0x2));
OUT_REG(ring, A7XX_RB_UNKNOWN_8E09(0x4));
OUT_REG(ring, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_GMEM));
OUT_REG(ring, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
}
template <chip CHIP>
@@ -1099,7 +1099,7 @@ fd6_build_preemption_preamble(struct fd_context *ctx)
* manually restore this state.
*/
OUT_PKT7(ring, CP_MEM_TO_REG, 3);
OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VSC_STATE(0)) |
OUT_RING(ring, CP_MEM_TO_REG_0_REG(REG_A6XX_VSC_CHANNEL_VISIBILITY(0)) |
CP_MEM_TO_REG_0_CNT(32));
OUT_RELOC(ring, control_ptr(fd6_context(ctx), vsc_state));
@@ -1153,7 +1153,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
if (use_hw_binning(batch)) {
/* enable stream-out during binning pass: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
OUT_REG(ring, A6XX_VPC_SO_OVERRIDE(false));
set_bin_size<CHIP>(ring, gmem, {
.render_mode = BINNING_PASS,
@@ -1164,7 +1164,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
emit_binning_pass<CHIP>(batch);
/* and disable stream-out for draw pass: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(true));
OUT_REG(ring, A6XX_VPC_SO_OVERRIDE(true));
/*
* NOTE: even if we detect VSC overflow and disable use of
@@ -1181,7 +1181,7 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
: LRZ_FEEDBACK_NONE,
});
OUT_REG(ring, A6XX_VFD_MODE_CNTL(RENDERING_PASS));
OUT_REG(ring, A6XX_VFD_RENDER_MODE(RENDERING_PASS));
if (CHIP == A6XX) {
OUT_REG(ring, A6XX_PC_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
@@ -1195,12 +1195,12 @@ fd6_emit_tile_init(struct fd_batch *batch) assert_dt
* preemption.
*/
OUT_PKT7(ring, CP_REG_TO_MEM, 3);
OUT_RING(ring, CP_REG_TO_MEM_0_REG(REG_A6XX_VSC_STATE_REG(0)) |
OUT_RING(ring, CP_REG_TO_MEM_0_REG(REG_A6XX_VSC_CHANNEL_VISIBILITY(0)) |
CP_REG_TO_MEM_0_CNT(32));
OUT_RELOC(ring, control_ptr(fd6_context(batch->ctx), vsc_state));
} else {
/* no binning pass, so enable stream-out for draw pass:: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
OUT_REG(ring, A6XX_VPC_SO_OVERRIDE(false));
set_bin_size<CHIP>(ring, gmem, {
.render_mode = RENDERING_PASS,
@@ -1225,14 +1225,14 @@ set_window_offset(struct fd_ringbuffer *ring, uint32_t x1, uint32_t y1)
OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET, 1);
OUT_RING(ring, A6XX_RB_WINDOW_OFFSET_X(x1) | A6XX_RB_WINDOW_OFFSET_Y(y1));
OUT_PKT4(ring, REG_A6XX_RB_WINDOW_OFFSET2, 1);
OUT_RING(ring, A6XX_RB_WINDOW_OFFSET2_X(x1) | A6XX_RB_WINDOW_OFFSET2_Y(y1));
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_WINDOW_OFFSET, 1);
OUT_RING(ring, A6XX_RB_RESOLVE_WINDOW_OFFSET_X(x1) | A6XX_RB_RESOLVE_WINDOW_OFFSET_Y(y1));
OUT_REG(ring, SP_WINDOW_OFFSET(CHIP, .x = x1, .y = y1));
OUT_PKT4(ring, REG_A6XX_SP_TP_WINDOW_OFFSET, 1);
OUT_PKT4(ring, REG_A6XX_TPL1_WINDOW_OFFSET, 1);
OUT_RING(ring,
A6XX_SP_TP_WINDOW_OFFSET_X(x1) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1));
A6XX_TPL1_WINDOW_OFFSET_X(x1) | A6XX_TPL1_WINDOW_OFFSET_Y(y1));
}
/* before mem2gmem */
@@ -1283,7 +1283,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
OUT_RELOC(ring, fd6_ctx->vsc_draw_strm, /* per-pipe draw-stream address */
(tile->p * fd6_ctx->vsc_draw_strm_pitch), 0, 0);
OUT_RELOC(
ring, fd6_ctx->vsc_draw_strm, /* VSC_DRAW_STRM_ADDRESS + (p * 4) */
ring, fd6_ctx->vsc_draw_strm, /* VSC_PIPE_DATA_DRAW_BASE + (p * 4) */
(tile->p * 4) + (num_vsc_pipes * fd6_ctx->vsc_draw_strm_pitch),
0, 0);
OUT_RELOC(ring, fd6_ctx->vsc_prim_strm,
@@ -1293,7 +1293,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
OUT_RING(ring, 0x0);
/* and disable stream-out for draw pass: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(true));
OUT_REG(ring, A6XX_VPC_SO_OVERRIDE(true));
/*
* NOTE: even if we detect VSC overflow and disable use of
@@ -1310,7 +1310,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
: LRZ_FEEDBACK_NONE,
});
OUT_REG(ring, A6XX_VFD_MODE_CNTL(RENDERING_PASS));
OUT_REG(ring, A6XX_VFD_RENDER_MODE(RENDERING_PASS));
if (CHIP == A6XX) {
OUT_REG(ring, A6XX_PC_POWER_CNTL(screen->info->a6xx.magic.PC_POWER_CNTL));
@@ -1325,7 +1325,7 @@ fd6_emit_tile_prep(struct fd_batch *batch, const struct fd_tile *tile)
OUT_RING(ring, 0x1);
/* no binning pass, so enable stream-out for draw pass:: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
OUT_REG(ring, A6XX_VPC_SO_OVERRIDE(false));
set_bin_size<CHIP>(ring, gmem, {
.render_mode = RENDERING_PASS,
@@ -1365,11 +1365,11 @@ set_blit_scissor(struct fd_batch *batch, struct fd_ringbuffer *ring)
blit_scissor.maxx = ALIGN(pfb->width, 16);
blit_scissor.maxy = ALIGN(pfb->height, 4);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_SCISSOR_TL, 2);
OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_TL_X(blit_scissor.minx) |
A6XX_RB_BLIT_SCISSOR_TL_Y(blit_scissor.miny));
OUT_RING(ring, A6XX_RB_BLIT_SCISSOR_BR_X(blit_scissor.maxx - 1) |
A6XX_RB_BLIT_SCISSOR_BR_Y(blit_scissor.maxy - 1));
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_1, 2);
OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_1_X(blit_scissor.minx) |
A6XX_RB_RESOLVE_CNTL_1_Y(blit_scissor.miny));
OUT_RING(ring, A6XX_RB_RESOLVE_CNTL_2_X(blit_scissor.maxx - 1) |
A6XX_RB_RESOLVE_CNTL_2_Y(blit_scissor.maxy - 1));
}
template <chip CHIP>
@@ -1407,27 +1407,27 @@ emit_blit(struct fd_batch *batch, struct fd_ringbuffer *ring, uint32_t base,
enum a3xx_msaa_samples samples = fd_msaa_samples(rsc->b.b.nr_samples);
OUT_REG(ring,
A6XX_RB_BLIT_DST_INFO(
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO(
.tile_mode = tile_mode,
.flags = ubwc_enabled,
.samples = samples,
.color_swap = swap,
.color_format = format,
),
A6XX_RB_BLIT_DST(.bo = rsc->bo, .bo_offset = offset),
A6XX_RB_BLIT_DST_PITCH(stride),
A6XX_RB_BLIT_DST_ARRAY_PITCH(array_stride));
A6XX_RB_RESOLVE_SYSTEM_BUFFER_BASE(.bo = rsc->bo, .bo_offset = offset),
A6XX_RB_RESOLVE_SYSTEM_BUFFER_PITCH(stride),
A6XX_RB_RESOLVE_SYSTEM_BUFFER_ARRAY_PITCH(array_stride));
OUT_REG(ring, A6XX_RB_BLIT_BASE_GMEM(.dword = base));
OUT_REG(ring, A6XX_RB_RESOLVE_GMEM_BUFFER_BASE(.dword = base));
if (ubwc_enabled) {
OUT_PKT4(ring, REG_A6XX_RB_BLIT_FLAG_DST, 3);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_SYSTEM_FLAG_BUFFER_BASE, 3);
fd6_emit_flag_reference(ring, rsc, psurf->level,
psurf->first_layer);
}
if (CHIP >= A7XX)
OUT_REG(ring, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_GMEM));
OUT_REG(ring, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
fd6_emit_blit<CHIP>(batch->ctx, ring);
}
@@ -1440,7 +1440,7 @@ emit_restore_blit(struct fd_batch *batch, struct fd_ringbuffer *ring,
bool stencil = (buffer == FD_BUFFER_STENCIL);
OUT_REG(ring,
A6XX_RB_BLIT_INFO(
A6XX_RB_RESOLVE_OPERATION(
.type = BLIT_EVENT_LOAD,
.sample_0 = util_format_is_pure_integer(psurf->format),
.depth = (buffer == FD_BUFFER_DEPTH),
@@ -1506,30 +1506,30 @@ emit_subpass_clears(struct fd_batch *batch, struct fd_batch_subpass *subpass)
util_pack_color_union(pfmt, &uc, &swapped);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO, 1);
OUT_RING(ring,
A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_color_format(pfmt, TILE6_LINEAR)));
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_SAMPLES(samples) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_FORMAT(fd6_color_format(pfmt, TILE6_LINEAR)));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_CLEAR) |
A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_OPERATION, 1);
OUT_RING(ring, A6XX_RB_RESOLVE_OPERATION_TYPE(BLIT_EVENT_CLEAR) |
A6XX_RB_RESOLVE_OPERATION_CLEAR_MASK(0xf));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_GMEM_BUFFER_BASE, 1);
OUT_RING(ring, gmem->cbuf_base[i]);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_0, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 4);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 4);
OUT_RING(ring, uc.ui[0]);
OUT_RING(ring, uc.ui[1]);
OUT_RING(ring, uc.ui[2]);
OUT_RING(ring, uc.ui[3]);
if (CHIP >= A7XX)
OUT_REG(ring, A7XX_RB_BLIT_CLEAR_MODE(.clear_mode = CLEAR_MODE_GMEM));
OUT_REG(ring, A7XX_RB_CLEAR_TARGET(.clear_mode = CLEAR_MODE_GMEM));
fd6_emit_blit<CHIP>(batch->ctx, ring);
}
@@ -1561,24 +1561,24 @@ emit_subpass_clears(struct fd_batch *batch, struct fd_batch_subpass *subpass)
if (!has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL))
mask |= 0x2;
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO, 1);
OUT_RING(ring,
A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(fd6_color_format(pfmt, TILE6_LINEAR)));
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_SAMPLES(samples) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_FORMAT(fd6_color_format(pfmt, TILE6_LINEAR)));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_CLEAR) |
A6XX_RB_BLIT_INFO_DEPTH |
A6XX_RB_BLIT_INFO_CLEAR_MASK(mask));
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_OPERATION, 1);
OUT_RING(ring, A6XX_RB_RESOLVE_OPERATION_TYPE(BLIT_EVENT_CLEAR) |
A6XX_RB_RESOLVE_OPERATION_DEPTH |
A6XX_RB_RESOLVE_OPERATION_CLEAR_MASK(mask));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_GMEM_BUFFER_BASE, 1);
OUT_RING(ring, gmem->zsbuf_base[0]);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_0, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 1);
OUT_RING(ring, clear_value);
fd6_emit_blit<CHIP>(batch->ctx, ring);
@@ -1587,23 +1587,23 @@ emit_subpass_clears(struct fd_batch *batch, struct fd_batch_subpass *subpass)
/* Then clear the separate stencil buffer in case of 32 bit depth
* formats with separate stencil. */
if (has_separate_stencil && (buffers & PIPE_CLEAR_STENCIL)) {
OUT_PKT4(ring, REG_A6XX_RB_BLIT_DST_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_BLIT_DST_INFO_SAMPLES(samples) |
A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(FMT6_8_UINT));
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO, 1);
OUT_RING(ring, A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_TILE_MODE(TILE6_LINEAR) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_SAMPLES(samples) |
A6XX_RB_RESOLVE_SYSTEM_BUFFER_INFO_COLOR_FORMAT(FMT6_8_UINT));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_RING(ring, A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_CLEAR) |
A6XX_RB_BLIT_INFO_DEPTH |
A6XX_RB_BLIT_INFO_CLEAR_MASK(0x1));
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_OPERATION, 1);
OUT_RING(ring, A6XX_RB_RESOLVE_OPERATION_TYPE(BLIT_EVENT_CLEAR) |
A6XX_RB_RESOLVE_OPERATION_DEPTH |
A6XX_RB_RESOLVE_OPERATION_CLEAR_MASK(0x1));
OUT_PKT4(ring, REG_A6XX_RB_BLIT_BASE_GMEM, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_GMEM_BUFFER_BASE, 1);
OUT_RING(ring, gmem->zsbuf_base[1]);
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_88D0, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CNTL_0, 1);
OUT_RING(ring, 0);
OUT_PKT4(ring, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_CLEAR_COLOR_DW0, 1);
OUT_RING(ring, subpass->clear_stencil & 0xff);
fd6_emit_blit<CHIP>(batch->ctx, ring);
@@ -1781,22 +1781,22 @@ emit_resolve_blit(struct fd_batch *batch, struct fd_ringbuffer *ring,
switch (buffer) {
case FD_BUFFER_COLOR:
info = A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_STORE);
info = A6XX_RB_RESOLVE_OPERATION_TYPE(BLIT_EVENT_STORE);
break;
case FD_BUFFER_STENCIL:
info = A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_STORE_AND_CLEAR);
info = A6XX_RB_RESOLVE_OPERATION_TYPE(BLIT_EVENT_STORE_AND_CLEAR);
stencil = true;
break;
case FD_BUFFER_DEPTH:
info = A6XX_RB_BLIT_INFO_TYPE(BLIT_EVENT_STORE) | A6XX_RB_BLIT_INFO_DEPTH;
info = A6XX_RB_RESOLVE_OPERATION_TYPE(BLIT_EVENT_STORE) | A6XX_RB_RESOLVE_OPERATION_DEPTH;
break;
}
if (util_format_is_pure_integer(psurf->format) ||
util_format_is_depth_or_stencil(psurf->format))
info |= A6XX_RB_BLIT_INFO_SAMPLE_0;
info |= A6XX_RB_RESOLVE_OPERATION_SAMPLE_0;
OUT_PKT4(ring, REG_A6XX_RB_BLIT_INFO, 1);
OUT_PKT4(ring, REG_A6XX_RB_RESOLVE_OPERATION, 1);
OUT_RING(ring, info);
emit_blit<CHIP>(batch, ring, base, psurf, stencil);
@@ -2032,7 +2032,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
if (CHIP >= A7XX) {
OUT_REG(ring, A7XX_RB_UNKNOWN_8812(0x3ff)); // all buffers in sysmem
OUT_REG(ring, A7XX_RB_UNKNOWN_8E06(batch->ctx->screen->info->a6xx.magic.RB_UNKNOWN_8E06));
OUT_REG(ring, A7XX_RB_CCU_DBG_ECO_CNTL(batch->ctx->screen->info->a6xx.magic.RB_CCU_DBG_ECO_CNTL));
OUT_REG(ring, A7XX_GRAS_UNKNOWN_8007(0x0));
OUT_REG(ring, A6XX_GRAS_UNKNOWN_8110(0x2));
OUT_REG(ring, A7XX_RB_UNKNOWN_8E09(0x4));
@@ -2051,7 +2051,7 @@ fd6_emit_sysmem_prep(struct fd_batch *batch) assert_dt
OUT_RING(ring, 0x1);
/* enable stream-out, with sysmem there is only one pass: */
OUT_REG(ring, A6XX_VPC_SO_DISABLE(false));
OUT_REG(ring, A6XX_VPC_SO_OVERRIDE(false));
OUT_PKT7(ring, CP_SET_VISIBILITY_OVERRIDE, 1);
OUT_RING(ring, 0x1);
src/gallium/drivers/freedreno/a6xx/fd6_image.cc
+3 -3
View File
@@ -271,7 +271,7 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
if (shader == PIPE_SHADER_COMPUTE) {
OUT_REG(ring,
HLSQ_INVALIDATE_CMD(
SP_UPDATE_CNTL(
CHIP,
.cs_bindless = CHIP == A6XX ? 0x1f : 0xff,
)
@@ -321,12 +321,12 @@ fd6_build_bindless_state(struct fd_context *ctx, enum pipe_shader_type shader,
}
} else {
OUT_REG(ring,
HLSQ_INVALIDATE_CMD(
SP_UPDATE_CNTL(
CHIP,
.gfx_bindless = CHIP == A6XX ? 0x1f : 0xff,
)
);
OUT_REG(ring, SP_BINDLESS_BASE_DESCRIPTOR(CHIP,
OUT_REG(ring, SP_GFX_BINDLESS_BASE_DESCRIPTOR(CHIP,
idx, .desc_size = BINDLESS_DESCRIPTOR_64B, .bo = set->bo,
));
if (CHIP == A6XX) {
src/gallium/drivers/freedreno/a6xx/fd6_program.cc
+231 -231
View File
@@ -54,46 +54,46 @@ struct xs_config {
template <chip CHIP>
static const struct xs_config<CHIP> xs_configs[] = {
[MESA_SHADER_VERTEX] = {
REG_A6XX_SP_VS_INSTRLEN,
CHIP == A6XX ? REG_A6XX_HLSQ_VS_CNTL : REG_A7XX_HLSQ_VS_CNTL,
REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_VS_VGPR_CONFIG,
REG_A6XX_SP_VS_INSTR_SIZE,
CHIP == A6XX ? REG_A6XX_SP_VS_CONST_CONFIG : REG_A7XX_SP_VS_CONST_CONFIG,
REG_A6XX_SP_VS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_VS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_VS_VGS_CNTL,
},
[MESA_SHADER_TESS_CTRL] = {
REG_A6XX_SP_HS_INSTRLEN,
CHIP == A6XX ? REG_A6XX_HLSQ_HS_CNTL : REG_A7XX_HLSQ_HS_CNTL,
REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_HS_VGPR_CONFIG,
REG_A6XX_SP_HS_INSTR_SIZE,
CHIP == A6XX ? REG_A6XX_SP_HS_CONST_CONFIG : REG_A7XX_SP_HS_CONST_CONFIG,
REG_A6XX_SP_HS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_HS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_HS_VGS_CNTL,
},
[MESA_SHADER_TESS_EVAL] = {
REG_A6XX_SP_DS_INSTRLEN,
CHIP == A6XX ? REG_A6XX_HLSQ_DS_CNTL : REG_A7XX_HLSQ_DS_CNTL,
REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_DS_VGPR_CONFIG,
REG_A6XX_SP_DS_INSTR_SIZE,
CHIP == A6XX ? REG_A6XX_SP_DS_CONST_CONFIG : REG_A7XX_SP_DS_CONST_CONFIG,
REG_A6XX_SP_DS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_DS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_DS_VGS_CNTL,
},
[MESA_SHADER_GEOMETRY] = {
REG_A6XX_SP_GS_INSTRLEN,
CHIP == A6XX ? REG_A6XX_HLSQ_GS_CNTL : REG_A7XX_HLSQ_GS_CNTL,
REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_GS_VGPR_CONFIG,
REG_A6XX_SP_GS_INSTR_SIZE,
CHIP == A6XX ? REG_A6XX_SP_GS_CONST_CONFIG : REG_A7XX_SP_GS_CONST_CONFIG,
REG_A6XX_SP_GS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_GS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_GS_VGS_CNTL,
},
[MESA_SHADER_FRAGMENT] = {
REG_A6XX_SP_FS_INSTRLEN,
CHIP == A6XX ? REG_A6XX_HLSQ_FS_CNTL : REG_A7XX_HLSQ_FS_CNTL,
REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_FS_VGPR_CONFIG,
REG_A6XX_SP_PS_INSTR_SIZE,
CHIP == A6XX ? REG_A6XX_SP_PS_CONST_CONFIG : REG_A7XX_SP_PS_CONST_CONFIG,
REG_A6XX_SP_PS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_PS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_PS_VGS_CNTL,
},
[MESA_SHADER_COMPUTE] = {
REG_A6XX_SP_CS_INSTRLEN,
CHIP == A6XX ? REG_A6XX_HLSQ_CS_CNTL : REG_A7XX_HLSQ_CS_CNTL,
REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET,
REG_A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET,
REG_A7XX_SP_CS_VGPR_CONFIG,
REG_A6XX_SP_CS_INSTR_SIZE,
CHIP == A6XX ? REG_A6XX_SP_CS_CONST_CONFIG : REG_A7XX_SP_CS_CONST_CONFIG,
REG_A6XX_SP_CS_PROGRAM_COUNTER_OFFSET,
REG_A6XX_SP_CS_PVT_MEM_STACK_OFFSET,
REG_A7XX_SP_CS_VGS_CNTL,
},
};
@@ -123,7 +123,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
switch (type) {
case MESA_SHADER_VERTEX:
OUT_REG(ring, A6XX_SP_VS_CTRL_REG0(
OUT_REG(ring, A6XX_SP_VS_CNTL_0(
.halfregfootprint = so->info.max_half_reg + 1,
.fullregfootprint = so->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(so),
@@ -132,7 +132,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
));
break;
case MESA_SHADER_TESS_CTRL:
OUT_REG(ring, A6XX_SP_HS_CTRL_REG0(
OUT_REG(ring, A6XX_SP_HS_CNTL_0(
.halfregfootprint = so->info.max_half_reg + 1,
.fullregfootprint = so->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(so),
@@ -140,7 +140,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
));
break;
case MESA_SHADER_TESS_EVAL:
OUT_REG(ring, A6XX_SP_DS_CTRL_REG0(
OUT_REG(ring, A6XX_SP_DS_CNTL_0(
.halfregfootprint = so->info.max_half_reg + 1,
.fullregfootprint = so->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(so),
@@ -148,7 +148,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
));
break;
case MESA_SHADER_GEOMETRY:
OUT_REG(ring, A6XX_SP_GS_CTRL_REG0(
OUT_REG(ring, A6XX_SP_GS_CNTL_0(
.halfregfootprint = so->info.max_half_reg + 1,
.fullregfootprint = so->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(so),
@@ -156,7 +156,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
));
break;
case MESA_SHADER_FRAGMENT:
OUT_REG(ring, A6XX_SP_FS_CTRL_REG0(
OUT_REG(ring, A6XX_SP_PS_CNTL_0(
.halfregfootprint = so->info.max_half_reg + 1,
.fullregfootprint = so->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(so),
@@ -171,7 +171,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
break;
case MESA_SHADER_COMPUTE:
thrsz = ctx->screen->info->a6xx.supports_double_threadsize ? thrsz : THREAD128;
OUT_REG(ring, A6XX_SP_CS_CTRL_REG0(
OUT_REG(ring, A6XX_SP_CS_CNTL_0(
.halfregfootprint = so->info.max_half_reg + 1,
.fullregfootprint = so->info.max_reg + 1,
.branchstack = ir3_shader_branchstack_hw(so),
@@ -214,7 +214,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT));
OUT_PKT4(ring, cfg->reg_sp_xs_pvt_mem_hw_stack_offset, 1);
OUT_RING(ring, A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(per_sp_size));
OUT_RING(ring, A6XX_SP_VS_PVT_MEM_STACK_OFFSET_OFFSET(per_sp_size));
if (CHIP >= A7XX) {
OUT_PKT4(ring, cfg->reg_sp_xs_vgpr_config, 1);
@@ -255,13 +255,13 @@ setup_stream_out_disable(struct fd_context *ctx)
fd_ringbuffer_new_object(ctx->pipe, (1 + sizedw) * 4);
OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, sizedw);
OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
OUT_RING(ring, REG_A6XX_VPC_SO_MAPPING_WPTR);
OUT_RING(ring, 0);
OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL);
OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
OUT_RING(ring, 0);
if (ctx->screen->info->a6xx.tess_use_shared) {
OUT_RING(ring, REG_A6XX_PC_SO_STREAM_CNTL);
OUT_RING(ring, REG_A6XX_PC_DGEN_SO_CNTL);
OUT_RING(ring, 0);
}
@@ -305,13 +305,13 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
unsigned dword = out->stream * A6XX_SO_PROG_DWORDS + loc/2;
if (loc & 1) {
prog[dword] |= A6XX_VPC_SO_PROG_B_EN |
A6XX_VPC_SO_PROG_B_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_B_OFF(off * 4);
prog[dword] |= A6XX_VPC_SO_MAPPING_PORT_B_EN |
A6XX_VPC_SO_MAPPING_PORT_B_BUF(out->output_buffer) |
A6XX_VPC_SO_MAPPING_PORT_B_OFF(off * 4);
} else {
prog[dword] |= A6XX_VPC_SO_PROG_A_EN |
A6XX_VPC_SO_PROG_A_BUF(out->output_buffer) |
A6XX_VPC_SO_PROG_A_OFF(off * 4);
prog[dword] |= A6XX_VPC_SO_MAPPING_PORT_A_EN |
A6XX_VPC_SO_MAPPING_PORT_A_BUF(out->output_buffer) |
A6XX_VPC_SO_MAPPING_PORT_A_OFF(off * 4);
}
BITSET_SET(valid_dwords, dword);
}
@@ -336,17 +336,17 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
fd_ringbuffer_new_object(ctx->pipe, (1 + sizedw) * 4);
OUT_PKT7(ring, CP_CONTEXT_REG_BUNCH, sizedw);
OUT_RING(ring, REG_A6XX_VPC_SO_STREAM_CNTL);
OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
OUT_RING(ring,
A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(strmout->streams_written) |
A6XX_VPC_SO_CNTL_STREAM_ENABLE(strmout->streams_written) |
COND(strmout->stride[0] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF0_STREAM(1 + strmout->output[0].stream)) |
A6XX_VPC_SO_CNTL_BUF0_STREAM(1 + strmout->output[0].stream)) |
COND(strmout->stride[1] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF1_STREAM(1 + strmout->output[1].stream)) |
A6XX_VPC_SO_CNTL_BUF1_STREAM(1 + strmout->output[1].stream)) |
COND(strmout->stride[2] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF2_STREAM(1 + strmout->output[2].stream)) |
A6XX_VPC_SO_CNTL_BUF2_STREAM(1 + strmout->output[2].stream)) |
COND(strmout->stride[3] > 0,
A6XX_VPC_SO_STREAM_CNTL_BUF3_STREAM(1 + strmout->output[3].stream)));
A6XX_VPC_SO_CNTL_BUF3_STREAM(1 + strmout->output[3].stream)));
OUT_RING(ring, REG_A6XX_VPC_SO_BUFFER_STRIDE(0));
OUT_RING(ring, strmout->stride[0]);
OUT_RING(ring, REG_A6XX_VPC_SO_BUFFER_STRIDE(1));
@@ -359,11 +359,11 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
bool first = true;
BITSET_FOREACH_RANGE (start, end, valid_dwords,
A6XX_SO_PROG_DWORDS * IR3_MAX_SO_STREAMS) {
OUT_RING(ring, REG_A6XX_VPC_SO_CNTL);
OUT_RING(ring, COND(first, A6XX_VPC_SO_CNTL_RESET) |
A6XX_VPC_SO_CNTL_ADDR(start));
OUT_RING(ring, REG_A6XX_VPC_SO_MAPPING_WPTR);
OUT_RING(ring, COND(first, A6XX_VPC_SO_MAPPING_WPTR_RESET) |
A6XX_VPC_SO_MAPPING_WPTR_ADDR(start));
for (unsigned i = start; i < end; i++) {
OUT_RING(ring, REG_A6XX_VPC_SO_PROG);
OUT_RING(ring, REG_A6XX_VPC_SO_MAPPING_PORT);
OUT_RING(ring, prog[i]);
}
first = false;
@@ -373,8 +373,8 @@ setup_stream_out(struct fd_context *ctx, struct fd6_program_state *state,
/* Possibly not tess_use_shared related, but the combination of
* tess + xfb fails some tests if we don't emit this.
*/
OUT_RING(ring, REG_A6XX_PC_SO_STREAM_CNTL);
OUT_RING(ring, A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE(0x1));
OUT_RING(ring, REG_A6XX_PC_DGEN_SO_CNTL);
OUT_RING(ring, A6XX_PC_DGEN_SO_CNTL_STREAM_ENABLE(0x1));
}
state->streamout_stateobj = ring;
@@ -402,34 +402,34 @@ setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
{
struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 100 * 4);
OUT_REG(ring, HLSQ_INVALIDATE_CMD(CHIP, .vs_state = true, .hs_state = true,
OUT_REG(ring, SP_UPDATE_CNTL(CHIP, .vs_state = true, .hs_state = true,
.ds_state = true, .gs_state = true,
.fs_state = true, .cs_state = true,
.cs_uav = true, .gfx_uav = true, ));
assert(state->vs->constlen >= state->bs->constlen);
OUT_REG(ring, HLSQ_VS_CNTL(
OUT_REG(ring, SP_VS_CONST_CONFIG(
CHIP,
.constlen = state->vs->constlen,
.enabled = true,
));
OUT_REG(ring, HLSQ_HS_CNTL(
OUT_REG(ring, SP_HS_CONST_CONFIG(
CHIP,
.constlen = COND(state->hs, state->hs->constlen),
.enabled = COND(state->hs, true),
));
OUT_REG(ring, HLSQ_DS_CNTL(
OUT_REG(ring, SP_DS_CONST_CONFIG(
CHIP,
.constlen = COND(state->ds, state->ds->constlen),
.enabled = COND(state->ds, true),
));
OUT_REG(ring, HLSQ_GS_CNTL(
OUT_REG(ring, SP_GS_CONST_CONFIG(
CHIP,
.constlen = COND(state->gs, state->gs->constlen),
.enabled = COND(state->gs, true),
));
OUT_REG(ring, HLSQ_FS_CNTL(
OUT_REG(ring, SP_PS_CONST_CONFIG(
CHIP,
.constlen = state->fs->constlen,
.enabled = true,
@@ -447,10 +447,10 @@ setup_config_stateobj(struct fd_context *ctx, struct fd6_program_state *state)
OUT_PKT4(ring, REG_A6XX_SP_GS_CONFIG, 1);
OUT_RING(ring, sp_xs_config(state->gs));
OUT_PKT4(ring, REG_A6XX_SP_FS_CONFIG, 1);
OUT_PKT4(ring, REG_A6XX_SP_PS_CONFIG, 1);
OUT_RING(ring, sp_xs_config(state->fs));
OUT_PKT4(ring, REG_A6XX_SP_UAV_COUNT, 1);
OUT_PKT4(ring, REG_A6XX_SP_GFX_USIZE, 1);
OUT_RING(ring, ir3_shader_num_uavs(state->fs));
state->config_stateobj = ring;
@@ -491,7 +491,7 @@ emit_vfd_dest(struct fd_ringbuffer *ring, const struct ir3_shader_variant *vs)
if (!vs->inputs[i].sysval)
attr_count++;
OUT_REG(ring, A6XX_VFD_CONTROL_0(
OUT_REG(ring, A6XX_VFD_CNTL_0(
.fetch_cnt = attr_count, /* decode_cnt for binning pass ? */
.decode_cnt = attr_count));
@@ -537,21 +537,21 @@ emit_vs_system_values(struct fd_ringbuffer *ring,
*/
const uint32_t viewid_regid = INVALID_REG;
OUT_PKT4(ring, REG_A6XX_VFD_CONTROL_1, 6);
OUT_RING(ring, A6XX_VFD_CONTROL_1_REGID4VTX(vertexid_regid) |
A6XX_VFD_CONTROL_1_REGID4INST(instanceid_regid) |
A6XX_VFD_CONTROL_1_REGID4PRIMID(vs_primitiveid_regid) |
A6XX_VFD_CONTROL_1_REGID4VIEWID(viewid_regid));
OUT_RING(ring, A6XX_VFD_CONTROL_2_REGID_HSRELPATCHID(hs_rel_patch_regid) |
A6XX_VFD_CONTROL_2_REGID_INVOCATIONID(hs_invocation_regid));
OUT_RING(ring, A6XX_VFD_CONTROL_3_REGID_DSRELPATCHID(ds_rel_patch_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSX(tess_coord_x_regid) |
A6XX_VFD_CONTROL_3_REGID_TESSY(tess_coord_y_regid) |
A6XX_VFD_CONTROL_3_REGID_DSPRIMID(ds_primitiveid_regid));
OUT_RING(ring, 0x000000fc); /* VFD_CONTROL_4 */
OUT_RING(ring, A6XX_VFD_CONTROL_5_REGID_GSHEADER(gsheader_regid) |
0xfc00); /* VFD_CONTROL_5 */
OUT_RING(ring, COND(b->fs->reads_primid, A6XX_VFD_CONTROL_6_PRIMID4PSEN)); /* VFD_CONTROL_6 */
OUT_PKT4(ring, REG_A6XX_VFD_CNTL_1, 6);
OUT_RING(ring, A6XX_VFD_CNTL_1_REGID4VTX(vertexid_regid) |
A6XX_VFD_CNTL_1_REGID4INST(instanceid_regid) |
A6XX_VFD_CNTL_1_REGID4PRIMID(vs_primitiveid_regid) |
A6XX_VFD_CNTL_1_REGID4VIEWID(viewid_regid));
OUT_RING(ring, A6XX_VFD_CNTL_2_REGID_HSRELPATCHID(hs_rel_patch_regid) |
A6XX_VFD_CNTL_2_REGID_INVOCATIONID(hs_invocation_regid));
OUT_RING(ring, A6XX_VFD_CNTL_3_REGID_DSRELPATCHID(ds_rel_patch_regid) |
A6XX_VFD_CNTL_3_REGID_TESSX(tess_coord_x_regid) |
A6XX_VFD_CNTL_3_REGID_TESSY(tess_coord_y_regid) |
A6XX_VFD_CNTL_3_REGID_DSPRIMID(ds_primitiveid_regid));
OUT_RING(ring, 0x000000fc); /* VFD_CNTL_4 */
OUT_RING(ring, A6XX_VFD_CNTL_5_REGID_GSHEADER(gsheader_regid) |
0xfc00); /* VFD_CNTL_5 */
OUT_RING(ring, COND(b->fs->reads_primid, A6XX_VFD_CNTL_6_PRIMID4PSEN)); /* VFD_CNTL_6 */
}
template <chip CHIP>
@@ -575,17 +575,17 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
uint16_t reg_gras_xs_layer_cntl;
} reg_config[] = {
[MESA_SHADER_VERTEX] = {
REG_A6XX_SP_VS_OUT_REG(0),
REG_A6XX_SP_VS_VPC_DST_REG(0),
REG_A6XX_VPC_VS_PACK,
REG_A6XX_VPC_VS_CLIP_CNTL,
REG_A6XX_VPC_VS_CLIP_CNTL_V2,
REG_A6XX_GRAS_VS_CL_CNTL,
REG_A6XX_PC_VS_OUT_CNTL,
REG_A6XX_SP_VS_PRIMITIVE_CNTL,
REG_A6XX_VPC_VS_LAYER_CNTL,
REG_A6XX_VPC_VS_LAYER_CNTL_V2,
REG_A6XX_GRAS_VS_LAYER_CNTL
REG_A6XX_SP_VS_OUTPUT_REG(0),
REG_A6XX_SP_VS_VPC_DEST_REG(0),
REG_A6XX_VPC_VS_CNTL,
REG_A6XX_VPC_VS_CLIP_CULL_CNTL,
REG_A6XX_VPC_VS_CLIP_CULL_CNTL_V2,
REG_A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE,
REG_A6XX_PC_VS_CNTL,
REG_A6XX_SP_VS_OUTPUT_CNTL,
REG_A6XX_VPC_VS_SIV_CNTL,
REG_A6XX_VPC_VS_SIV_CNTL_V2,
REG_A6XX_GRAS_SU_VS_SIV_CNTL,
},
[MESA_SHADER_TESS_CTRL] = {
0,
@@ -594,37 +594,37 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
0,
0,
0,
REG_A6XX_PC_HS_OUT_CNTL,
REG_A6XX_PC_HS_CNTL,
0,
0,
0,
0
},
[MESA_SHADER_TESS_EVAL] = {
REG_A6XX_SP_DS_OUT_REG(0),
REG_A6XX_SP_DS_VPC_DST_REG(0),
REG_A6XX_VPC_DS_PACK,
REG_A6XX_VPC_DS_CLIP_CNTL,
REG_A6XX_VPC_DS_CLIP_CNTL_V2,
REG_A6XX_GRAS_DS_CL_CNTL,
REG_A6XX_PC_DS_OUT_CNTL,
REG_A6XX_SP_DS_PRIMITIVE_CNTL,
REG_A6XX_VPC_DS_LAYER_CNTL,
REG_A6XX_VPC_DS_LAYER_CNTL_V2,
REG_A6XX_GRAS_DS_LAYER_CNTL
REG_A6XX_SP_DS_OUTPUT_REG(0),
REG_A6XX_SP_DS_VPC_DEST_REG(0),
REG_A6XX_VPC_DS_CNTL,
REG_A6XX_VPC_DS_CLIP_CULL_CNTL,
REG_A6XX_VPC_DS_CLIP_CULL_CNTL_V2,
REG_A6XX_GRAS_CL_DS_CLIP_CULL_DISTANCE,
REG_A6XX_PC_DS_CNTL,
REG_A6XX_SP_DS_OUTPUT_CNTL,
REG_A6XX_VPC_DS_SIV_CNTL,
REG_A6XX_VPC_DS_SIV_CNTL_V2,
REG_A6XX_GRAS_SU_DS_SIV_CNTL,
},
[MESA_SHADER_GEOMETRY] = {
REG_A6XX_SP_GS_OUT_REG(0),
REG_A6XX_SP_GS_VPC_DST_REG(0),
REG_A6XX_VPC_GS_PACK,
REG_A6XX_VPC_GS_CLIP_CNTL,
REG_A6XX_VPC_GS_CLIP_CNTL_V2,
REG_A6XX_GRAS_GS_CL_CNTL,
REG_A6XX_PC_GS_OUT_CNTL,
REG_A6XX_SP_GS_PRIMITIVE_CNTL,
REG_A6XX_VPC_GS_LAYER_CNTL,
REG_A6XX_VPC_GS_LAYER_CNTL_V2,
REG_A6XX_GRAS_GS_LAYER_CNTL
REG_A6XX_SP_GS_OUTPUT_REG(0),
REG_A6XX_SP_GS_VPC_DEST_REG(0),
REG_A6XX_VPC_GS_CNTL,
REG_A6XX_VPC_GS_CLIP_CULL_CNTL,
REG_A6XX_VPC_GS_CLIP_CULL_CNTL_V2,
REG_A6XX_GRAS_CL_GS_CLIP_CULL_DISTANCE,
REG_A6XX_PC_GS_CNTL,
REG_A6XX_SP_GS_OUTPUT_CNTL,
REG_A6XX_VPC_GS_SIV_CNTL,
REG_A6XX_VPC_GS_SIV_CNTL_V2,
REG_A6XX_GRAS_SU_GS_SIV_CNTL,
},
};
const struct reg_config *cfg = &reg_config[b->last_shader->type];
@@ -652,7 +652,7 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
emit_vs_system_values(ring, b);
OUT_PKT4(ring, REG_A6XX_VPC_VAR_DISABLE(0), 4);
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_LM_TRANSFER_CNTL_0_DISABLE(0), 4);
OUT_RING(ring, ~linkage.varmask[0]);
OUT_RING(ring, ~linkage.varmask[1]);
OUT_RING(ring, ~linkage.varmask[2]);
@@ -755,10 +755,10 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
uint8_t sp_vpc_dst[32] = {0};
for (uint32_t i = 0; i < linkage.cnt; i++) {
sp_out[i] =
A6XX_SP_VS_OUT_REG_A_REGID(linkage.var[i].regid) |
A6XX_SP_VS_OUT_REG_A_COMPMASK(linkage.var[i].compmask);
A6XX_SP_VS_OUTPUT_REG_A_REGID(linkage.var[i].regid) |
A6XX_SP_VS_OUTPUT_REG_A_COMPMASK(linkage.var[i].compmask);
sp_vpc_dst[i] =
A6XX_SP_VS_VPC_DST_REG_OUTLOC0(linkage.var[i].loc);
A6XX_SP_VS_VPC_DEST_REG_OUTLOC0(linkage.var[i].loc);
}
OUT_PKT4(ring, cfg->reg_sp_xs_out_reg, sp_out_count);
@@ -768,23 +768,23 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
OUT_BUF(ring, sp_vpc_dst, sp_vpc_dst_count);
OUT_PKT4(ring, cfg->reg_vpc_xs_pack, 1);
OUT_RING(ring, A6XX_VPC_VS_PACK_POSITIONLOC(position_loc) |
A6XX_VPC_VS_PACK_PSIZELOC(pointsize_loc) |
A6XX_VPC_VS_PACK_STRIDE_IN_VPC(linkage.max_loc));
OUT_RING(ring, A6XX_VPC_VS_CNTL_POSITIONLOC(position_loc) |
A6XX_VPC_VS_CNTL_PSIZELOC(pointsize_loc) |
A6XX_VPC_VS_CNTL_STRIDE_IN_VPC(linkage.max_loc));
OUT_PKT4(ring, cfg->reg_vpc_xs_clip_cntl, 1);
OUT_RING(ring, A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
OUT_RING(ring, A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC(clip1_loc));
OUT_PKT4(ring, cfg->reg_vpc_xs_clip_cntl_v2, 1);
OUT_RING(ring, A6XX_VPC_VS_CLIP_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CNTL_CLIP_DIST_47_LOC(clip1_loc));
OUT_RING(ring, A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_MASK(clip_cull_mask) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_03_LOC(clip0_loc) |
A6XX_VPC_VS_CLIP_CULL_CNTL_CLIP_DIST_47_LOC(clip1_loc));
OUT_PKT4(ring, cfg->reg_gras_xs_cl_cntl, 1);
OUT_RING(ring, A6XX_GRAS_VS_CL_CNTL_CLIP_MASK(clip_mask) |
A6XX_GRAS_VS_CL_CNTL_CULL_MASK(cull_mask));
OUT_RING(ring, A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CLIP_MASK(clip_mask) |
A6XX_GRAS_CL_VS_CLIP_CULL_DISTANCE_CULL_MASK(cull_mask));
const struct ir3_shader_variant *geom_stages[] = { b->vs, b->hs, b->ds, b->gs };
@@ -798,15 +798,15 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
OUT_PKT4(ring, reg_config[shader->type].reg_pc_xs_out_cntl, 1);
if (shader == last_shader) {
OUT_RING(ring, A6XX_PC_VS_OUT_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
CONDREG(pointsize_regid, A6XX_PC_VS_OUT_CNTL_PSIZE) |
CONDREG(layer_regid, A6XX_PC_VS_OUT_CNTL_LAYER) |
CONDREG(view_regid, A6XX_PC_VS_OUT_CNTL_VIEW) |
COND(primid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID) |
COND(primid, A6XX_PC_GS_OUT_CNTL_PRIMITIVE_ID) |
A6XX_PC_VS_OUT_CNTL_CLIP_MASK(clip_cull_mask));
OUT_RING(ring, A6XX_PC_VS_CNTL_STRIDE_IN_VPC(linkage.max_loc) |
CONDREG(pointsize_regid, A6XX_PC_VS_CNTL_PSIZE) |
CONDREG(layer_regid, A6XX_PC_VS_CNTL_LAYER) |
CONDREG(view_regid, A6XX_PC_VS_CNTL_VIEW) |
COND(primid, A6XX_PC_VS_CNTL_PRIMITIVE_ID) |
COND(primid, A6XX_PC_GS_CNTL_PRIMITIVE_ID) |
A6XX_PC_VS_CNTL_CLIP_MASK(clip_cull_mask));
} else {
OUT_RING(ring, COND(primid, A6XX_PC_VS_OUT_CNTL_PRIMITIVE_ID));
OUT_RING(ring, COND(primid, A6XX_PC_VS_CNTL_PRIMITIVE_ID));
}
}
@@ -814,38 +814,38 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
assert(flags_regid != INVALID_REG);
OUT_PKT4(ring, cfg->reg_sp_xs_primitive_cntl, 1);
OUT_RING(ring, A6XX_SP_VS_PRIMITIVE_CNTL_OUT(linkage.cnt) |
A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(flags_regid));
OUT_RING(ring, A6XX_SP_VS_OUTPUT_CNTL_OUT(linkage.cnt) |
A6XX_SP_GS_OUTPUT_CNTL_FLAGS_REGID(flags_regid));
OUT_PKT4(ring, cfg->reg_vpc_xs_layer_cntl, 1);
OUT_RING(ring, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(0xff));
OUT_RING(ring, A6XX_VPC_VS_SIV_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_SIV_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_SIV_CNTL_SHADINGRATELOC(0xff));
OUT_PKT4(ring, cfg->reg_vpc_xs_layer_cntl_v2, 1);
OUT_RING(ring, A6XX_VPC_VS_LAYER_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(0xff));
OUT_RING(ring, A6XX_VPC_VS_SIV_CNTL_LAYERLOC(layer_loc) |
A6XX_VPC_VS_SIV_CNTL_VIEWLOC(view_loc) |
A6XX_VPC_VS_SIV_CNTL_SHADINGRATELOC(0xff));
OUT_PKT4(ring, cfg->reg_gras_xs_layer_cntl, 1);
OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_LAYER) |
CONDREG(view_regid, A6XX_GRAS_GS_LAYER_CNTL_WRITES_VIEW));
OUT_RING(ring, CONDREG(layer_regid, A6XX_GRAS_SU_VS_SIV_CNTL_WRITES_LAYER) |
CONDREG(view_regid, A6XX_GRAS_SU_VS_SIV_CNTL_WRITES_VIEW));
OUT_REG(ring, A6XX_PC_PS_CNTL(b->fs->reads_primid));
if (CHIP >= A7XX) {
OUT_REG(ring, A6XX_GRAS_UNKNOWN_8110(0x2));
OUT_REG(ring, A7XX_HLSQ_FS_UNKNOWN_A9AA(.fs_disable = false));
OUT_REG(ring, A7XX_SP_RENDER_CNTL(.fs_disable = false));
}
OUT_PKT4(ring, REG_A6XX_VPC_CNTL_0, 1);
OUT_RING(ring, A6XX_VPC_CNTL_0_NUMNONPOSVAR(b->fs->total_in) |
COND(b->fs->total_in, A6XX_VPC_CNTL_0_VARYING) |
A6XX_VPC_CNTL_0_PRIMIDLOC(linkage.primid_loc) |
A6XX_VPC_CNTL_0_VIEWIDLOC(linkage.viewid_loc));
OUT_PKT4(ring, REG_A6XX_VPC_PS_CNTL, 1);
OUT_RING(ring, A6XX_VPC_PS_CNTL_NUMNONPOSVAR(b->fs->total_in) |
COND(b->fs->total_in, A6XX_VPC_PS_CNTL_VARYING) |
A6XX_VPC_PS_CNTL_PRIMIDLOC(linkage.primid_loc) |
A6XX_VPC_PS_CNTL_VIEWIDLOC(linkage.viewid_loc));
if (b->hs) {
OUT_PKT4(ring, REG_A6XX_PC_TESS_NUM_VERTEX, 1);
OUT_PKT4(ring, REG_A6XX_PC_HS_PARAM_0, 1);
OUT_RING(ring, b->hs->tess.tcs_vertices_out);
fd6_emit_link_map<CHIP>(b->ctx, b->vs, b->hs, ring);
@@ -871,15 +871,15 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
vec4_size = b->gs->gs.vertices_in *
DIV_ROUND_UP(prev_stage_output_size, 4);
OUT_PKT4(ring, REG_A6XX_PC_PRIMITIVE_CNTL_5, 1);
OUT_PKT4(ring, REG_A6XX_PC_GS_PARAM_0, 1);
OUT_RING(ring,
A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(vertices_out) |
A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(output) |
A6XX_PC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(invocations));
A6XX_PC_GS_PARAM_0_GS_VERTICES_OUT(vertices_out) |
A6XX_PC_GS_PARAM_0_GS_OUTPUT(output) |
A6XX_PC_GS_PARAM_0_GS_INVOCATIONS(invocations));
if (CHIP >= A7XX) {
OUT_REG(ring,
A7XX_VPC_PRIMITIVE_CNTL_5(
A7XX_VPC_GS_PARAM_0(
.gs_vertices_out = vertices_out,
.gs_invocations = invocations,
.gs_output = output,
@@ -901,7 +901,7 @@ emit_vpc(struct fd_ringbuffer *ring, const struct program_builder *b)
else if (prim_size == 64)
prim_size = 63;
OUT_PKT4(ring, REG_A6XX_SP_GS_PRIM_SIZE, 1);
OUT_PKT4(ring, REG_A6XX_SP_GS_CNTL_1, 1);
OUT_RING(ring, prim_size);
}
}
@@ -943,20 +943,20 @@ emit_fs_inputs(struct fd_ringbuffer *ring, const struct program_builder *b)
ij_regid[fs->prefetch_bary_type] == regid(0, 0));
}
OUT_PKT4(ring, REG_A6XX_SP_FS_PREFETCH_CNTL, 1 + fs->num_sampler_prefetch);
OUT_RING(ring, A6XX_SP_FS_PREFETCH_CNTL_COUNT(fs->num_sampler_prefetch) |
COND(CHIP >= A7XX, A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(0x1ff)) |
COND(CHIP >= A7XX, A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(0x1ff)) |
OUT_PKT4(ring, REG_A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL, 1 + fs->num_sampler_prefetch);
OUT_RING(ring, A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_COUNT(fs->num_sampler_prefetch) |
COND(CHIP >= A7XX, A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID(0x1ff)) |
COND(CHIP >= A7XX, A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_CONSTSLOTID4COORD(0x1ff)) |
COND(!VALIDREG(ij_regid[IJ_PERSP_PIXEL]),
A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE) |
A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_IJ_WRITE_DISABLE) |
COND(fs->prefetch_end_of_quad,
A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD));
A6XX_SP_PS_INITIAL_TEX_LOAD_CNTL_ENDOFQUAD));
for (int i = 0; i < fs->num_sampler_prefetch; i++) {
const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
OUT_RING(ring, SP_FS_PREFETCH_CMD(
OUT_RING(ring, SP_PS_INITIAL_TEX_LOAD_CMD(
CHIP, i,
.src = prefetch->src,
/* For a7xx, samp_id/tex_id is always in SP_FS_BINDLESS_PREFETCH_CMD[n]
/* For a7xx, samp_id/tex_id is always in SP_PS_INITIAL_TEX_INDEX_CMD[n]
* even in the non-bindless case (which probably makes the reg name
* wrong)
*/
@@ -975,7 +975,7 @@ emit_fs_inputs(struct fd_ringbuffer *ring, const struct program_builder *b)
for (int i = 0; i < fs->num_sampler_prefetch; i++) {
const struct ir3_sampler_prefetch *prefetch = &fs->sampler_prefetch[i];
OUT_REG(ring,
A6XX_SP_FS_BINDLESS_PREFETCH_CMD(i,
A6XX_SP_PS_INITIAL_TEX_INDEX_CMD(i,
.samp_id = prefetch->samp_id,
.tex_id = prefetch->tex_id,
)
@@ -984,30 +984,30 @@ emit_fs_inputs(struct fd_ringbuffer *ring, const struct program_builder *b)
}
OUT_REG(ring,
HLSQ_CONTROL_1_REG(CHIP,
SP_LB_PARAM_LIMIT(CHIP,
b->ctx->screen->info->a6xx.prim_alloc_threshold),
HLSQ_CONTROL_2_REG(
SP_REG_PROG_ID_0(
CHIP,
.faceregid = face_regid,
.sampleid = samp_id_regid,
.samplemask = smask_in_regid,
.centerrhw = ij_regid[IJ_PERSP_CENTER_RHW],
),
HLSQ_CONTROL_3_REG(
SP_REG_PROG_ID_1(
CHIP,
.ij_persp_pixel = ij_regid[IJ_PERSP_PIXEL],
.ij_linear_pixel = ij_regid[IJ_LINEAR_PIXEL],
.ij_persp_centroid = ij_regid[IJ_PERSP_CENTROID],
.ij_linear_centroid = ij_regid[IJ_LINEAR_CENTROID],
),
HLSQ_CONTROL_4_REG(
SP_REG_PROG_ID_2(
CHIP,
.ij_persp_sample = ij_regid[IJ_PERSP_SAMPLE],
.ij_linear_sample = ij_regid[IJ_LINEAR_SAMPLE],
.xycoordregid = coord_regid,
.zwcoordregid = zwcoord_regid,
),
HLSQ_CONTROL_5_REG(
SP_REG_PROG_ID_3(
CHIP,
.linelengthregid = INVALID_REG,
.foveationqualityregid = INVALID_REG,
@@ -1036,7 +1036,7 @@ emit_fs_inputs(struct fd_ringbuffer *ring, const struct program_builder *b)
}
OUT_REG(ring,
A7XX_HLSQ_UNKNOWN_A9AE(
A7XX_SP_PS_CNTL_1(
.sysval_regs_count = sysval_regs,
.unk8 = 1,
.unk9 = 1,
@@ -1046,7 +1046,7 @@ emit_fs_inputs(struct fd_ringbuffer *ring, const struct program_builder *b)
enum a6xx_threadsize thrsz = fs->info.double_threadsize ? THREAD128 : THREAD64;
OUT_REG(ring,
HLSQ_FS_CNTL_0(
SP_PS_WAVE_CNTL(
CHIP,
.threadsize = thrsz,
.varyings = enable_varyings,
@@ -1062,43 +1062,43 @@ emit_fs_inputs(struct fd_ringbuffer *ring, const struct program_builder *b)
need_size = true;
}
OUT_PKT4(ring, REG_A6XX_GRAS_CNTL, 1);
OUT_PKT4(ring, REG_A6XX_GRAS_CL_INTERP_CNTL, 1);
OUT_RING(ring,
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CNTL_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CNTL_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CNTL_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_GRAS_CNTL_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_GRAS_CNTL_IJ_LINEAR_PIXEL) |
COND(need_size_persamp, A6XX_GRAS_CNTL_IJ_LINEAR_SAMPLE) |
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_GRAS_CL_INTERP_CNTL_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_PIXEL) |
COND(need_size_persamp, A6XX_GRAS_CL_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(fs->fragcoord_compmask != 0,
A6XX_GRAS_CNTL_COORD_MASK(fs->fragcoord_compmask)));
A6XX_GRAS_CL_INTERP_CNTL_COORD_MASK(fs->fragcoord_compmask)));
OUT_PKT4(ring, REG_A6XX_RB_RENDER_CONTROL0, 2);
OUT_PKT4(ring, REG_A6XX_RB_INTERP_CNTL, 2);
OUT_RING(ring,
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_PIXEL) |
COND(enable_varyings, A6XX_RB_RENDER_CONTROL0_UNK10) |
COND(need_size_persamp, A6XX_RB_RENDER_CONTROL0_IJ_LINEAR_SAMPLE) |
CONDREG(ij_regid[IJ_PERSP_PIXEL], A6XX_RB_INTERP_CNTL_IJ_PERSP_PIXEL) |
CONDREG(ij_regid[IJ_PERSP_CENTROID], A6XX_RB_INTERP_CNTL_IJ_PERSP_CENTROID) |
CONDREG(ij_regid[IJ_PERSP_SAMPLE], A6XX_RB_INTERP_CNTL_IJ_PERSP_SAMPLE) |
CONDREG(ij_regid[IJ_LINEAR_PIXEL], A6XX_RB_INTERP_CNTL_IJ_LINEAR_PIXEL) |
CONDREG(ij_regid[IJ_LINEAR_CENTROID], A6XX_RB_INTERP_CNTL_IJ_LINEAR_CENTROID) |
CONDREG(ij_regid[IJ_LINEAR_SAMPLE], A6XX_RB_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(need_size, A6XX_RB_INTERP_CNTL_IJ_LINEAR_PIXEL) |
COND(enable_varyings, A6XX_RB_INTERP_CNTL_UNK10) |
COND(need_size_persamp, A6XX_RB_INTERP_CNTL_IJ_LINEAR_SAMPLE) |
COND(fs->fragcoord_compmask != 0,
A6XX_RB_RENDER_CONTROL0_COORD_MASK(fs->fragcoord_compmask)));
A6XX_RB_INTERP_CNTL_COORD_MASK(fs->fragcoord_compmask)));
OUT_RING(ring,
A6XX_RB_RENDER_CONTROL1_FRAGCOORDSAMPLEMODE(
A6XX_RB_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER) |
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_CENTERRHW) |
COND(fs->post_depth_coverage, A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE) |
COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
CONDREG(smask_in_regid, A6XX_RB_PS_INPUT_CNTL_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_PS_INPUT_CNTL_SAMPLEID) |
CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_PS_INPUT_CNTL_CENTERRHW) |
COND(fs->post_depth_coverage, A6XX_RB_PS_INPUT_CNTL_POSTDEPTHCOVERAGE) |
COND(fs->frag_face, A6XX_RB_PS_INPUT_CNTL_FACENESS));
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_CNTL, 1);
OUT_RING(ring, COND(sample_shading, A6XX_RB_SAMPLE_CNTL_PER_SAMP_MODE));
OUT_PKT4(ring, REG_A6XX_RB_PS_SAMPLEFREQ_CNTL, 1);
OUT_RING(ring, COND(sample_shading, A6XX_RB_PS_SAMPLEFREQ_CNTL_PER_SAMP_MODE));
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL, 1);
OUT_RING(ring,
@@ -1106,8 +1106,8 @@ emit_fs_inputs(struct fd_ringbuffer *ring, const struct program_builder *b)
A6XX_GRAS_LRZ_PS_INPUT_CNTL_FRAGCOORDSAMPLEMODE(
sample_shading ? FRAGCOORD_SAMPLE : FRAGCOORD_CENTER));
OUT_PKT4(ring, REG_A6XX_GRAS_SAMPLE_CNTL, 1);
OUT_RING(ring, COND(sample_shading, A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE));
OUT_PKT4(ring, REG_A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL, 1);
OUT_RING(ring, COND(sample_shading, A6XX_GRAS_LRZ_PS_SAMPLEFREQ_CNTL_PER_SAMP_MODE));
}
template<chip CHIP>
@@ -1153,17 +1153,17 @@ emit_fs_outputs(struct fd_ringbuffer *ring, const struct program_builder *b)
}
}
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_CNTL0, 1);
OUT_RING(ring, A6XX_SP_FS_OUTPUT_CNTL0_DEPTH_REGID(posz_regid) |
A6XX_SP_FS_OUTPUT_CNTL0_SAMPMASK_REGID(smask_regid) |
A6XX_SP_FS_OUTPUT_CNTL0_STENCILREF_REGID(stencilref_regid) |
COND(fs->dual_src_blend, A6XX_SP_FS_OUTPUT_CNTL0_DUAL_COLOR_IN_ENABLE));
OUT_PKT4(ring, REG_A6XX_SP_PS_OUTPUT_CNTL, 1);
OUT_RING(ring, A6XX_SP_PS_OUTPUT_CNTL_DEPTH_REGID(posz_regid) |
A6XX_SP_PS_OUTPUT_CNTL_SAMPMASK_REGID(smask_regid) |
A6XX_SP_PS_OUTPUT_CNTL_STENCILREF_REGID(stencilref_regid) |
COND(fs->dual_src_blend, A6XX_SP_PS_OUTPUT_CNTL_DUAL_COLOR_IN_ENABLE));
OUT_PKT4(ring, REG_A6XX_SP_FS_OUTPUT_REG(0), output_reg_count);
OUT_PKT4(ring, REG_A6XX_SP_PS_OUTPUT_REG(0), output_reg_count);
for (uint32_t i = 0; i < output_reg_count; i++) {
OUT_RING(ring, A6XX_SP_FS_OUTPUT_REG_REGID(fragdata_regid[i]) |
OUT_RING(ring, A6XX_SP_PS_OUTPUT_REG_REGID(fragdata_regid[i]) |
COND(fragdata_regid[i] & HALF_REG_ID,
A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION));
A6XX_SP_PS_OUTPUT_REG_HALF_PRECISION));
if (VALIDREG(fragdata_regid[i]) ||
(fragdata_aliased_components & (0xf << (i * 4)))) {
@@ -1174,9 +1174,9 @@ emit_fs_outputs(struct fd_ringbuffer *ring, const struct program_builder *b)
if (CHIP >= A7XX) {
OUT_REG(
ring,
A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL(
A7XX_SP_PS_OUTPUT_CONST_CNTL(
.enabled = fragdata_aliased_components != 0),
A7XX_SP_PS_ALIASED_COMPONENTS(.dword = fragdata_aliased_components));
A7XX_SP_PS_OUTPUT_CONST_MASK(.dword = fragdata_aliased_components));
} else {
assert(fragdata_aliased_components == 0);
}
@@ -1194,7 +1194,7 @@ setup_stateobj(struct fd_ringbuffer *ring, const struct program_builder *b)
if (!b->binning_pass)
fd6_emit_shader<CHIP>(b->ctx, ring, b->fs);
OUT_PKT4(ring, REG_A6XX_PC_MULTIVIEW_CNTL, 1);
OUT_PKT4(ring, REG_A6XX_PC_STEREO_RENDERING_CNTL, 1);
OUT_RING(ring, 0);
emit_vfd_dest(ring, b->vs);
@@ -1211,7 +1211,7 @@ setup_stateobj(struct fd_ringbuffer *ring, const struct program_builder *b)
patch_control_points * b->vs->output_size / 4;
/* Total attribute slots in HS incoming patch. */
OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
OUT_PKT4(ring, REG_A6XX_PC_HS_PARAM_1, 1);
OUT_RING(ring, patch_local_mem_size_16b);
const uint32_t wavesize = 64;
@@ -1239,7 +1239,7 @@ setup_stateobj(struct fd_ringbuffer *ring, const struct program_builder *b)
uint32_t wave_input_size = DIV_ROUND_UP(
patches_per_wave * patch_local_mem_size_16b * 16, 256);
OUT_PKT4(ring, REG_A6XX_SP_HS_WAVE_INPUT_SIZE, 1);
OUT_PKT4(ring, REG_A6XX_SP_HS_CNTL_1, 1);
OUT_RING(ring, wave_input_size);
enum a6xx_tess_output output;
@@ -1252,10 +1252,10 @@ setup_stateobj(struct fd_ringbuffer *ring, const struct program_builder *b)
else
output = TESS_CW_TRIS;
OUT_PKT4(ring, REG_A6XX_PC_TESS_CNTL, 1);
OUT_RING(ring, A6XX_PC_TESS_CNTL_SPACING(
OUT_PKT4(ring, REG_A6XX_PC_DS_PARAM, 1);
OUT_RING(ring, A6XX_PC_DS_PARAM_SPACING(
fd6_gl2spacing(b->ds->tess.spacing)) |
A6XX_PC_TESS_CNTL_OUTPUT(output));
A6XX_PC_DS_PARAM_OUTPUT(output));
}
}
@@ -1372,21 +1372,21 @@ emit_interp_state(struct fd_ringbuffer *ring, const struct fd6_program_state *st
}
}
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE(0), 8);
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_INTERP_MODE_MODE(0), 8);
for (int i = 0; i < 8; i++)
OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP[i].MODE */
OUT_RING(ring, vinterp[i]); /* VPC_VARYING_INTERP_MODE[i].MODE */
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_PS_REPL_MODE(0), 8);
OUT_PKT4(ring, REG_A6XX_VPC_VARYING_REPLACE_MODE_0_MODE(0), 8);
for (int i = 0; i < 8; i++)
OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_PS_REPL[i] */
OUT_RING(ring, vpsrepl[i]); /* VPC_VARYING_REPLACE_MODE_0[i] */
}
template <chip CHIP>
static struct ir3_program_state *
fd6_program_create(void *data, const struct ir3_shader_variant *bs,
const struct ir3_shader_variant *vs,
const struct ir3_shader_variant *vs,
const struct ir3_shader_variant *hs,
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
const struct ir3_shader_variant *fs,
const struct ir3_cache_key *key) in_dt
src/gallium/drivers/freedreno/a6xx/fd6_query.cc
+12 -12
View File
@@ -29,7 +29,7 @@
struct PACKED fd6_query_sample {
struct fd_acc_query_sample base;
/* The RB_SAMPLE_COUNT_ADDR destination needs to be 16-byte aligned: */
/* The RB_SAMPLE_COUNTER_BASE destination needs to be 16-byte aligned: */
uint64_t pad;
uint64_t start;
@@ -64,11 +64,11 @@ occlusion_resume(struct fd_acc_query *aq, struct fd_batch *batch)
ASSERT_ALIGNED(struct fd6_query_sample, start, 16);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_CNTL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNTER_CNTL_COPY);
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_BASE, 2);
OUT_RELOC(ring, query_sample(aq, start));
fd6_event_write<CHIP>(ctx, ring, FD_ZPASS_DONE);
@@ -120,13 +120,13 @@ occlusion_pause(struct fd_acc_query *aq, struct fd_batch *batch) assert_dt
OUT_PKT7(ring, CP_WAIT_MEM_WRITES, 0);
}
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_CONTROL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNT_CONTROL_COPY);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_CNTL, 1);
OUT_RING(ring, A6XX_RB_SAMPLE_COUNTER_CNTL_COPY);
ASSERT_ALIGNED(struct fd6_query_sample, stop, 16);
if (!ctx->screen->info->a7xx.has_event_write_sample_count) {
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNT_ADDR, 2);
OUT_PKT4(ring, REG_A6XX_RB_SAMPLE_COUNTER_BASE, 2);
OUT_RELOC(ring, query_sample(aq, stop));
fd6_event_write<CHIP>(batch->ctx, ring, FD_ZPASS_DONE);
@@ -497,7 +497,7 @@ pipeline_stats_resume(struct fd_acc_query *aq, struct fd_batch *batch)
struct fd_ringbuffer *ring = batch->draw;
enum stats_type type = get_stats_type(aq);
unsigned idx = stats_counter_index(aq);
unsigned reg = REG_A6XX_RBBM_PRIMCTR_0 + (2 * idx);
unsigned reg = REG_A6XX_RBBM_PIPESTAT_IAVERTICES + (2 * idx);
OUT_WFI5(ring);
@@ -522,7 +522,7 @@ pipeline_stats_pause(struct fd_acc_query *aq, struct fd_batch *batch)
struct fd_ringbuffer *ring = batch->draw;
enum stats_type type = get_stats_type(aq);
unsigned idx = stats_counter_index(aq);
unsigned reg = REG_A6XX_RBBM_PRIMCTR_0 + (2 * idx);
unsigned reg = REG_A6XX_RBBM_PIPESTAT_IAVERTICES + (2 * idx);
OUT_WFI5(ring);
@@ -595,7 +595,7 @@ static const struct fd_acc_sample_provider pipeline_statistics_single = {
struct PACKED fd6_primitives_sample {
struct fd_acc_query_sample base;
/* VPC_SO_STREAM_COUNTS dest address must be 32b aligned: */
/* VPC_SO_QUERY_BASE dest address must be 32b aligned: */
uint64_t pad[3];
struct {
@@ -640,7 +640,7 @@ primitives_emitted_resume(struct fd_acc_query *aq,
ASSERT_ALIGNED(struct fd6_primitives_sample, start[0], 32);
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS, 2);
OUT_PKT4(ring, REG_A6XX_VPC_SO_QUERY_BASE, 2);
primitives_reloc(ring, aq, start[0]);
fd6_event_write<CHIP>(batch->ctx, ring, FD_WRITE_PRIMITIVE_COUNTS);
@@ -685,7 +685,7 @@ primitives_emitted_pause(struct fd_acc_query *aq,
ASSERT_ALIGNED(struct fd6_primitives_sample, stop[0], 32);
OUT_PKT4(ring, REG_A6XX_VPC_SO_STREAM_COUNTS, 2);
OUT_PKT4(ring, REG_A6XX_VPC_SO_QUERY_BASE, 2);
primitives_reloc(ring, aq, stop[0]);
fd6_event_write<CHIP>(batch->ctx, ring, FD_WRITE_PRIMITIVE_COUNTS);
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.cc
+8 -8
View File
@@ -68,7 +68,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
A6XX_GRAS_SU_POLY_OFFSET_OFFSET_CLAMP(cso->offset_clamp));
OUT_REG(ring,
A6XX_PC_PRIMITIVE_CNTL_0(
A6XX_PC_CNTL(
.primitive_restart = primitive_restart,
.provoking_vtx_last = !cso->flatshade_first,
),
@@ -76,7 +76,7 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
if (CHIP >= A7XX) {
OUT_REG(ring,
A7XX_VPC_PRIMITIVE_CNTL_0(
A7XX_VPC_PC_CNTL(
.primitive_restart = primitive_restart,
.provoking_vtx_last = !cso->flatshade_first,
),
@@ -96,12 +96,12 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
break;
}
OUT_REG(ring, A6XX_VPC_POLYGON_MODE(mode));
OUT_REG(ring, PC_POLYGON_MODE(CHIP, mode));
OUT_REG(ring, A6XX_VPC_RAST_CNTL(mode));
OUT_REG(ring, PC_DGEN_RAST_CNTL(CHIP, mode));
if (CHIP == A7XX ||
(CHIP == A6XX && ctx->screen->info->a6xx.is_a702)) {
OUT_REG(ring, A6XX_VPC_POLYGON_MODE2(mode));
OUT_REG(ring, A6XX_VPC_PS_RAST_CNTL(mode));
}
/* With a7xx the hw doesn't do the clamping for us. When depth clamp
@@ -115,15 +115,15 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
/* We must assume the max: */
const unsigned num_viewports = 16;
OUT_PKT4(ring, REG_A6XX_GRAS_CL_Z_CLAMP(0), num_viewports * 2);
OUT_PKT4(ring, REG_A6XX_GRAS_CL_VIEWPORT_ZCLAMP(0), num_viewports * 2);
for (unsigned i = 0; i < num_viewports; i++) {
OUT_RING(ring, fui(0.0f));
OUT_RING(ring, fui(1.0f));
}
OUT_REG(ring,
A6XX_RB_Z_CLAMP_MIN(0.0f),
A6XX_RB_Z_CLAMP_MAX(1.0),
A6XX_RB_VIEWPORT_ZCLAMP_MIN(0.0f),
A6XX_RB_VIEWPORT_ZCLAMP_MAX(1.0),
);
}
src/gallium/drivers/freedreno/a6xx/fd6_texture.cc
+18 -18
View File
@@ -613,44 +613,44 @@ build_texture_state(struct fd_context *ctx, enum pipe_shader_type type,
case PIPE_SHADER_VERTEX:
sb = SB6_VS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_VS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_VS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_VS_TEX_COUNT;
tex_samp_reg = REG_A6XX_SP_VS_SAMPLER_BASE;
tex_const_reg = REG_A6XX_SP_VS_TEXMEMOBJ_BASE;
tex_count_reg = REG_A6XX_SP_VS_TSIZE;
break;
case PIPE_SHADER_TESS_CTRL:
sb = SB6_HS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_HS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_HS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_HS_TEX_COUNT;
tex_samp_reg = REG_A6XX_SP_HS_SAMPLER_BASE;
tex_const_reg = REG_A6XX_SP_HS_TEXMEMOBJ_BASE;
tex_count_reg = REG_A6XX_SP_HS_TSIZE;
break;
case PIPE_SHADER_TESS_EVAL:
sb = SB6_DS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_DS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_DS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_DS_TEX_COUNT;
tex_samp_reg = REG_A6XX_SP_DS_SAMPLER_BASE;
tex_const_reg = REG_A6XX_SP_DS_TEXMEMOBJ_BASE;
tex_count_reg = REG_A6XX_SP_DS_TSIZE;
break;
case PIPE_SHADER_GEOMETRY:
sb = SB6_GS_TEX;
opcode = CP_LOAD_STATE6_GEOM;
tex_samp_reg = REG_A6XX_SP_GS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_GS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_GS_TEX_COUNT;
tex_samp_reg = REG_A6XX_SP_GS_SAMPLER_BASE;
tex_const_reg = REG_A6XX_SP_GS_TEXMEMOBJ_BASE;
tex_count_reg = REG_A6XX_SP_GS_TSIZE;
break;
case PIPE_SHADER_FRAGMENT:
sb = SB6_FS_TEX;
opcode = CP_LOAD_STATE6_FRAG;
tex_samp_reg = REG_A6XX_SP_FS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_FS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_FS_TEX_COUNT;
tex_samp_reg = REG_A6XX_SP_PS_SAMPLER_BASE;
tex_const_reg = REG_A6XX_SP_PS_TEXMEMOBJ_BASE;
tex_count_reg = REG_A6XX_SP_PS_TSIZE;
break;
case PIPE_SHADER_COMPUTE:
sb = SB6_CS_TEX;
opcode = CP_LOAD_STATE6_FRAG;
tex_samp_reg = REG_A6XX_SP_CS_TEX_SAMP;
tex_const_reg = REG_A6XX_SP_CS_TEX_CONST;
tex_count_reg = REG_A6XX_SP_CS_TEX_COUNT;
tex_samp_reg = REG_A6XX_SP_CS_SAMPLER_BASE;
tex_const_reg = REG_A6XX_SP_CS_TEXMEMOBJ_BASE;
tex_count_reg = REG_A6XX_SP_CS_TSIZE;
break;
default:
unreachable("bad state block");
src/gallium/drivers/freedreno/a6xx/fd6_zsa.cc
+26 -26
View File
@@ -168,15 +168,15 @@ fd6_zsa_state_create(struct pipe_context *pctx,
update_lrz_stencil(so, (enum pipe_compare_func)s->func, util_writes_stencil(s));
so->rb_stencil_control |=
A6XX_RB_STENCIL_CONTROL_STENCIL_READ |
A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE |
A6XX_RB_STENCIL_CONTROL_FUNC((enum adreno_compare_func)s->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CONTROL_FAIL(fd_stencil_op(s->fail_op)) |
A6XX_RB_STENCIL_CONTROL_ZPASS(fd_stencil_op(s->zpass_op)) |
A6XX_RB_STENCIL_CONTROL_ZFAIL(fd_stencil_op(s->zfail_op));
A6XX_RB_STENCIL_CNTL_STENCIL_READ |
A6XX_RB_STENCIL_CNTL_STENCIL_ENABLE |
A6XX_RB_STENCIL_CNTL_FUNC((enum adreno_compare_func)s->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CNTL_FAIL(fd_stencil_op(s->fail_op)) |
A6XX_RB_STENCIL_CNTL_ZPASS(fd_stencil_op(s->zpass_op)) |
A6XX_RB_STENCIL_CNTL_ZFAIL(fd_stencil_op(s->zfail_op));
so->rb_stencilmask = A6XX_RB_STENCILMASK_MASK(s->valuemask);
so->rb_stencilwrmask = A6XX_RB_STENCILWRMASK_WRMASK(s->writemask);
so->rb_stencilmask = A6XX_RB_STENCIL_MASK_MASK(s->valuemask);
so->rb_stencilwrmask = A6XX_RB_STENCIL_WRITE_MASK_WRMASK(s->writemask);
if (cso->stencil[1].enabled) {
const struct pipe_stencil_state *bs = &cso->stencil[1];
@@ -184,14 +184,14 @@ fd6_zsa_state_create(struct pipe_context *pctx,
update_lrz_stencil(so, (enum pipe_compare_func)bs->func, util_writes_stencil(bs));
so->rb_stencil_control |=
A6XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF |
A6XX_RB_STENCIL_CONTROL_FUNC_BF((enum adreno_compare_func)bs->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CONTROL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
A6XX_RB_STENCIL_CONTROL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
A6XX_RB_STENCIL_CNTL_STENCIL_ENABLE_BF |
A6XX_RB_STENCIL_CNTL_FUNC_BF((enum adreno_compare_func)bs->func) | /* maps 1:1 */
A6XX_RB_STENCIL_CNTL_FAIL_BF(fd_stencil_op(bs->fail_op)) |
A6XX_RB_STENCIL_CNTL_ZPASS_BF(fd_stencil_op(bs->zpass_op)) |
A6XX_RB_STENCIL_CNTL_ZFAIL_BF(fd_stencil_op(bs->zfail_op));
so->rb_stencilmask |= A6XX_RB_STENCILMASK_BFMASK(bs->valuemask);
so->rb_stencilwrmask |= A6XX_RB_STENCILWRMASK_BFWRMASK(bs->writemask);
so->rb_stencilmask |= A6XX_RB_STENCIL_MASK_BFMASK(bs->valuemask);
so->rb_stencilwrmask |= A6XX_RB_STENCIL_WRITE_MASK_BFWRMASK(bs->writemask);
}
}
@@ -206,9 +206,9 @@ fd6_zsa_state_create(struct pipe_context *pctx,
uint32_t ref = cso->alpha_ref_value * 255.0f;
so->rb_alpha_control =
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST |
A6XX_RB_ALPHA_CONTROL_ALPHA_REF(ref) |
A6XX_RB_ALPHA_CONTROL_ALPHA_TEST_FUNC(
A6XX_RB_ALPHA_TEST_CNTL_ALPHA_TEST |
A6XX_RB_ALPHA_TEST_CNTL_ALPHA_REF(ref) |
A6XX_RB_ALPHA_TEST_CNTL_ALPHA_TEST_FUNC(
(enum adreno_compare_func)cso->alpha_func);
}
@@ -223,13 +223,13 @@ fd6_zsa_state_create(struct pipe_context *pctx,
struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 16 * 4);
bool depth_clamp_enable = (i & FD6_ZSA_DEPTH_CLAMP);
OUT_PKT4(ring, REG_A6XX_RB_ALPHA_CONTROL, 1);
OUT_PKT4(ring, REG_A6XX_RB_ALPHA_TEST_CNTL, 1);
OUT_RING(ring,
(i & FD6_ZSA_NO_ALPHA)
? so->rb_alpha_control & ~A6XX_RB_ALPHA_CONTROL_ALPHA_TEST
? so->rb_alpha_control & ~A6XX_RB_ALPHA_TEST_CNTL_ALPHA_TEST
: so->rb_alpha_control);
OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CONTROL, 1);
OUT_PKT4(ring, REG_A6XX_RB_STENCIL_CNTL, 1);
OUT_RING(ring, so->rb_stencil_control);
OUT_REG(ring, A6XX_GRAS_SU_STENCIL_CNTL(cso->stencil[0].enabled));
@@ -241,19 +241,19 @@ fd6_zsa_state_create(struct pipe_context *pctx,
OUT_REG(ring, A6XX_GRAS_SU_DEPTH_CNTL(cso->depth_enabled));
OUT_PKT4(ring, REG_A6XX_RB_STENCILMASK, 2);
OUT_PKT4(ring, REG_A6XX_RB_STENCIL_MASK, 2);
OUT_RING(ring, so->rb_stencilmask);
OUT_RING(ring, so->rb_stencilwrmask);
if (CHIP >= A7XX && !depth_clamp_enable) {
OUT_REG(ring,
A6XX_RB_Z_BOUNDS_MIN(0.0f),
A6XX_RB_Z_BOUNDS_MAX(1.0f),
A6XX_RB_DEPTH_BOUND_MIN(0.0f),
A6XX_RB_DEPTH_BOUND_MAX(1.0f),
);
} else {
OUT_REG(ring,
A6XX_RB_Z_BOUNDS_MIN(cso->depth_bounds_min),
A6XX_RB_Z_BOUNDS_MAX(cso->depth_bounds_max),
A6XX_RB_DEPTH_BOUND_MIN(cso->depth_bounds_min),
A6XX_RB_DEPTH_BOUND_MAX(cso->depth_bounds_max),
);
}