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radeonsi/gfx10: set GE_CTNL.PACKET_TO_ONE_PA for NGG

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Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
This commit is contained in:
Marek Olšák
2019-07-05 21:06:04 -04:00
parent e08463ac22
commit 7f0ada3f3e
3 changed files with 27 additions and 27 deletions
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src/gallium/drivers/radeonsi/si_pipe.h
+3 -1
View File
@@ -1629,7 +1629,9 @@ static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
static inline struct si_shader* si_get_vs_state(struct si_context *sctx)
{
if (sctx->gs_shader.cso)
if (sctx->gs_shader.cso &&
sctx->gs_shader.current &&
!sctx->gs_shader.current->key.as_ngg)
return sctx->gs_shader.cso->gs_copy_shader;
struct si_shader_ctx_state *vs = si_get_vs(sctx);
src/gallium/drivers/radeonsi/si_state_draw.c
+24 -21
View File
@@ -715,30 +715,33 @@ static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
*/
static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
{
if (sctx->ngg)
return; /* set during PM4 emit */
unsigned ge_cntl;
union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
unsigned primgroup_size;
unsigned vertgroup_size;
if (sctx->tes_shader.cso) {
primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
vertgroup_size = 0;
} else if (sctx->gs_shader.cso) {
unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
if (sctx->ngg) {
ge_cntl = si_get_vs_state(sctx)->ge_cntl |
S_03096C_PACKET_TO_ONE_PA(sctx->ia_multi_vgt_param_key.u.line_stipple_enabled);
} else {
primgroup_size = 128; /* recommended without a GS and tess */
vertgroup_size = 0;
}
union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
unsigned primgroup_size;
unsigned vertgroup_size;
unsigned ge_cntl =
S_03096C_PRIM_GRP_SIZE(primgroup_size) |
S_03096C_VERT_GRP_SIZE(vertgroup_size) |
S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled) |
S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
if (sctx->tes_shader.cso) {
primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
vertgroup_size = 0;
} else if (sctx->gs_shader.cso) {
unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
} else {
primgroup_size = 128; /* recommended without a GS and tess */
vertgroup_size = 0;
}
ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) |
S_03096C_VERT_GRP_SIZE(vertgroup_size) |
S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id) |
S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled);
}
if (ge_cntl != sctx->last_multi_vgt_param) {
radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
src/gallium/drivers/radeonsi/si_state_shaders.c
-5
View File
@@ -990,11 +990,6 @@ static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
if (initial_cdw != sctx->gfx_cs->current.cdw)
sctx->context_roll = true;
if (shader->ge_cntl != sctx->last_multi_vgt_param) {
radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
sctx->last_multi_vgt_param = shader->ge_cntl;
}
}
static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)