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freedreno/drm: Cleanup bo allocation flags

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Most of them were actually unused.  The memory type (KMEM vs SMI) only
applied to very old a2xx era devices that had a small/fast stacked
memory (SMI) vs normal memory (KMEM).  And the cache flags are ignored
(ie. everything is writecombine), but we can add new cache flags later
when they actually do something.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10444>
This commit is contained in:
Rob Clark
2021-04-22 11:09:56 -07:00
committed by Marge Bot
parent ef0c5007f2
commit 7f0abd9048
21 changed files with 34 additions and 52 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/computerator/a6xx.c
+2 -3
View File
@@ -389,8 +389,7 @@ a6xx_emit_grid(struct kernel *kernel, uint32_t grid[3],
if (a6xx_backend->num_perfcntrs > 0) {
a6xx_backend->query_mem = fd_bo_new(
a6xx_backend->dev,
a6xx_backend->num_perfcntrs * sizeof(struct fd6_query_sample),
DRM_FREEDRENO_GEM_TYPE_KMEM, "query");
a6xx_backend->num_perfcntrs * sizeof(struct fd6_query_sample), 0, "query");
/* configure the performance counters to count the requested
* countables:
@@ -489,7 +488,7 @@ a6xx_init(struct fd_device *dev, uint32_t gpu_id)
a6xx_backend->dev = dev;
a6xx_backend->control_mem =
fd_bo_new(dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM, "control");
fd_bo_new(dev, 0x1000, 0, "control");
return &a6xx_backend->base;
}
src/freedreno/computerator/ir3_asm.c
+1 -3
View File
@@ -49,9 +49,7 @@ ir3_asm_assemble(struct ir3_compiler *c, FILE *in)
unsigned sz = v->info.size;
v->bo = fd_bo_new(c->dev, sz,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE | DRM_FREEDRENO_GEM_TYPE_KMEM,
"%s", ir3_shader_stage(v));
v->bo = fd_bo_new(c->dev, sz, 0, "%s", ir3_shader_stage(v));
memcpy(fd_bo_map(v->bo), kernel->bin, sz);
src/freedreno/computerator/main.c
+1 -2
View File
@@ -263,8 +263,7 @@ main(int argc, char **argv)
kernel->local_size[2]);
for (int i = 0; i < kernel->num_bufs; i++) {
printf("buf[%d]: size=%u\n", i, kernel->buf_sizes[i]);
kernel->bufs[i] = fd_bo_new(dev, kernel->buf_sizes[i] * 4,
DRM_FREEDRENO_GEM_TYPE_KMEM, "buf[%d]", i);
kernel->bufs[i] = fd_bo_new(dev, kernel->buf_sizes[i] * 4, 0, "buf[%d]", i);
}
if (disasm)
src/freedreno/drm/freedreno_bo.c
+1 -1
View File
@@ -134,7 +134,7 @@ _fd_bo_set_name(struct fd_bo *bo, const char *fmt, va_list ap)
struct fd_bo *
fd_bo_new_ring(struct fd_device *dev, uint32_t size)
{
uint32_t flags = DRM_FREEDRENO_GEM_GPUREADONLY;
uint32_t flags = FD_BO_GPUREADONLY;
struct fd_bo *bo = bo_new(dev, size, flags, &dev->ring_cache);
if (bo) {
bo->bo_reuse = RING_CACHE;
src/freedreno/drm/freedreno_drmif.h
+4 -11
View File
@@ -29,6 +29,7 @@
#include <stdint.h>
#include "util/bitset.h"
#include "util/u_debug.h"
#ifdef __cplusplus
@@ -63,17 +64,9 @@ enum fd_param_id {
};
/* bo flags: */
#define DRM_FREEDRENO_GEM_TYPE_SMI 0x00000001
#define DRM_FREEDRENO_GEM_TYPE_KMEM 0x00000002
#define DRM_FREEDRENO_GEM_TYPE_MEM_MASK 0x0000000f
#define DRM_FREEDRENO_GEM_CACHE_NONE 0x00000000
#define DRM_FREEDRENO_GEM_CACHE_WCOMBINE 0x00100000
#define DRM_FREEDRENO_GEM_CACHE_WTHROUGH 0x00200000
#define DRM_FREEDRENO_GEM_CACHE_WBACK 0x00400000
#define DRM_FREEDRENO_GEM_CACHE_WBACKWA 0x00800000
#define DRM_FREEDRENO_GEM_CACHE_MASK 0x00f00000
#define DRM_FREEDRENO_GEM_GPUREADONLY 0x01000000
#define DRM_FREEDRENO_GEM_SCANOUT 0x02000000
#define FD_BO_GPUREADONLY BITSET_BIT(1)
#define FD_BO_SCANOUT BITSET_BIT(2)
/* Default caching is WRITECOMBINE, we can add new bo flags later for cached/etc */
/* bo access flags: (keep aligned to MSM_PREP_x) */
#define DRM_FREEDRENO_PREP_READ 0x01
src/freedreno/drm/msm_bo.c
+2 -2
View File
@@ -174,10 +174,10 @@ msm_bo_new_handle(struct fd_device *dev, uint32_t size, uint32_t flags,
};
int ret;
if (flags & DRM_FREEDRENO_GEM_SCANOUT)
if (flags & FD_BO_SCANOUT)
req.flags |= MSM_BO_SCANOUT;
if (flags & DRM_FREEDRENO_GEM_GPUREADONLY)
if (flags & FD_BO_GPUREADONLY)
req.flags |= MSM_BO_GPU_READONLY;
ret = drmCommandWriteRead(dev->fd, DRM_MSM_GEM_NEW, &req, sizeof(req));
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+1 -2
View File
@@ -602,8 +602,7 @@ fd2_emit_tile_init(struct fd_batch *batch) assert_dt
if (ctx->vsc_pipe_bo[i])
fd_bo_del(ctx->vsc_pipe_bo[i]);
ctx->vsc_pipe_bo[i] =
fd_bo_new(ctx->dev, bo_size, DRM_FREEDRENO_GEM_TYPE_KMEM,
"vsc_pipe[%u]", i);
fd_bo_new(ctx->dev, bo_size, 0, "vsc_pipe[%u]", i);
assert(ctx->vsc_pipe_bo[i]);
}
src/gallium/drivers/freedreno/a3xx/fd3_context.c
+3 -3
View File
@@ -107,13 +107,13 @@ fd3_context_create(struct pipe_screen *pscreen, void *priv,
fd_hw_query_init(pctx);
fd3_ctx->vs_pvt_mem =
fd_bo_new(screen->dev, 0x2000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vs_pvt");
fd_bo_new(screen->dev, 0x2000, 0, "vs_pvt");
fd3_ctx->fs_pvt_mem =
fd_bo_new(screen->dev, 0x2000, DRM_FREEDRENO_GEM_TYPE_KMEM, "fs_pvt");
fd_bo_new(screen->dev, 0x2000, 0, "fs_pvt");
fd3_ctx->vsc_size_mem =
fd_bo_new(screen->dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_size");
fd_bo_new(screen->dev, 0x1000, 0, "vsc_size");
fd_context_setup_common_vbos(&fd3_ctx->base);
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+1 -1
View File
@@ -806,7 +806,7 @@ update_vsc_pipe(struct fd_batch *batch) assert_dt
if (!ctx->vsc_pipe_bo[i]) {
ctx->vsc_pipe_bo[i] = fd_bo_new(
ctx->dev, 0x40000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
ctx->dev, 0x40000, 0, "vsc_pipe[%u]", i);
}
OUT_PKT0(ring, REG_A3XX_VSC_PIPE(i), 3);
src/gallium/drivers/freedreno/a4xx/fd4_context.c
+3 -3
View File
@@ -107,13 +107,13 @@ fd4_context_create(struct pipe_screen *pscreen, void *priv,
fd_hw_query_init(pctx);
fd4_ctx->vs_pvt_mem =
fd_bo_new(screen->dev, 0x2000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vs_pvt");
fd_bo_new(screen->dev, 0x2000, 0, "vs_pvt");
fd4_ctx->fs_pvt_mem =
fd_bo_new(screen->dev, 0x2000, DRM_FREEDRENO_GEM_TYPE_KMEM, "fs_pvt");
fd_bo_new(screen->dev, 0x2000, 0, "fs_pvt");
fd4_ctx->vsc_size_mem =
fd_bo_new(screen->dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_size");
fd_bo_new(screen->dev, 0x1000, 0, "vsc_size");
fd_context_setup_common_vbos(&fd4_ctx->base);
src/gallium/drivers/freedreno/a4xx/fd4_gmem.c
+1 -1
View File
@@ -587,7 +587,7 @@ update_vsc_pipe(struct fd_batch *batch) assert_dt
for (i = 0; i < 8; i++) {
if (!ctx->vsc_pipe_bo[i]) {
ctx->vsc_pipe_bo[i] = fd_bo_new(
ctx->dev, 0x40000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
ctx->dev, 0x40000, 0, "vsc_pipe[%u]", i);
}
OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0,
0); /* VSC_PIPE_DATA_ADDRESS[i] */
src/gallium/drivers/freedreno/a5xx/fd5_context.c
+2 -2
View File
@@ -110,10 +110,10 @@ fd5_context_create(struct pipe_screen *pscreen, void *priv,
util_blitter_set_texture_multisample(fd5_ctx->base.blitter, true);
fd5_ctx->vsc_size_mem =
fd_bo_new(screen->dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_size");
fd_bo_new(screen->dev, 0x1000, 0, "vsc_size");
fd5_ctx->blit_mem =
fd_bo_new(screen->dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM, "blit");
fd_bo_new(screen->dev, 0x1000, 0, "blit");
fd_context_setup_common_vbos(&fd5_ctx->base);
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+1 -1
View File
@@ -291,7 +291,7 @@ update_vsc_pipe(struct fd_batch *batch) assert_dt
for (i = 0; i < 16; i++) {
if (!ctx->vsc_pipe_bo[i]) {
ctx->vsc_pipe_bo[i] = fd_bo_new(
ctx->dev, 0x20000, DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_pipe[%u]", i);
ctx->dev, 0x20000, 0, "vsc_pipe[%u]", i);
}
OUT_RELOC(ring, ctx->vsc_pipe_bo[i], 0, 0,
0); /* VSC_PIPE_DATA_ADDRESS[i].LO/HI */
src/gallium/drivers/freedreno/a5xx/fd5_resource.c
+1 -3
View File
@@ -30,8 +30,6 @@ static void
setup_lrz(struct fd_resource *rsc)
{
struct fd_screen *screen = fd_screen(rsc->b.b.screen);
const uint32_t flags =
DRM_FREEDRENO_GEM_CACHE_WCOMBINE | DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
unsigned lrz_pitch = align(DIV_ROUND_UP(rsc->b.b.width0, 8), 64);
unsigned lrz_height = DIV_ROUND_UP(rsc->b.b.height0, 8);
@@ -51,7 +49,7 @@ setup_lrz(struct fd_resource *rsc)
rsc->lrz_height = lrz_height;
rsc->lrz_width = lrz_pitch;
rsc->lrz_pitch = lrz_pitch;
rsc->lrz = fd_bo_new(screen->dev, size, flags, "lrz");
rsc->lrz = fd_bo_new(screen->dev, size, 0, "lrz");
}
uint32_t
src/gallium/drivers/freedreno/a6xx/fd6_context.c
+1 -1
View File
@@ -241,7 +241,7 @@ fd6_context_create(struct pipe_screen *pscreen, void *priv,
fd6_ctx->vsc_prim_strm_pitch = 0x1040;
fd6_ctx->control_mem =
fd_bo_new(screen->dev, 0x1000, DRM_FREEDRENO_GEM_TYPE_KMEM, "control");
fd_bo_new(screen->dev, 0x1000, 0, "control");
memset(fd_bo_map(fd6_ctx->control_mem), 0, sizeof(struct fd6_control));
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+4 -4
View File
@@ -335,13 +335,13 @@ update_vsc_pipe(struct fd_batch *batch)
if (!fd6_ctx->vsc_draw_strm) {
fd6_ctx->vsc_draw_strm = fd_bo_new(
ctx->screen->dev, VSC_DRAW_STRM_SIZE(fd6_ctx->vsc_draw_strm_pitch),
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_draw_strm");
0, "vsc_draw_strm");
}
if (!fd6_ctx->vsc_prim_strm) {
fd6_ctx->vsc_prim_strm = fd_bo_new(
ctx->screen->dev, VSC_PRIM_STRM_SIZE(fd6_ctx->vsc_prim_strm_pitch),
DRM_FREEDRENO_GEM_TYPE_KMEM, "vsc_prim_strm");
0, "vsc_prim_strm");
}
OUT_REG(
@@ -1443,10 +1443,10 @@ setup_tess_buffers(struct fd_batch *batch, struct fd_ringbuffer *ring)
struct fd_context *ctx = batch->ctx;
batch->tessfactor_bo = fd_bo_new(ctx->screen->dev, batch->tessfactor_size,
DRM_FREEDRENO_GEM_TYPE_KMEM, "tessfactor");
0, "tessfactor");
batch->tessparam_bo = fd_bo_new(ctx->screen->dev, batch->tessparam_size,
DRM_FREEDRENO_GEM_TYPE_KMEM, "tessparam");
0, "tessparam");
OUT_PKT4(ring, REG_A6XX_PC_TESSFACTOR_ADDR, 2);
OUT_RELOC(ring, batch->tessfactor_bo, 0, 0, 0);
src/gallium/drivers/freedreno/a6xx/fd6_program.c
+1 -1
View File
@@ -107,7 +107,7 @@ fd6_emit_shader(struct fd_context *ctx, struct fd_ringbuffer *ring,
uint32_t total_size =
ALIGN(per_fiber_size * fibers_per_sp, 1 << 12) * num_sp_cores;
ctx->pvtmem[so->pvtmem_per_wave].bo = fd_bo_new(
ctx->screen->dev, total_size, DRM_FREEDRENO_GEM_TYPE_KMEM,
ctx->screen->dev, total_size, 0,
"pvtmem_%s_%d", so->pvtmem_per_wave ? "per_wave" : "per_fiber",
per_fiber_size);
} else {
src/gallium/drivers/freedreno/a6xx/fd6_resource.c
+1 -3
View File
@@ -132,8 +132,6 @@ static void
setup_lrz(struct fd_resource *rsc)
{
struct fd_screen *screen = fd_screen(rsc->b.b.screen);
const uint32_t flags =
DRM_FREEDRENO_GEM_CACHE_WCOMBINE | DRM_FREEDRENO_GEM_TYPE_KMEM; /* TODO */
unsigned width0 = rsc->b.b.width0;
unsigned height0 = rsc->b.b.height0;
@@ -154,7 +152,7 @@ setup_lrz(struct fd_resource *rsc)
rsc->lrz_height = lrz_height;
rsc->lrz_width = lrz_pitch;
rsc->lrz_pitch = lrz_pitch;
rsc->lrz = fd_bo_new(screen->dev, size, flags, "lrz");
rsc->lrz = fd_bo_new(screen->dev, size, 0, "lrz");
}
static uint32_t
src/gallium/drivers/freedreno/freedreno_autotune.c
+1 -1
View File
@@ -251,7 +251,7 @@ fd_autotune_init(struct fd_autotune *at, struct fd_device *dev)
list_inithead(&at->lru);
at->results_mem = fd_bo_new(dev, sizeof(struct fd_autotune_results),
DRM_FREEDRENO_GEM_TYPE_KMEM, "autotune");
0, "autotune");
at->results = fd_bo_map(at->results_mem);
list_inithead(&at->pending_results);
src/gallium/drivers/freedreno/freedreno_resource.c
+1 -2
View File
@@ -196,8 +196,7 @@ realloc_bo(struct fd_resource *rsc, uint32_t size)
struct pipe_resource *prsc = &rsc->b.b;
struct fd_screen *screen = fd_screen(rsc->b.b.screen);
uint32_t flags =
DRM_FREEDRENO_GEM_CACHE_WCOMBINE | DRM_FREEDRENO_GEM_TYPE_KMEM |
COND(prsc->bind & PIPE_BIND_SCANOUT, DRM_FREEDRENO_GEM_SCANOUT);
COND(prsc->bind & PIPE_BIND_SCANOUT, FD_BO_SCANOUT);
/* TODO other flags? */
/* if we start using things other than write-combine,
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
+1 -2
View File
@@ -105,8 +105,7 @@ upload_shader_variant(struct ir3_shader_variant *v)
assert(!v->bo);
v->bo =
fd_bo_new(compiler->dev, v->info.size,
DRM_FREEDRENO_GEM_CACHE_WCOMBINE | DRM_FREEDRENO_GEM_TYPE_KMEM,
fd_bo_new(compiler->dev, v->info.size, 0,
"%s:%s", ir3_shader_stage(v), info->name);
/* Always include shaders in kernel crash dumps. */