AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

radv/video: Fix bitstreamStartOffset including dstBufferOffset

Browse Source 
The bitstreamStartOffset from the VK_QUERY_TYPE_VIDEO_ENCODE_FEEDBACK_KHR query in RADV is currently relative to the dstBuffer, and not dstBuffer + dstBufferOffset like the spec states.

To fix this, let's append the offset to the VA directly and not tell the encoder about the offset relative to the VA at all.

The Vulkan spec states:
"VK_VIDEO_ENCODE_FEEDBACK_BITSTREAM_BUFFER_OFFSET_BIT_KHR specifies that queries managed by the pool will capture the byte offset of the bitstream data written by the video encode operation to the bitstream buffer specified in VkVideoEncodeInfoKHR::dstBuffer relative to the offset specified in VkVideoEncodeInfoKHR::dstBufferOffset."

The relevant part being that is is relative to dstBufferOffset and not the start of the VkBuffer.

Signed-off-by: Autumn Ashton <misyl@froggi.es>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32452>
This commit is contained in:
Autumn Ashton
2024-12-03 07:00:26 +00:00
committed by Marge Bot
parent 1a7ebfd2a8
commit 7e9ea5c1b5
1 changed files with 2 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/vulkan/radv_video_enc.c
+2 -2
View File
@@ -1260,7 +1260,7 @@ radv_enc_bitstream(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffe
struct radv_device *device = radv_cmd_buffer_device(cmd_buffer);
const struct radv_physical_device *pdev = radv_device_physical(device);
struct radeon_cmdbuf *cs = cmd_buffer->cs;
uint64_t va = radv_buffer_get_va(buffer->bo) + buffer->offset;
uint64_t va = radv_buffer_get_va(buffer->bo) + buffer->offset + offset;
radv_cs_add_buffer(device->ws, cs, buffer->bo);
ENC_BEGIN;
@@ -1269,7 +1269,7 @@ radv_enc_bitstream(struct radv_cmd_buffer *cmd_buffer, struct radv_buffer *buffe
radeon_emit(cs, va >> 32);
radeon_emit(cs, va & 0xffffffff);
radeon_emit(cs, buffer->vk.size);
radeon_emit(cs, offset);
radeon_emit(cs, 0);
ENC_END;
}