freedreno: Used cached coherent for staging resources

These are really only accessed by the GPU once, so CPU access speed is
more important.  Especially for PIPE_MAP_READ.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11176>
This commit is contained in:
Rob Clark
2021-06-18 10:59:40 -07:00
committed by Marge Bot
parent 926ffea994
commit 7e088d3621
@@ -196,6 +196,7 @@ realloc_bo(struct fd_context *ctx, struct fd_resource *rsc, uint32_t size)
struct pipe_resource *prsc = &rsc->b.b;
struct fd_screen *screen = fd_screen(rsc->b.b.screen);
uint32_t flags =
COND(prsc->usage & PIPE_USAGE_STAGING, FD_BO_CACHED_COHERENT) |
COND(prsc->bind & PIPE_BIND_SCANOUT, FD_BO_SCANOUT);
/* TODO other flags? */