freedreno: Used cached coherent for staging resources
These are really only accessed by the GPU once, so CPU access speed is more important. Especially for PIPE_MAP_READ. Signed-off-by: Rob Clark <robdclark@chromium.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11176>
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@@ -196,6 +196,7 @@ realloc_bo(struct fd_context *ctx, struct fd_resource *rsc, uint32_t size)
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struct pipe_resource *prsc = &rsc->b.b;
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struct fd_screen *screen = fd_screen(rsc->b.b.screen);
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uint32_t flags =
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COND(prsc->usage & PIPE_USAGE_STAGING, FD_BO_CACHED_COHERENT) |
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COND(prsc->bind & PIPE_BIND_SCANOUT, FD_BO_SCANOUT);
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/* TODO other flags? */
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