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i965: Use WE_all for FB write header setup on Broadwell.

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I forgot to disable writemasking on the OR and MOV which set the render
target index and "source 0 alpha present to render target" bit.

Using get_element_ud is equivalent and avoids a line-wrap.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Cc: "10.2" <mesa-stable@lists.freedesktop.org>
This commit is contained in:
Kenneth Graunke
2014-05-20 14:52:39 -07:00
parent f50361cce7
commit 7d3985ca6c
1 changed files with 7 additions and 6 deletions
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src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+7 -6
View File
@@ -76,16 +76,17 @@ gen8_fs_generator::generate_fb_write(fs_inst *ir)
if (ir->target > 0 && key->replicate_alpha) {
/* Set "Source0 Alpha Present to RenderTarget" bit in the header. */
OR(vec1(retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD)),
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(1 << 11));
gen8_instruction *inst =
OR(get_element_ud(brw_message_reg(ir->base_mrf), 0),
vec1(retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD)),
brw_imm_ud(1 << 11));
gen8_set_mask_control(inst, BRW_MASK_DISABLE);
}
if (ir->target > 0) {
/* Set the render target index for choosing BLEND_STATE. */
MOV(retype(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, ir->base_mrf, 2),
BRW_REGISTER_TYPE_UD),
brw_imm_ud(ir->target));
MOV_RAW(brw_vec1_reg(BRW_MESSAGE_REGISTER_FILE, ir->base_mrf, 2),
brw_imm_ud(ir->target));
}
}