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radeonsi: add num_draws parameter into si_need_gfx_cs_space

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Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7056>
This commit is contained in:
Marek Olšák
2020-10-07 18:58:06 -04:00
committed by Marge Bot
parent 095ee8f867
commit 7cc939f7dd
8 changed files with 16 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/radeonsi/si_compute.c
+1 -1
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@@ -840,7 +840,7 @@ static void si_launch_grid(struct pipe_context *ctx, const struct pipe_grid_info
}
}
si_need_gfx_cs_space(sctx);
si_need_gfx_cs_space(sctx, 0);
/* If we're using a secure context, determine if cs must be secure or not */
if (unlikely(radeon_uses_secure_bos(sctx->ws))) {
src/gallium/drivers/radeonsi/si_compute_prim_discard.c
+1 -1
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@@ -1032,7 +1032,7 @@ si_prepare_prim_discard_or_split_draw(struct si_context *sctx, const struct pipe
unsigned need_compute_dw = 11 /* shader */ + 34 /* first draw */ +
24 * (num_subdraws - 1) + /* subdraws */
30; /* leave some space at the end */
unsigned need_gfx_dw = si_get_minimum_num_gfx_cs_dwords(sctx);
unsigned need_gfx_dw = si_get_minimum_num_gfx_cs_dwords(sctx, 0);
if (sctx->chip_class <= GFX7 || FORCE_REWIND_EMULATION)
need_gfx_dw += 9; /* NOP(2) + WAIT_REG_MEM(7), then chain */
src/gallium/drivers/radeonsi/si_cp_dma.c
+1 -1
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@@ -163,7 +163,7 @@ static void si_cp_dma_prepare(struct si_context *sctx, struct pipe_resource *dst
}
if (!(user_flags & SI_CPDMA_SKIP_CHECK_CS_SPACE))
si_need_gfx_cs_space(sctx);
si_need_gfx_cs_space(sctx, 0);
/* This must be done after need_cs_space. */
if (!(user_flags & SI_CPDMA_SKIP_BO_LIST_UPDATE)) {
src/gallium/drivers/radeonsi/si_gfx_cs.c
+2 -2
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@@ -30,7 +30,7 @@
#include "util/u_upload_mgr.h"
/* initialize */
void si_need_gfx_cs_space(struct si_context *ctx)
void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws)
{
struct radeon_cmdbuf *cs = ctx->gfx_cs;
@@ -54,7 +54,7 @@ void si_need_gfx_cs_space(struct si_context *ctx)
ctx->gtt = 0;
ctx->vram = 0;
unsigned need_dwords = si_get_minimum_num_gfx_cs_dwords(ctx);
unsigned need_dwords = si_get_minimum_num_gfx_cs_dwords(ctx, num_draws);
if (!ctx->ws->cs_check_space(cs, need_dwords, false))
si_flush_gfx_cs(ctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
}
src/gallium/drivers/radeonsi/si_perfcounter.c
+1 -1
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@@ -941,7 +941,7 @@ static void si_pc_query_resume(struct si_context *sctx, struct si_query *squery)
if (!si_query_buffer_alloc(sctx, &query->buffer, NULL, query->result_size))
return;
si_need_gfx_cs_space(sctx);
si_need_gfx_cs_space(sctx, 0);
if (query->shaders)
si_pc_emit_shaders(sctx, query->shaders);
src/gallium/drivers/radeonsi/si_pipe.h
+6 -3
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@@ -1433,7 +1433,7 @@ void si_flush_gfx_cs(struct si_context *ctx, unsigned flags, struct pipe_fence_h
void si_allocate_gds(struct si_context *ctx);
void si_set_tracked_regs_to_clear_state(struct si_context *ctx);
void si_begin_new_gfx_cs(struct si_context *ctx, bool first_cs);
void si_need_gfx_cs_space(struct si_context *ctx);
void si_need_gfx_cs_space(struct si_context *ctx, unsigned num_draws);
void si_unref_sdma_uploads(struct si_context *sctx);
/* si_gpu_load.c */
@@ -1593,14 +1593,17 @@ static inline unsigned si_tile_mode_index(struct si_texture *tex, unsigned level
return tex->surface.u.legacy.tiling_index[level];
}
static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx)
static inline unsigned si_get_minimum_num_gfx_cs_dwords(struct si_context *sctx,
unsigned num_draws)
{
/* Don't count the needed CS space exactly and just use an upper bound.
*
* Also reserve space for stopping queries at the end of IB, because
* the number of active queries is unlimited in theory.
*
* Both indexed and non-indexed draws use 6 dwords per draw.
*/
return 2048 + sctx->num_cs_dw_queries_suspend;
return 2048 + sctx->num_cs_dw_queries_suspend + num_draws * 6;
}
static inline void si_context_add_resource_size(struct si_context *sctx, struct pipe_resource *r)
src/gallium/drivers/radeonsi/si_query.c
+3 -3
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@@ -887,7 +887,7 @@ static void si_query_hw_emit_start(struct si_context *sctx, struct si_query_hw *
sctx->num_pipeline_stat_queries++;
if (query->b.type != SI_QUERY_TIME_ELAPSED_SDMA)
si_need_gfx_cs_space(sctx);
si_need_gfx_cs_space(sctx, 0);
va = query->buffer.buf->gpu_address + query->buffer.results_end;
query->ops->emit_start(sctx, query, query->buffer.buf, va);
@@ -965,7 +965,7 @@ static void si_query_hw_emit_stop(struct si_context *sctx, struct si_query_hw *q
/* The queries which need begin already called this in begin_query. */
if (query->flags & SI_QUERY_HW_FLAG_NO_START) {
si_need_gfx_cs_space(sctx);
si_need_gfx_cs_space(sctx, 0);
if (!si_query_buffer_alloc(sctx, &query->buffer, query->ops->prepare_buffer,
query->result_size))
return;
@@ -1644,7 +1644,7 @@ void si_resume_queries(struct si_context *sctx)
struct si_query *query;
/* Check CS space here. Resuming must not be interrupted by flushes. */
si_need_gfx_cs_space(sctx);
si_need_gfx_cs_space(sctx, 0);
LIST_FOR_EACH_ENTRY (query, &sctx->active_queries, active_list)
query->ops->resume(sctx, query);
src/gallium/drivers/radeonsi/si_state_draw.c
+1 -1
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@@ -2043,7 +2043,7 @@ static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *i
if (unlikely(sctx->do_update_shaders && !si_update_shaders(sctx)))
goto return_cleanup;
si_need_gfx_cs_space(sctx);
si_need_gfx_cs_space(sctx, 0);
/* If we're using a secure context, determine if cs must be secure or not */
if (unlikely(radeon_uses_secure_bos(sctx->ws))) {