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radeonsi: remove shader and compute get param

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Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33176>
This commit is contained in:
Qiang Yu
2025-01-22 10:03:19 +08:00
parent ba2e6ae8f8
commit 7ca3618c01
1 changed files with 0 additions and 259 deletions
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src/gallium/drivers/radeonsi/si_get.c
-259
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@@ -56,80 +56,6 @@ si_is_compute_copy_faster(struct pipe_screen *pscreen,
return false;
}
static int si_get_shader_param(struct pipe_screen *pscreen, enum pipe_shader_type shader,
enum pipe_shader_cap param)
{
struct si_screen *sscreen = (struct si_screen *)pscreen;
if (shader == PIPE_SHADER_MESH ||
shader == PIPE_SHADER_TASK)
return 0;
switch (param) {
/* Shader limits. */
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
return 16384;
case PIPE_SHADER_CAP_MAX_INPUTS:
return shader == PIPE_SHADER_VERTEX ? SI_MAX_ATTRIBS : 32;
case PIPE_SHADER_CAP_MAX_OUTPUTS:
return shader == PIPE_SHADER_FRAGMENT ? 8 : 32;
case PIPE_SHADER_CAP_MAX_TEMPS:
return 256; /* Max native temporaries. */
case PIPE_SHADER_CAP_MAX_CONST_BUFFER0_SIZE:
return 1 << 26; /* 64 MB */
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
return SI_NUM_CONST_BUFFERS;
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
return SI_NUM_SAMPLERS;
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
return SI_NUM_SHADER_BUFFERS;
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return SI_NUM_IMAGES;
case PIPE_SHADER_CAP_SUPPORTED_IRS:
if (shader == PIPE_SHADER_COMPUTE) {
return (1 << PIPE_SHADER_IR_NATIVE) |
(1 << PIPE_SHADER_IR_NIR) |
(1 << PIPE_SHADER_IR_TGSI);
}
return (1 << PIPE_SHADER_IR_TGSI) |
(1 << PIPE_SHADER_IR_NIR);
/* Supported boolean features. */
case PIPE_SHADER_CAP_CONT_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
case PIPE_SHADER_CAP_INTEGERS:
case PIPE_SHADER_CAP_INT64_ATOMICS:
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
return 1;
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
/* We need f16c for fast FP16 conversions in glUniform. */
if (!util_get_cpu_caps()->has_f16c)
return 0;
FALLTHROUGH;
case PIPE_SHADER_CAP_FP16:
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
case PIPE_SHADER_CAP_INT16:
return sscreen->nir_options->lower_mediump_io != NULL;
/* Unsupported boolean features. */
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
return 0;
}
return 0;
}
static const void *si_get_compiler_options(struct pipe_screen *screen, enum pipe_shader_ir ir,
enum pipe_shader_type shader)
{
@@ -812,189 +738,6 @@ static bool si_vid_is_target_buffer_supported(struct pipe_screen *screen,
return si_vid_is_format_supported(screen, format, profile, entrypoint);
}
static int si_get_compute_param(struct pipe_screen *screen,
enum pipe_compute_cap param, void *ret)
{
struct si_screen *sscreen = (struct si_screen *)screen;
// TODO: select these params by asic
switch (param) {
case PIPE_COMPUTE_CAP_IR_TARGET: {
const char *gpu, *triple;
triple = "amdgcn-mesa-mesa3d";
gpu = ac_get_llvm_processor_name(sscreen->info.family);
if (ret) {
sprintf(ret, "%s-%s", gpu, triple);
}
/* +2 for dash and terminating NIL byte */
return (strlen(triple) + strlen(gpu) + 2) * sizeof(char);
}
case PIPE_COMPUTE_CAP_GRID_DIMENSION:
if (ret) {
uint64_t *grid_dimension = ret;
grid_dimension[0] = 3;
}
return 1 * sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
if (ret) {
uint64_t *grid_size = ret;
/* Use this size, so that internal counters don't overflow 64 bits. */
grid_size[0] = UINT32_MAX;
grid_size[1] = UINT16_MAX;
grid_size[2] = UINT16_MAX;
}
return 3 * sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
if (ret) {
uint64_t *block_size = ret;
block_size[0] = 1024;
block_size[1] = 1024;
block_size[2] = 1024;
}
return 3 * sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE_CLOVER:
if (ret) {
uint64_t *block_size = ret;
block_size[0] = 256;
block_size[1] = 256;
block_size[2] = 256;
}
return 3 * sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
if (ret) {
uint64_t *max_threads_per_block = ret;
*max_threads_per_block = 1024;
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK_CLOVER:
if (ret) {
uint64_t *max_threads_per_block = ret;
*max_threads_per_block = 256;
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
if (ret) {
uint32_t *address_bits = ret;
address_bits[0] = 64;
}
return 1 * sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
if (ret) {
uint64_t *max_global_size = ret;
uint64_t max_mem_alloc_size;
si_get_compute_param(screen, PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE,
&max_mem_alloc_size);
/* In OpenCL, the MAX_MEM_ALLOC_SIZE must be at least
* 1/4 of the MAX_GLOBAL_SIZE. Since the
* MAX_MEM_ALLOC_SIZE is fixed for older kernels,
* make sure we never report more than
* 4 * MAX_MEM_ALLOC_SIZE.
*/
*max_global_size =
MIN2(4 * max_mem_alloc_size, sscreen->info.max_heap_size_kb * 1024ull);
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
if (ret) {
uint64_t *max_local_size = ret;
/* Value reported by the closed source driver. */
if (sscreen->info.gfx_level == GFX6)
*max_local_size = 32 * 1024;
else
*max_local_size = 64 * 1024;
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
if (ret) {
uint64_t *max_input_size = ret;
/* Value reported by the closed source driver. */
*max_input_size = 1024;
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
if (ret) {
uint64_t *max_mem_alloc_size = ret;
/* Return 1/4 of the heap size as the maximum because the max size is not practically
* allocatable.
*/
*max_mem_alloc_size = (sscreen->info.max_heap_size_kb / 4) * 1024ull;
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
if (ret) {
uint32_t *max_clock_frequency = ret;
*max_clock_frequency = sscreen->info.max_gpu_freq_mhz;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS:
if (ret) {
uint32_t *max_compute_units = ret;
*max_compute_units = sscreen->info.num_cu;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
if (ret) {
uint32_t *images_supported = ret;
*images_supported = 0;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
break; /* unused */
case PIPE_COMPUTE_CAP_MAX_SUBGROUPS: {
if (ret) {
uint32_t *max_subgroups = ret;
unsigned threads = 1024;
unsigned subgroup_size;
if (sscreen->debug_flags & DBG(W64_CS) || sscreen->info.gfx_level < GFX10)
subgroup_size = 64;
else
subgroup_size = 32;
*max_subgroups = threads / subgroup_size;
}
return sizeof(uint32_t);
}
case PIPE_COMPUTE_CAP_SUBGROUP_SIZES:
if (ret) {
uint32_t *subgroup_size = ret;
if (sscreen->debug_flags & DBG(W32_CS))
*subgroup_size = 32;
else if (sscreen->debug_flags & DBG(W64_CS))
*subgroup_size = 64;
else
*subgroup_size = sscreen->info.gfx_level < GFX10 ? 64 : 64 | 32;
}
return sizeof(uint32_t);
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
if (ret) {
uint64_t *max_variable_threads_per_block = ret;
*max_variable_threads_per_block = SI_MAX_VARIABLE_THREADS_PER_BLOCK;
}
return sizeof(uint64_t);
}
fprintf(stderr, "unknown PIPE_COMPUTE_CAP %d\n", param);
return 0;
}
static uint64_t si_get_timestamp(struct pipe_screen *screen)
{
struct si_screen *sscreen = (struct si_screen *)screen;
@@ -1113,9 +856,7 @@ void si_init_screen_get_functions(struct si_screen *sscreen)
sscreen->b.get_screen_fd = si_get_screen_fd;
sscreen->b.is_compute_copy_faster = si_is_compute_copy_faster;
sscreen->b.driver_thread_add_job = si_driver_thread_add_job;
sscreen->b.get_compute_param = si_get_compute_param;
sscreen->b.get_timestamp = si_get_timestamp;
sscreen->b.get_shader_param = si_get_shader_param;
sscreen->b.get_compiler_options = si_get_compiler_options;
sscreen->b.get_device_uuid = si_get_device_uuid;
sscreen->b.get_driver_uuid = si_get_driver_uuid;