asahi: fix data valid tracking

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26963>

src/gallium/drivers/asahi/agx_batch.c

@@ -6,6 +6,7 @@
 
 #include <xf86drm.h>
 #include "asahi/lib/decode.h"
+#include "util/bitset.h"
 #include "util/u_dynarray.h"
 #include "agx_state.h"
 
@@ -476,7 +477,8 @@ agx_batch_reads(struct agx_batch *batch, struct agx_resource *rsrc)
 }
 
 void
-agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc)
+agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc,
+                 unsigned level)
 {
    struct agx_context *ctx = batch->ctx;
    struct agx_batch *writer = agx_writer_get(ctx, rsrc->bo->handle);
@@ -485,6 +487,8 @@ agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc)
 
    agx_flush_readers_except(ctx, rsrc, batch, "Write from other batch", false);
 
+   BITSET_SET(rsrc->data_valid, level);
+
    /* Nothing to do if we're already writing */
    if (writer == batch)
       return;

src/gallium/drivers/asahi/agx_pipe.c

@@ -661,11 +661,10 @@ agx_batch_track_image(struct agx_batch *batch, struct pipe_image_view *image)
    struct agx_resource *rsrc = agx_resource(image->resource);
 
    if (image->shader_access & PIPE_IMAGE_ACCESS_WRITE) {
-      agx_batch_writes(batch, rsrc);
-
       bool is_buffer = rsrc->base.target == PIPE_BUFFER;
       unsigned level = is_buffer ? 0 : image->u.tex.level;
-      BITSET_SET(rsrc->data_valid, level);
+
+      agx_batch_writes(batch, rsrc, level);
 
       if (is_buffer) {
          util_range_add(&rsrc->base, &rsrc->valid_buffer_range, 0,

src/gallium/drivers/asahi/agx_state.c

@@ -3085,13 +3085,10 @@ agx_batch_init_state(struct agx_batch *batch)
       unsigned level = batch->key.zsbuf->u.tex.level;
       struct agx_resource *rsrc = agx_resource(batch->key.zsbuf->texture);
 
-      agx_batch_writes(batch, rsrc);
-      BITSET_SET(rsrc->data_valid, level);
+      agx_batch_writes(batch, rsrc, level);
 
-      if (rsrc->separate_stencil) {
-         agx_batch_writes(batch, rsrc->separate_stencil);
-         BITSET_SET(rsrc->separate_stencil->data_valid, level);
-      }
+      if (rsrc->separate_stencil)
+         agx_batch_writes(batch, rsrc->separate_stencil, level);
    }
 
    for (unsigned i = 0; i < batch->key.nr_cbufs; ++i) {
@@ -3102,8 +3099,7 @@ agx_batch_init_state(struct agx_batch *batch)
          if (agx_resource_valid(rsrc, level))
             batch->load |= PIPE_CLEAR_COLOR0 << i;
 
-         agx_batch_writes(batch, rsrc);
-         BITSET_SET(rsrc->data_valid, batch->key.cbufs[i]->u.tex.level);
+         agx_batch_writes(batch, rsrc, batch->key.cbufs[i]->u.tex.level);
       }
    }
 
@@ -3528,7 +3524,7 @@ agx_batch_geometry_state(struct agx_batch *batch)
          .heap = agx_resource(ctx->heap)->bo->ptr.gpu,
       };
 
-      agx_batch_writes(batch, agx_resource(ctx->heap));
+      agx_batch_writes(batch, agx_resource(ctx->heap), 0);
 
       batch->geometry_state =
          agx_pool_upload_aligned(&batch->pool, &state, sizeof(state), 8);
@@ -3608,7 +3604,7 @@ agx_batch_geometry_params(struct agx_batch *batch, uint64_t input_index_buffer,
 
       if (rsrc) {
          params.xfb_offs_ptrs[i] = rsrc->bo->ptr.gpu;
-         agx_batch_writes(batch, rsrc);
+         agx_batch_writes(batch, rsrc, 0);
       } else {
          params.xfb_offs_ptrs[i] = 0;
       }
@@ -4412,7 +4408,7 @@ agx_launch(struct agx_batch *batch, const struct pipe_grid_info *info,
          continue;
 
       struct agx_resource *buffer = agx_resource(*res);
-      agx_batch_writes(batch, buffer);
+      agx_batch_writes(batch, buffer, 0);
    }
 
    agx_batch_add_bo(batch, cs->bo);

src/gallium/drivers/asahi/agx_state.h

@@ -931,7 +931,8 @@ void agx_sync_batch_for_reason(struct agx_context *ctx, struct agx_batch *batch,
 
 /* Use these instead of batch_add_bo for proper resource tracking */
 void agx_batch_reads(struct agx_batch *batch, struct agx_resource *rsrc);
-void agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc);
+void agx_batch_writes(struct agx_batch *batch, struct agx_resource *rsrc,
+                      unsigned level);
 void agx_batch_track_image(struct agx_batch *batch,
                            struct pipe_image_view *image);
 

src/gallium/drivers/asahi/agx_streamout.c

@@ -108,7 +108,7 @@ agx_batch_get_so_address(struct agx_batch *batch, unsigned buffer,
 
    /* Otherwise, write the target */
    struct agx_resource *rsrc = agx_resource(target->buffer);
-   agx_batch_writes(batch, rsrc);
+   agx_batch_writes(batch, rsrc, 0);
 
    *size = target->buffer_size;
    return rsrc->bo->ptr.gpu + target->buffer_offset;

src/gallium/drivers/asahi/agx_uniforms.c

@@ -26,7 +26,7 @@ agx_shader_buffer_ptr(struct agx_batch *batch, struct pipe_shader_buffer *sb)
       struct agx_resource *rsrc = agx_resource(sb->buffer);
 
       /* Assume SSBOs are written. TODO: Optimize read-only SSBOs */
-      agx_batch_writes(batch, rsrc);
+      agx_batch_writes(batch, rsrc, 0);
 
       return rsrc->bo->ptr.gpu + sb->buffer_offset;
    } else {