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turnip: Apply the RB_DBG_ECO_CNTL_blit workaround.

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On blob v512.490 on a615, using WRAP_GPU_ID to fake GPU versions, I see
0x41 used everywhere, except for BLIT_OP_SCALE on a630.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19794>
This commit is contained in:
Emma Anholt
2022-10-12 09:15:23 -07:00
committed by Marge Bot
parent 9076b38610
commit 7befecf500
2 changed files with 20 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
src/freedreno/vulkan/tu_clear_blit.c
View File

@@ -413,8 +413,25 @@ r2d_teardown(struct tu_cmd_buffer *cmd,
static void
r2d_run(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
{
if (cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL_blit !=
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL) {
/* This a non-context register, so we have to WFI before changing. */
tu_cs_emit_wfi(cs);
tu_cs_emit_write_reg(
cs, REG_A6XX_RB_DBG_ECO_CNTL,
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL_blit);
}
tu_cs_emit_pkt7(cs, CP_BLIT, 1);
tu_cs_emit(cs, CP_BLIT_0_OP(BLIT_OP_SCALE));
if (cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL_blit !=
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL) {
tu_cs_emit_wfi(cs);
tu_cs_emit_write_reg(
cs, REG_A6XX_RB_DBG_ECO_CNTL,
cmd->device->physical_device->info->a6xx.magic.RB_DBG_ECO_CNTL);
}
}
/* r3d_ = shader path operations */
@@ -3189,8 +3206,7 @@ store_cp_blit(struct tu_cmd_buffer *cmd,
/* Wait for CACHE_INVALIDATE to land */
tu_cs_emit_wfi(cs);
tu_cs_emit_pkt7(cs, CP_BLIT, 1);
tu_cs_emit(cs, CP_BLIT_0_OP(BLIT_OP_SCALE));
r2d_run(cmd, cs);
/* CP_BLIT writes to the CCU, unlike CP_EVENT_WRITE::BLIT which writes to
* sysmem, and we generally assume that GMEM renderpasses leave their

3
src/freedreno/vulkan/tu_cmd_buffer.c
View File

@@ -934,7 +934,8 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_regs(cs,
A6XX_RB_CCU_CNTL(.color_offset = phys_dev->ccu_offset_bypass));
cmd->state.ccu_state = TU_CMD_CCU_SYSMEM;
tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL, 0x00100000);
tu_cs_emit_write_reg(cs, REG_A6XX_RB_DBG_ECO_CNTL,
phys_dev->info->a6xx.magic.RB_DBG_ECO_CNTL);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_FLOAT_CNTL, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_SP_DBG_ECO_CNTL,
phys_dev->info->a6xx.magic.SP_DBG_ECO_CNTL);