r600g/llvm: tgsi to llvm emits stream output intrinsics.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
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committed by
Tom Stellard
parent
ce34ff1ad7
commit
7b20526466
@@ -161,4 +161,6 @@ void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t word0
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output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
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output->inst = EG_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
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output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
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output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
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output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
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}
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@@ -2967,4 +2967,6 @@ void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t wor
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output->end_of_program = G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
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output->inst = R600_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
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output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
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output->array_size = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_ARRAY_SIZE(word1);
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output->comp_mask = G_SQ_CF_ALLOC_EXPORT_WORD1_BUF_COMP_MASK(word1);
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}
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@@ -240,11 +240,43 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context * bld_base)
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{
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struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
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struct lp_build_context * base = &bld_base->base;
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struct pipe_stream_output_info * so = ctx->stream_outputs;
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unsigned i;
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unsigned color_count = 0;
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boolean has_color = false;
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if (ctx->type == TGSI_PROCESSOR_VERTEX && so->num_outputs) {
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for (i = 0; i < so->num_outputs; i++) {
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unsigned register_index = so->output[i].register_index;
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unsigned start_component = so->output[i].start_component;
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unsigned num_components = so->output[i].num_components;
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unsigned dst_offset = so->output[i].dst_offset;
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unsigned chan;
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LLVMValueRef elements[4];
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if (dst_offset < start_component) {
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for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
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elements[chan] = LLVMBuildLoad(base->gallivm->builder,
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ctx->soa.outputs[register_index][(chan + start_component) % TGSI_NUM_CHANNELS], "");
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}
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start_component = 0;
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} else {
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for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
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elements[chan] = LLVMBuildLoad(base->gallivm->builder,
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ctx->soa.outputs[register_index][chan], "");
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}
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}
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LLVMValueRef output = lp_build_gather_values(base->gallivm, elements, 4);
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LLVMValueRef args[4];
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args[0] = output;
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args[1] = lp_build_const_int32(base->gallivm, dst_offset - start_component);
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args[2] = lp_build_const_int32(base->gallivm, so->output[i].output_buffer);
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args[3] = lp_build_const_int32(base->gallivm, ((1 << num_components) - 1) << start_component);
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lp_build_intrinsic(base->gallivm->builder, "llvm.R600.store.stream.output",
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LLVMVoidTypeInContext(base->gallivm->context), args, 4);
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}
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}
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/* Add the necessary export instructions */
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for (i = 0; i < ctx->output_reg_count; i++) {
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unsigned chan;
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@@ -1416,6 +1416,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
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radeon_llvm_ctx.color_buffer_count = MAX2(key.nr_cbufs , 1);
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radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
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radeon_llvm_ctx.fs_color_all = shader->fs_write_all && (rscreen->chip_class >= EVERGREEN);
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radeon_llvm_ctx.stream_outputs = &so;
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mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
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if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
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dump = 1;
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@@ -1572,7 +1573,7 @@ static int r600_shader_from_tgsi(struct r600_screen *rscreen,
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}
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/* Add stream outputs. */
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if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs) {
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if (ctx.type == TGSI_PROCESSOR_VERTEX && so.num_outputs && !use_llvm) {
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unsigned so_gpr[PIPE_MAX_SHADER_OUTPUTS];
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/* Sanity checking. */
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@@ -60,6 +60,7 @@ struct radeon_llvm_context {
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unsigned two_side;
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struct r600_shader_io * r600_inputs;
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struct r600_shader_io * r600_outputs;
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struct pipe_stream_output_info *stream_outputs;
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unsigned color_buffer_count;
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unsigned fs_color_all;
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