anv: Set MOCS in 3DSTATE_CONSTANT_XS even if there isn't a buffer.
This avoids MOCS != 0 assertions in later patches. iris also does this, and we do it for the 3DSTATE_CONSTANT_ALL packet path as well. It's a bit pointless, but it should hopefully be harmless also. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13480>
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@@ -3178,30 +3178,31 @@ cmd_buffer_emit_push_constant(struct anv_cmd_buffer *cmd_buffer,
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anv_batch_emit(&cmd_buffer->batch, GENX(3DSTATE_CONSTANT_VS), c) {
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c._3DCommandSubOpcode = push_constant_opcodes[stage];
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/* Set MOCS, except on Gfx8, because the Broadwell PRM says:
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*
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* "Constant Buffer Object Control State must be always
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* programmed to zero."
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*
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* This restriction does not exist on any newer platforms.
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*
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* We only have one MOCS field for the whole packet, not one per
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* buffer. We could go out of our way here to walk over all of
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* the buffers and see if any of them are used externally and use
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* the external MOCS. However, the notion that someone would use
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* the same bit of memory for both scanout and a UBO is nuts.
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*
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* Let's not bother and assume it's all internal.
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*/
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#if GFX_VER >= 9
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c.MOCS = mocs;
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#elif GFX_VER < 8
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c.ConstantBody.MOCS = mocs;
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#endif
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if (anv_pipeline_has_stage(pipeline, stage)) {
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const struct anv_pipeline_bind_map *bind_map =
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&pipeline->shaders[stage]->bind_map;
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/* Set MOCS, except on Gfx8, because the Broadwell PRM says:
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*
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* "Constant Buffer Object Control State must be always programmed
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* to zero."
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*
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* This restriction does not exist on any newer platforms.
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*
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* We only have one MOCS field for the whole packet, not one per
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* buffer. We could go out of our way here to walk over all of the
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* buffers and see if any of them are used externally and use the
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* external MOCS. However, the notion that someone would use the
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* same bit of memory for both scanout and a UBO is nuts. Let's not
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* bother and assume it's all internal.
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*/
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#if GFX_VER >= 9
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c.MOCS = mocs;
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#elif GFX_VER < 8
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c.ConstantBody.MOCS = mocs;
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#endif
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#if GFX_VERx10 >= 75
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/* The Skylake PRM contains the following restriction:
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*
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