iris: Use coherent allocation for PIPE_RESOURCE_STAGING
On !llc machines (Atoms), reading from a linear buffers is slow and so copying from one resource into the linear staging buffer is still slow. However, we can tell the GPU to snoop the CPU cache when reading from and writing to the staging buffer eliminating the slow uncached reads. Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
committed by
Kenneth Graunke
parent
01b224047b
commit
797fb6c6ac
@@ -521,6 +521,12 @@ bo_alloc_internal(struct iris_bufmgr *bufmgr,
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if (flags & BO_ALLOC_ZEROED)
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zeroed = true;
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if ((flags & BO_ALLOC_COHERENT) && !bufmgr->has_llc) {
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bo_size = MAX2(ALIGN(size, page_size), page_size);
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bucket = NULL;
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goto skip_cache;
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}
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/* Round the allocated size up to a power of two number of pages. */
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bucket = bucket_for_size(bufmgr, size);
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@@ -579,6 +585,7 @@ retry:
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bo->gtt_offset = 0ull;
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}
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} else {
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skip_cache:
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bo = bo_calloc();
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if (!bo)
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goto err;
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@@ -644,6 +651,17 @@ retry:
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mtx_unlock(&bufmgr->lock);
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if ((flags & BO_ALLOC_COHERENT) && !bo->cache_coherent) {
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struct drm_i915_gem_caching arg = {
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.handle = bo->gem_handle,
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.caching = 1,
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};
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if (drm_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg) == 0) {
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bo->cache_coherent = true;
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bo->reusable = false;
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}
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}
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DBG("bo_create: buf %d (%s) %llub\n", bo->gem_handle, bo->name,
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(unsigned long long) size);
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@@ -191,6 +191,7 @@ struct iris_bo {
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};
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#define BO_ALLOC_ZEROED (1<<0)
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#define BO_ALLOC_COHERENT (1<<1)
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/**
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* Allocate a buffer object.
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@@ -592,6 +592,10 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
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const char *name = "miptree";
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enum iris_memory_zone memzone = IRIS_MEMZONE_OTHER;
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unsigned int flags = 0;
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if (templ->usage == PIPE_USAGE_STAGING)
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flags |= BO_ALLOC_COHERENT;
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/* These are for u_upload_mgr buffers only */
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assert(!(templ->flags & (IRIS_RESOURCE_FLAG_SHADER_MEMZONE |
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IRIS_RESOURCE_FLAG_SURFACE_MEMZONE |
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@@ -600,7 +604,7 @@ iris_resource_create_with_modifiers(struct pipe_screen *pscreen,
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res->bo = iris_bo_alloc_tiled(screen->bufmgr, name, res->surf.size_B,
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memzone,
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isl_tiling_to_i915_tiling(res->surf.tiling),
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res->surf.row_pitch_B, 0);
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res->surf.row_pitch_B, flags);
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if (!res->bo)
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goto fail;
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