nvc0: expose spirv support

required for OpenCL

v2: adjust to changes in previous commits
v3: properly convert to NIR in nvc0_cp_state_create

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Pierre Moreau <pierre.morrow@free.fr> (v1)

src/gallium/drivers/nouveau/nouveau_screen.c

@@ -23,6 +23,8 @@
 #include "nouveau_mm.h"
 #include "nouveau_buffer.h"
 
+#include <compiler/glsl_types.h>
+
 /* XXX this should go away */
 #include "state_tracker/drm_driver.h"
 
@@ -187,6 +189,9 @@ nouveau_screen_init(struct nouveau_screen *screen, struct nouveau_device *dev)
       nouveau_mesa_debug = atoi(nv_dbg);
 
    screen->prefer_nir = debug_get_bool_option("NV50_PROG_USE_NIR", false);
+   screen->force_enable_cl = debug_get_bool_option("NOUVEAU_ENABLE_CL", false);
+   if (screen->force_enable_cl)
+      glsl_type_singleton_init_or_ref();
 
    /* These must be set before any failure is possible, as the cleanup
     * paths assume they're responsible for deleting them.
@@ -279,6 +284,9 @@ nouveau_screen_fini(struct nouveau_screen *screen)
 {
    int fd = screen->drm->fd;
 
+   if (screen->force_enable_cl)
+      glsl_type_singleton_decref();
+
    nouveau_mm_destroy(screen->mm_GART);
    nouveau_mm_destroy(screen->mm_VRAM);
 

src/gallium/drivers/nouveau/nouveau_screen.h

@@ -69,6 +69,7 @@ struct nouveau_screen {
    struct disk_cache *disk_shader_cache;
 
    bool prefer_nir;
+   bool force_enable_cl;
 
 #ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
    union {

src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

@@ -418,9 +418,13 @@ nvc0_screen_get_shader_param(struct pipe_screen *pscreen,
    switch (param) {
    case PIPE_SHADER_CAP_PREFERRED_IR:
       return screen->prefer_nir ? PIPE_SHADER_IR_NIR : PIPE_SHADER_IR_TGSI;
-   case PIPE_SHADER_CAP_SUPPORTED_IRS:
-      return 1 << PIPE_SHADER_IR_TGSI |
-             1 << PIPE_SHADER_IR_NIR;
+   case PIPE_SHADER_CAP_SUPPORTED_IRS: {
+      uint32_t irs = 1 << PIPE_SHADER_IR_TGSI |
+                     1 << PIPE_SHADER_IR_NIR;
+      if (screen->force_enable_cl)
+         irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
+      return irs;
+   }
    case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
    case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
    case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:

src/gallium/drivers/nouveau/nvc0/nvc0_state.c

@@ -28,6 +28,7 @@
 
 #include "tgsi/tgsi_parse.h"
 #include "compiler/nir/nir.h"
+#include "compiler/nir/nir_serialize.h"
 
 #include "nvc0/nvc0_stateobj.h"
 #include "nvc0/nvc0_context.h"
@@ -740,6 +741,15 @@ nvc0_cp_state_create(struct pipe_context *pipe,
    case PIPE_SHADER_IR_NIR:
       prog->pipe.ir.nir = (nir_shader *)cso->prog;
       break;
+   case PIPE_SHADER_IR_NIR_SERIALIZED: {
+      struct blob_reader reader;
+      const struct pipe_binary_program_header *hdr = cso->prog;
+
+      blob_reader_init(&reader, hdr->blob, hdr->num_bytes);
+      prog->pipe.ir.nir = nir_deserialize(NULL, pipe->screen->get_compiler_options(pipe->screen, PIPE_SHADER_IR_NIR, PIPE_SHADER_COMPUTE), &reader);
+      prog->pipe.type = PIPE_SHADER_IR_NIR;
+      break;
+   }
    default:
       assert(!"unsupported IR!");
       free(prog);