intel/compiler: add a spec note about L1WT types being uncached

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33755>

src/intel/compiler/brw_eu_defines.h

@@ -1721,6 +1721,9 @@ enum PACKED xe2_lsc_cache_store {
    XE2_LSC_CACHE_STORE_L1UC_L3UC = 2,
    /* Override to L1 uncached and L3 cached */
    XE2_LSC_CACHE_STORE_L1UC_L3WB = 4,
+   /* From BSpec: 71167 for L1WT_L3UC and L1WT_L3WB:
+    * "L1 will be uncached rather than write-through."
+    */
    /* Override to L1 write-through and L3 uncached */
    XE2_LSC_CACHE_STORE_L1WT_L3UC = 6,
    /* Override to L1 write-through and L3 cached */