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broadcom/vc5: Disable early Z when the stencil func isn't ALWAYS.

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Apparently the other funcs will have observable differences when early Z
is enabled.

Fixes (new) simulator assertion failures in
dEQP-GLES3.functional.rasterizer_discard.basic.clear_depth.
This commit is contained in:
Eric Anholt
2017-12-28 15:42:14 -08:00
parent 635131a238
commit 7836c85919
1 changed files with 3 additions and 1 deletions
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src/gallium/drivers/vc5/vc5_state.c
+3 -1
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@@ -165,8 +165,10 @@ vc5_create_depth_stencil_alpha_state(struct pipe_context *pctx,
cso->depth.func == PIPE_FUNC_LEQUAL) &&
(!cso->stencil[0].enabled ||
(cso->stencil[0].zfail_op == PIPE_STENCIL_OP_KEEP &&
cso->stencil[0].func == PIPE_FUNC_ALWAYS &&
(!cso->stencil[1].enabled ||
cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP))));
(cso->stencil[1].zfail_op == PIPE_STENCIL_OP_KEEP &&
cso->stencil[1].func == PIPE_FUNC_ALWAYS)))));
}
const struct pipe_stencil_state *front = &cso->stencil[0];