intel: Transition intel_region_map() to being a miptree operation.
I'm trying to move us away from the region structure, and all the callers are currently dereferencing a miptree to get the region. In this change, the map_refcount is dropped. However, the bo->virtual is itself map refcounted, so that's already dealt with. Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
This commit is contained in:
@@ -948,9 +948,9 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
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*
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* Note: the clear value for MCS buffers is all 1's, so we memset to 0xff.
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*/
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void *data = intel_region_map(intel, mt->mcs_mt->region, 0);
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void *data = intel_miptree_map_raw(intel, mt->mcs_mt);
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memset(data, 0xff, mt->mcs_mt->region->bo->size);
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intel_region_unmap(intel, mt->mcs_mt->region);
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intel_miptree_unmap_raw(intel, mt->mcs_mt);
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return mt->mcs_mt;
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}
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@@ -1192,6 +1192,34 @@ intel_miptree_upsample(struct intel_context *intel,
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intel_miptree_slice_set_needs_hiz_resolve(mt, 0, 0);
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}
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void *
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intel_miptree_map_raw(struct intel_context *intel, struct intel_mipmap_tree *mt)
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{
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drm_intel_bo *bo = mt->region->bo;
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if (unlikely(INTEL_DEBUG & DEBUG_PERF)) {
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if (drm_intel_bo_busy(bo)) {
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perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
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}
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}
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intel_flush(&intel->ctx);
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if (mt->region->tiling != I915_TILING_NONE)
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drm_intel_gem_bo_map_gtt(bo);
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else
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drm_intel_bo_map(bo, true);
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return bo->virtual;
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}
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void
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intel_miptree_unmap_raw(struct intel_context *intel,
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struct intel_mipmap_tree *mt)
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{
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drm_intel_bo_unmap(mt->region->bo);
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}
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static void
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intel_miptree_map_gtt(struct intel_context *intel,
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struct intel_mipmap_tree *mt,
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@@ -1212,7 +1240,7 @@ intel_miptree_map_gtt(struct intel_context *intel,
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assert(y % bh == 0);
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y /= bh;
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base = intel_region_map(intel, mt->region, map->mode) + mt->offset;
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base = intel_miptree_map_raw(intel, mt) + mt->offset;
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if (base == NULL)
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map->ptr = NULL;
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@@ -1241,7 +1269,7 @@ intel_miptree_unmap_gtt(struct intel_context *intel,
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unsigned int level,
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unsigned int slice)
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{
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intel_region_unmap(intel, mt->region);
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intel_miptree_unmap_raw(intel, mt);
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}
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static void
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@@ -1336,8 +1364,7 @@ intel_miptree_map_s8(struct intel_context *intel,
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*/
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if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
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uint8_t *untiled_s8_map = map->ptr;
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uint8_t *tiled_s8_map = intel_region_map(intel, mt->region,
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GL_MAP_READ_BIT);
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uint8_t *tiled_s8_map = intel_miptree_map_raw(intel, mt);
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unsigned int image_x, image_y;
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intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y);
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@@ -1352,7 +1379,7 @@ intel_miptree_map_s8(struct intel_context *intel,
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}
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}
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intel_region_unmap(intel, mt->region);
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intel_miptree_unmap_raw(intel, mt);
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DBG("%s: %d,%d %dx%d from mt %p %d,%d = %p/%d\n", __FUNCTION__,
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map->x, map->y, map->w, map->h,
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@@ -1374,7 +1401,7 @@ intel_miptree_unmap_s8(struct intel_context *intel,
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if (map->mode & GL_MAP_WRITE_BIT) {
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unsigned int image_x, image_y;
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uint8_t *untiled_s8_map = map->ptr;
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uint8_t *tiled_s8_map = intel_region_map(intel, mt->region, map->mode);
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uint8_t *tiled_s8_map = intel_miptree_map_raw(intel, mt);
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intel_miptree_get_image_offset(mt, level, slice, &image_x, &image_y);
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@@ -1388,7 +1415,7 @@ intel_miptree_unmap_s8(struct intel_context *intel,
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}
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}
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intel_region_unmap(intel, mt->region);
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intel_miptree_unmap_raw(intel, mt);
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}
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free(map->buffer);
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@@ -1429,7 +1456,7 @@ intel_miptree_unmap_etc(struct intel_context *intel,
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image_x += map->x;
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image_y += map->y;
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uint8_t *dst = intel_region_map(intel, mt->region, map->mode)
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uint8_t *dst = intel_miptree_map_raw(intel, mt)
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+ image_y * mt->region->pitch
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+ image_x * mt->region->cpp;
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@@ -1442,7 +1469,7 @@ intel_miptree_unmap_etc(struct intel_context *intel,
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map->ptr, map->stride,
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map->w, map->h, mt->etc_format);
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intel_region_unmap(intel, mt->region);
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intel_miptree_unmap_raw(intel, mt);
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free(map->buffer);
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}
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@@ -1480,8 +1507,8 @@ intel_miptree_map_depthstencil(struct intel_context *intel,
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*/
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if (!(map->mode & GL_MAP_INVALIDATE_RANGE_BIT)) {
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uint32_t *packed_map = map->ptr;
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uint8_t *s_map = intel_region_map(intel, s_mt->region, GL_MAP_READ_BIT);
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uint32_t *z_map = intel_region_map(intel, z_mt->region, GL_MAP_READ_BIT);
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uint8_t *s_map = intel_miptree_map_raw(intel, s_mt);
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uint32_t *z_map = intel_miptree_map_raw(intel, z_mt);
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unsigned int s_image_x, s_image_y;
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unsigned int z_image_x, z_image_y;
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@@ -1512,8 +1539,8 @@ intel_miptree_map_depthstencil(struct intel_context *intel,
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}
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}
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intel_region_unmap(intel, s_mt->region);
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intel_region_unmap(intel, z_mt->region);
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intel_miptree_unmap_raw(intel, s_mt);
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intel_miptree_unmap_raw(intel, z_mt);
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DBG("%s: %d,%d %dx%d from z mt %p %d,%d, s mt %p %d,%d = %p/%d\n",
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__FUNCTION__,
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@@ -1541,8 +1568,8 @@ intel_miptree_unmap_depthstencil(struct intel_context *intel,
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if (map->mode & GL_MAP_WRITE_BIT) {
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uint32_t *packed_map = map->ptr;
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uint8_t *s_map = intel_region_map(intel, s_mt->region, map->mode);
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uint32_t *z_map = intel_region_map(intel, z_mt->region, map->mode);
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uint8_t *s_map = intel_miptree_map_raw(intel, s_mt);
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uint32_t *z_map = intel_miptree_map_raw(intel, z_mt);
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unsigned int s_image_x, s_image_y;
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unsigned int z_image_x, z_image_y;
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@@ -1572,8 +1599,8 @@ intel_miptree_unmap_depthstencil(struct intel_context *intel,
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}
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}
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intel_region_unmap(intel, s_mt->region);
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intel_region_unmap(intel, z_mt->region);
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intel_miptree_unmap_raw(intel, s_mt);
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intel_miptree_unmap_raw(intel, z_mt);
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DBG("%s: %d,%d %dx%d from z mt %p (%s) %d,%d, s mt %p %d,%d = %p/%d\n",
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__FUNCTION__,
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@@ -590,6 +590,12 @@ void i945_miptree_layout(struct intel_mipmap_tree *mt);
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void brw_miptree_layout(struct intel_context *intel,
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struct intel_mipmap_tree *mt);
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void *intel_miptree_map_raw(struct intel_context *intel,
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struct intel_mipmap_tree *mt);
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void intel_miptree_unmap_raw(struct intel_context *intel,
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struct intel_mipmap_tree *mt);
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void
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intel_miptree_map(struct intel_context *intel,
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struct intel_mipmap_tree *mt,
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@@ -104,60 +104,6 @@ debug_backtrace(void)
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#endif
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/* XXX: Thread safety?
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*/
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void *
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intel_region_map(struct intel_context *intel, struct intel_region *region,
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GLbitfield mode)
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{
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/* We have the region->map_refcount controlling mapping of the BO because
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* in software fallbacks we may end up mapping the same buffer multiple
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* times on Mesa's behalf, so we refcount our mappings to make sure that
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* the pointer stays valid until the end of the unmap chain. However, we
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* must not emit any batchbuffers between the start of mapping and the end
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* of unmapping, or further use of the map will be incoherent with the GPU
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* rendering done by that batchbuffer. Hence we assert in
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* intel_batchbuffer_flush() that that doesn't happen, which means that the
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* flush is only needed on first map of the buffer.
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*/
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if (unlikely(intel->perf_debug)) {
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if (drm_intel_bo_busy(region->bo)) {
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perf_debug("Mapping a busy BO, causing a stall on the GPU.\n");
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}
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}
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_DBG("%s %p\n", __FUNCTION__, region);
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if (!region->map_refcount) {
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intel_flush(&intel->ctx);
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if (region->tiling != I915_TILING_NONE)
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drm_intel_gem_bo_map_gtt(region->bo);
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else
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drm_intel_bo_map(region->bo, true);
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region->map = region->bo->virtual;
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}
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return region->map;
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}
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void
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intel_region_unmap(struct intel_context *intel, struct intel_region *region)
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{
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_DBG("%s %p\n", __FUNCTION__, region);
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if (!--region->map_refcount) {
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if (region->tiling != I915_TILING_NONE)
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drm_intel_gem_bo_unmap_gtt(region->bo);
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else
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drm_intel_bo_unmap(region->bo);
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region->map = NULL;
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}
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}
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static struct intel_region *
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intel_region_alloc_internal(struct intel_screen *screen,
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GLuint cpp,
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@@ -291,8 +237,6 @@ intel_region_release(struct intel_region **region_handle)
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region->refcount--;
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if (region->refcount == 0) {
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assert(region->map_refcount == 0);
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drm_intel_bo_unreference(region->bo);
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free(region);
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@@ -65,8 +65,6 @@ struct intel_region
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GLuint width; /**< in pixels */
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GLuint height; /**< in pixels */
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GLuint pitch; /**< in bytes */
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GLubyte *map; /**< only non-NULL when region is actually mapped */
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GLuint map_refcount; /**< Reference count for mapping */
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uint32_t tiling; /**< Which tiling mode the region is in */
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@@ -99,17 +97,6 @@ void intel_region_release(struct intel_region **ib);
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void intel_recreate_static_regions(struct intel_context *intel);
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/**
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* Map/unmap regions. This is refcounted also:
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*
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* \param mode bitmask of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT
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*/
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void *intel_region_map(struct intel_context *intel,
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struct intel_region *ib,
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GLbitfield mode);
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void intel_region_unmap(struct intel_context *intel, struct intel_region *ib);
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/* Copy rectangular sub-regions
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*/
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bool
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@@ -178,7 +178,7 @@ intel_tex_map_image_for_swrast(struct intel_context *intel,
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DBG("%s \n", __FUNCTION__);
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intel_image->base.Map = intel_region_map(intel, mt->region, mode);
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intel_image->base.Map = intel_miptree_map_raw(intel, mt);
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} else {
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assert(intel_image->base.Base.Depth == 1);
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intel_miptree_get_image_offset(mt, level, face, &x, &y);
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@@ -186,7 +186,7 @@ intel_tex_map_image_for_swrast(struct intel_context *intel,
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DBG("%s: (%d,%d) -> (%d, %d)/%d\n",
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__FUNCTION__, face, level, x, y, mt->region->pitch);
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intel_image->base.Map = intel_region_map(intel, mt->region, mode) +
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intel_image->base.Map = intel_miptree_map_raw(intel, mt) +
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x * mt->cpp + y * mt->region->pitch;
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}
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@@ -199,7 +199,7 @@ intel_tex_unmap_image_for_swrast(struct intel_context *intel,
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struct intel_texture_image *intel_image)
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{
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if (intel_image && intel_image->mt) {
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intel_region_unmap(intel, intel_image->mt->region);
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intel_miptree_unmap_raw(intel, intel_image->mt);
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intel_image->base.Map = NULL;
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}
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}
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