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freedreno: name sysmem color/depth flush events

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Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3814>
This commit is contained in:
Jonathan Marek
2020-02-10 13:51:36 -05:00
parent c57456aab6
commit 75fbe089a6
8 changed files with 24 additions and 23 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/freedreno/registers/adreno_pm4.xml
+3 -2
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@@ -37,8 +37,9 @@ xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
<value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
<value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
<value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
<value name="UNK_1C" value="28" variants="A5XX,A6XX"/>
<value name="UNK_1D" value="29" variants="A5XX,A6XX"/>
<value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
<value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX,A6XX"/>
<value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX,A6XX"/>
<value name="BLIT" value="30" variants="A5XX,A6XX"/>
<value name="UNK_25" value="37" variants="A5XX"/>
<value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
src/freedreno/vulkan/tu_blit.c
+4 -4
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@@ -283,8 +283,8 @@ void tu_blit(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs,
tu_cs_reserve_space(cmdbuf->device, cs, 18);
tu6_emit_event_write(cmdbuf, cs, LRZ_FLUSH, false);
tu6_emit_event_write(cmdbuf, cs, 0x1d, true);
tu6_emit_event_write(cmdbuf, cs, FACENESS_FLUSH, true);
tu6_emit_event_write(cmdbuf, cs, PC_CCU_FLUSH_COLOR_TS, true);
tu6_emit_event_write(cmdbuf, cs, PC_CCU_FLUSH_DEPTH_TS, true);
tu6_emit_event_write(cmdbuf, cs, PC_CCU_INVALIDATE_COLOR, false);
tu6_emit_event_write(cmdbuf, cs, PC_CCU_INVALIDATE_DEPTH, false);
@@ -367,8 +367,8 @@ void tu_blit(struct tu_cmd_buffer *cmdbuf, struct tu_cs *cs,
tu_cs_reserve_space(cmdbuf->device, cs, 17);
tu6_emit_event_write(cmdbuf, cs, 0x1d, true);
tu6_emit_event_write(cmdbuf, cs, FACENESS_FLUSH, true);
tu6_emit_event_write(cmdbuf, cs, PC_CCU_FLUSH_COLOR_TS, true);
tu6_emit_event_write(cmdbuf, cs, PC_CCU_FLUSH_DEPTH_TS, true);
tu6_emit_event_write(cmdbuf, cs, CACHE_FLUSH_TS, true);
tu6_emit_event_write(cmdbuf, cs, CACHE_INVALIDATE, false);
}
src/freedreno/vulkan/tu_cmd_buffer.c
+5 -5
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@@ -1493,7 +1493,7 @@ tu_cmd_prepare_sysmem_clear_ib(struct tu_cmd_buffer *cmd,
* when nothing clears which we currently can't handle.
*/
tu_cs_reserve_space(cmd->device, &sub_cs, 5);
tu6_emit_event_write(cmd, &sub_cs, UNK_1D, true);
tu6_emit_event_write(cmd, &sub_cs, PC_CCU_FLUSH_COLOR_TS, true);
cmd->state.sysmem_clear_ib = tu_cs_end_sub_stream(&cmd->sub_cs, &sub_cs);
}
@@ -1584,8 +1584,8 @@ tu6_sysmem_render_end(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu6_emit_lrz_flush(cmd, cs);
tu6_emit_event_write(cmd, cs, UNK_1C, true);
tu6_emit_event_write(cmd, cs, UNK_1D, true);
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
tu_cs_sanity_check(cs);
}
@@ -2733,8 +2733,8 @@ tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
/* Emit flushes so that input attachments will read the correct value. This
* is for sysmem only, although it shouldn't do much harm on gmem.
*/
tu6_emit_event_write(cmd, cs, UNK_1C, true);
tu6_emit_event_write(cmd, cs, UNK_1D, true);
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_COLOR_TS, true);
tu6_emit_event_write(cmd, cs, PC_CCU_FLUSH_DEPTH_TS, true);
/* TODO:
* since we don't know how to do GMEM->GMEM resolve,
src/gallium/drivers/freedreno/a5xx/fd5_gmem.c
+1 -1
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@@ -775,7 +775,7 @@ fd5_emit_sysmem_fini(struct fd_batch *batch)
fd5_emit_lrz_flush(ring);
OUT_PKT7(ring, CP_EVENT_WRITE, 4);
OUT_RING(ring, UNK_1D);
OUT_RING(ring, PC_CCU_FLUSH_COLOR_TS);
OUT_RELOCW(ring, fd5_ctx->blit_mem, 0, 0, 0); /* ADDR_LO/HI */
OUT_RING(ring, 0x00000000);
}
src/gallium/drivers/freedreno/a6xx/fd6_blitter.c
+4 -4
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@@ -152,8 +152,8 @@ emit_setup(struct fd_batch *batch)
{
struct fd_ringbuffer *ring = batch->draw;
fd6_event_write(batch, ring, 0x1d, true);
fd6_event_write(batch, ring, FACENESS_FLUSH, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_DEPTH, false);
}
@@ -660,8 +660,8 @@ handle_rgba_blit(struct fd_context *ctx, const struct pipe_blit_info *info)
emit_blit_or_clear_texture(ctx, batch->draw, info, NULL);
}
fd6_event_write(batch, batch->draw, 0x1d, true);
fd6_event_write(batch, batch->draw, FACENESS_FLUSH, true);
fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, batch->draw, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, batch->draw, CACHE_FLUSH_TS, true);
fd6_cache_inv(batch, batch->draw);
src/gallium/drivers/freedreno/a6xx/fd6_draw.c
+3 -3
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@@ -404,7 +404,7 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_RING(ring, A6XX_RB_2D_BLIT_CNTL_COLOR_FORMAT(FMT6_16_UNORM) |
0x4f00080);
fd6_event_write(batch, ring, UNK_1D, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_INVALIDATE_COLOR, false);
OUT_PKT4(ring, REG_A6XX_RB_2D_SRC_SOLID_C0, 4);
@@ -452,8 +452,8 @@ fd6_clear_lrz(struct fd_batch *batch, struct fd_resource *zsbuf, double depth)
OUT_PKT4(ring, REG_A6XX_RB_UNKNOWN_8E04, 1);
OUT_RING(ring, 0x0); /* RB_UNKNOWN_8E04 */
fd6_event_write(batch, ring, UNK_1D, true);
fd6_event_write(batch, ring, FACENESS_FLUSH, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
fd6_cache_inv(batch, ring);
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
+2 -2
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@@ -1404,8 +1404,8 @@ fd6_framebuffer_barrier(struct fd_context *ctx)
OUT_RING(ring, CP_WAIT_REG_MEM_4_MASK(~0));
OUT_RING(ring, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(16));
fd6_event_write(batch, ring, UNK_1D, true);
fd6_event_write(batch, ring, UNK_1C, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_DEPTH_TS, true);
seqno = fd6_event_write(batch, ring, CACHE_FLUSH_TS, true);
src/gallium/drivers/freedreno/a6xx/fd6_gmem.c
+2 -2
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@@ -1426,7 +1426,7 @@ emit_sysmem_clears(struct fd_batch *batch, struct fd_ringbuffer *ring)
}
}
fd6_event_write(batch, ring, UNK_1D, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
}
static void
@@ -1513,7 +1513,7 @@ fd6_emit_sysmem_fini(struct fd_batch *batch)
fd6_emit_lrz_flush(ring);
fd6_event_write(batch, ring, UNK_1D, true);
fd6_event_write(batch, ring, PC_CCU_FLUSH_COLOR_TS, true);
}
void