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ac/surface/gfx9: don't allow DCC for the smallest mipmap levels

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This fixes garbage there if we don't flush TC L2 after rendering.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák
2017-08-17 23:35:36 +02:00
parent 54c2c771bd
commit 759526813b
1 changed files with 18 additions and 1 deletions
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src/amd/common/ac_surface.c
+18 -1
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@@ -908,6 +908,23 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
surf->u.gfx9.dcc_pitch_max = dout.pitch - 1;
surf->dcc_size = dout.dccRamSize;
surf->dcc_alignment = dout.dccRamBaseAlign;
surf->num_dcc_levels = in->numMipLevels;
/* Disable DCC for the smallest levels. It seems to be
* required for DCC readability between CB and shaders
* when TC L2 isn't flushed. This was guessed.
*
* Alternative solutions that also work but are worse:
* - Disable DCC.
* - Flush TC L2 after rendering.
*/
for (unsigned i = 1; i < in->numMipLevels; i++) {
if (mip_info[i].pitch *
mip_info[i].height * surf->bpe < 1024) {
surf->num_dcc_levels = i;
break;
}
}
}
/* FMASK */
@@ -1061,6 +1078,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
surf->u.gfx9.resource_type = AddrSurfInfoIn.resourceType;
surf->num_dcc_levels = 0;
surf->surf_size = 0;
surf->dcc_size = 0;
surf->htile_size = 0;
@@ -1087,7 +1105,6 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
}
surf->is_linear = surf->u.gfx9.surf.swizzle_mode == ADDR_SW_LINEAR;
surf->num_dcc_levels = surf->dcc_size ? config->info.levels : 0;
switch (surf->u.gfx9.surf.swizzle_mode) {
/* S = standard. */