radeonsi: determine SPI_SHADER_Z_FORMAT outside of shader compilation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
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@@ -2247,13 +2247,6 @@ static void si_llvm_emit_fs_epilogue(struct lp_build_tgsi_context * bld_base)
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si_shader_ctx->screen->b.family != CHIP_OLAND)
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mask |= 0x1;
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if (samplemask_index >= 0)
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si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_ABGR;
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else if (stencil_index >= 0)
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si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_GR;
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else
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si_shader_ctx->shader->spi_shader_z_format = V_028710_SPI_SHADER_32_R;
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/* Specify which components to enable */
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args[0] = lp_build_const_int32(base->gallivm, mask);
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@@ -278,7 +278,6 @@ struct si_shader {
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unsigned float_mode;
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unsigned scratch_bytes_per_wave;
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unsigned spi_shader_col_format;
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unsigned spi_shader_z_format;
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unsigned cb_shader_mask;
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union si_shader_key key;
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@@ -431,7 +431,12 @@ static void si_shader_ps(struct si_shader *shader)
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si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
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si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
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si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT, shader->spi_shader_z_format);
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si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
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info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
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info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
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info->writes_z ? V_028710_SPI_SHADER_32_R :
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V_028710_SPI_SHADER_ZERO);
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si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT,
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shader->spi_shader_col_format);
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si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, shader->cb_shader_mask);
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