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radeonsi/vcn: use register versions for jpeg

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update the register version and select appropriate registers during decoder create

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22158>
This commit is contained in:
Sathishkumar S
2022-10-21 19:10:39 +05:30
committed by Marge Bot
parent 9422627074
commit 74572084d8
4 changed files with 131 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/amd/common/ac_vcn_dec.h
-1
View File
@@ -1195,7 +1195,6 @@ struct jpeg_params {
unsigned dt_luma_top_offset;
unsigned dt_chroma_top_offset;
unsigned dt_chromav_top_offset;
bool direct_reg;
};
#define RDECODE_VCN1_GPCOM_VCPU_CMD 0x2070c
src/gallium/drivers/radeonsi/radeon_vcn_dec.c
+49 -4
View File
@@ -3183,7 +3183,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
dec->reg.data1 = RDECODE_VCN1_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN1_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN1_ENGINE_CNTL;
dec->jpg.direct_reg = false;
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V1;
break;
case CHIP_NAVI10:
case CHIP_NAVI12:
@@ -3193,7 +3193,7 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
dec->reg.data1 = RDECODE_VCN2_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN2_ENGINE_CNTL;
dec->jpg.direct_reg = true;
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2;
break;
case CHIP_MI100:
case CHIP_MI200:
@@ -3208,14 +3208,14 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
dec->reg.data1 = RDECODE_VCN2_5_GPCOM_VCPU_DATA1;
dec->reg.cmd = RDECODE_VCN2_5_GPCOM_VCPU_CMD;
dec->reg.cntl = RDECODE_VCN2_5_ENGINE_CNTL;
dec->jpg.direct_reg = true;
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2;
break;
case CHIP_GFX1100:
case CHIP_GFX1101:
case CHIP_GFX1102:
case CHIP_GFX1103_R1:
case CHIP_GFX1103_R2:
dec->jpg.direct_reg = true;
dec->jpg_reg.version = RDECODE_JPEG_REG_VER_V2;
dec->addr_gfx_mode = RDECODE_ARRAY_MODE_ADDRLIB_SEL_GFX11;
dec->av1_version = RDECODE_AV1_VER_1;
break;
@@ -3231,6 +3231,51 @@ struct pipe_video_codec *radeon_create_decoder(struct pipe_context *context,
r = flush(dec, 0, NULL);
if (r)
goto error;
} else if (dec->jpg_reg.version != RDECODE_JPEG_REG_VER_V1) {
dec->jpg_reg.jrbc_ib_cond_rd_timer = vcnipUVD_JRBC_IB_COND_RD_TIMER;
dec->jpg_reg.jrbc_ib_ref_data = vcnipUVD_JRBC_IB_REF_DATA;
dec->jpg_reg.jpeg_rb_base = vcnipUVD_JPEG_RB_BASE;
dec->jpg_reg.jpeg_rb_size = vcnipUVD_JPEG_RB_SIZE;
dec->jpg_reg.jpeg_rb_wptr = vcnipUVD_JPEG_RB_WPTR;
dec->jpg_reg.jpeg_int_en = vcnipUVD_JPEG_INT_EN;
dec->jpg_reg.jpeg_cntl = vcnipUVD_JPEG_CNTL;
dec->jpg_reg.jpeg_rb_rptr = vcnipUVD_JPEG_RB_RPTR;
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V2) {
dec->jpg_reg.jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST;
dec->jpg_reg.lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH;
dec->jpg_reg.lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW;
dec->jpg_reg.jpeg_pitch = vcnipUVD_JPEG_PITCH;
dec->jpg_reg.jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH;
dec->jpg_reg.dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE;
dec->jpg_reg.dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE;
dec->jpg_reg.dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE;
dec->jpg_reg.lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH;
dec->jpg_reg.lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW;
dec->jpg_reg.jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2;
dec->jpg_reg.jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL;
dec->jpg_reg.jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR;
dec->jpg_reg.jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR;
dec->jpg_reg.jpeg_index = vcnipUVD_JPEG_INDEX;
dec->jpg_reg.jpeg_data = vcnipUVD_JPEG_DATA;
} else {
dec->jpg_reg.jpeg_dec_soft_rst = vcnipUVD_JPEG_DEC_SOFT_RST_1;
dec->jpg_reg.lmi_jpeg_read_64bit_bar_high = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH_1;
dec->jpg_reg.lmi_jpeg_read_64bit_bar_low = vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW_1;
dec->jpg_reg.jpeg_pitch = vcnipUVD_JPEG_PITCH_1;
dec->jpg_reg.jpeg_uv_pitch = vcnipUVD_JPEG_UV_PITCH_1;
dec->jpg_reg.dec_addr_mode = vcnipJPEG_DEC_ADDR_MODE_1;
dec->jpg_reg.dec_y_gfx10_tiling_surface = vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE_1;
dec->jpg_reg.dec_uv_gfx10_tiling_surface = vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE_1;
dec->jpg_reg.lmi_jpeg_write_64bit_bar_high = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH_1;
dec->jpg_reg.lmi_jpeg_write_64bit_bar_low = vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW_1;
dec->jpg_reg.jpeg_tier_cntl2 = vcnipUVD_JPEG_TIER_CNTL2_1;
dec->jpg_reg.jpeg_outbuf_cntl = vcnipUVD_JPEG_OUTBUF_CNTL_1;
dec->jpg_reg.jpeg_outbuf_rptr = vcnipUVD_JPEG_OUTBUF_RPTR_1;
dec->jpg_reg.jpeg_outbuf_wptr = vcnipUVD_JPEG_OUTBUF_WPTR_1;
dec->jpg_reg.jpeg_luma_base0_0 = vcnipUVD_JPEG_LUMA_BASE0_0;
dec->jpg_reg.jpeg_chroma_base0_0 = vcnipUVD_JPEG_CHROMA_BASE0_0;
dec->jpg_reg.jpeg_chromav_base0_0 = vcnipUVD_JPEG_CHROMAV_BASE0_0;
}
}
next_buffer(dec);
src/gallium/drivers/radeonsi/radeon_vcn_dec.h
+35
View File
@@ -41,6 +41,40 @@ struct rvcn_dec_dynamic_dpb_t2 {
struct rvid_buffer dpb;
};
struct jpeg_registers {
#define RDECODE_JPEG_REG_VER_V1 0
#define RDECODE_JPEG_REG_VER_V2 1
#define RDECODE_JPEG_REG_VER_V3 2
unsigned version;
unsigned jpeg_dec_soft_rst;
unsigned jrbc_ib_cond_rd_timer;
unsigned jrbc_ib_ref_data;
unsigned lmi_jpeg_read_64bit_bar_high;
unsigned lmi_jpeg_read_64bit_bar_low;
unsigned jpeg_rb_base;
unsigned jpeg_rb_size;
unsigned jpeg_rb_wptr;
unsigned jpeg_pitch;
unsigned jpeg_uv_pitch;
unsigned dec_addr_mode;
unsigned dec_y_gfx10_tiling_surface;
unsigned dec_uv_gfx10_tiling_surface;
unsigned lmi_jpeg_write_64bit_bar_high;
unsigned lmi_jpeg_write_64bit_bar_low;
unsigned jpeg_tier_cntl2;
unsigned jpeg_outbuf_rptr;
unsigned jpeg_outbuf_cntl;
unsigned jpeg_int_en;
unsigned jpeg_cntl;
unsigned jpeg_rb_rptr;
unsigned jpeg_outbuf_wptr;
unsigned jpeg_luma_base0_0;
unsigned jpeg_chroma_base0_0;
unsigned jpeg_chromav_base0_0;
unsigned jpeg_index;
unsigned jpeg_data;
};
struct radeon_decoder {
struct pipe_video_codec base;
@@ -90,6 +124,7 @@ struct radeon_decoder {
unsigned cntl;
} reg;
struct jpeg_params jpg;
struct jpeg_registers jpg_reg;
enum {
DPB_MAX_RES = 0,
DPB_DYNAMIC_TIER_1,
src/gallium/drivers/radeonsi/radeon_vcn_dec_jpeg.c
+47 -41
View File
@@ -209,36 +209,36 @@ static void send_cmd_bitstream_direct(struct radeon_decoder *dec, struct pb_buff
uint64_t addr;
// jpeg soft reset
set_reg_jpeg(dec, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 1);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 1);
// ensuring the Reset is asserted in SCLK domain
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0x1 << 0x10));
set_reg_jpeg(dec, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0x1 << 0x10));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
// wait mem
set_reg_jpeg(dec, vcnipUVD_JPEG_DEC_SOFT_RST, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND0, TYPE0, 0);
// ensuring the Reset is de-asserted in SCLK domain
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (0 << 0x10));
set_reg_jpeg(dec, vcnipUVD_JPEG_DEC_SOFT_RST, COND3, TYPE3, (0x1 << 0x10));
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (0 << 0x10));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_dec_soft_rst, COND3, TYPE3, (0x1 << 0x10));
dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_READ_64BIT_BAR_LOW/HIGH based on bitstream buffer address
set_reg_jpeg(dec, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_HIGH, COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, vcnipUVD_LMI_JPEG_READ_64BIT_BAR_LOW, COND0, TYPE0, addr);
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_high, COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_read_64bit_bar_low, COND0, TYPE0, addr);
// set jpeg_rb_base
set_reg_jpeg(dec, vcnipUVD_JPEG_RB_BASE, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_base, COND0, TYPE0, 0);
// set jpeg_rb_base
set_reg_jpeg(dec, vcnipUVD_JPEG_RB_SIZE, COND0, TYPE0, 0xFFFFFFF0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_size, COND0, TYPE0, 0xFFFFFFF0);
// set jpeg_rb_wptr
set_reg_jpeg(dec, vcnipUVD_JPEG_RB_WPTR, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_wptr, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
}
/* send a target buffer command */
@@ -247,54 +247,60 @@ static void send_cmd_target_direct(struct radeon_decoder *dec, struct pb_buffer
{
uint64_t addr;
set_reg_jpeg(dec, vcnipUVD_JPEG_PITCH, COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
set_reg_jpeg(dec, vcnipUVD_JPEG_UV_PITCH, COND0, TYPE0, ((dec->jpg.dt_uv_pitch * 2) >> 4));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_pitch, COND0, TYPE0, (dec->jpg.dt_pitch >> 4));
set_reg_jpeg(dec, dec->jpg_reg.jpeg_uv_pitch, COND0, TYPE0, ((dec->jpg.dt_uv_pitch * 2) >> 4));
set_reg_jpeg(dec, vcnipJPEG_DEC_ADDR_MODE, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipJPEG_DEC_Y_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipJPEG_DEC_UV_GFX10_TILING_SURFACE, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.dec_addr_mode, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.dec_y_gfx10_tiling_surface, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.dec_uv_gfx10_tiling_surface, COND0, TYPE0, 0);
dec->ws->cs_add_buffer(&dec->jcs[dec->cb_idx], buf, usage | RADEON_USAGE_SYNCHRONIZED, domain);
addr = dec->ws->buffer_get_virtual_address(buf);
addr = addr + off;
// set UVD_LMI_JPEG_WRITE_64BIT_BAR_LOW/HIGH based on target buffer address
set_reg_jpeg(dec, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_HIGH, COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, vcnipUVD_LMI_JPEG_WRITE_64BIT_BAR_LOW, COND0, TYPE0, addr);
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_high, COND0, TYPE0, (addr >> 32));
set_reg_jpeg(dec, dec->jpg_reg.lmi_jpeg_write_64bit_bar_low, COND0, TYPE0, addr);
// set output buffer data address
set_reg_jpeg(dec, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipUVD_JPEG_DATA, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
set_reg_jpeg(dec, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 1);
set_reg_jpeg(dec, vcnipUVD_JPEG_DATA, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
if (dec->jpg.dt_chromav_top_offset) {
set_reg_jpeg(dec, vcnipUVD_JPEG_INDEX, COND0, TYPE0, 2);
set_reg_jpeg(dec, vcnipUVD_JPEG_DATA, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V2) {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 1);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
if (dec->jpg.dt_chromav_top_offset) {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_index, COND0, TYPE0, 2);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_data, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
}
} else {
set_reg_jpeg(dec, dec->jpg_reg.jpeg_luma_base0_0, COND0, TYPE0, dec->jpg.dt_luma_top_offset);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_chroma_base0_0, COND0, TYPE0, dec->jpg.dt_chroma_top_offset);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_chromav_base0_0, COND0, TYPE0, dec->jpg.dt_chromav_top_offset);
}
set_reg_jpeg(dec, vcnipUVD_JPEG_TIER_CNTL2, COND0, 0, 0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_tier_cntl2, COND0, 0, 0);
// set output buffer read pointer
set_reg_jpeg(dec, vcnipUVD_JPEG_OUTBUF_RPTR, COND0, TYPE0, 0);
set_reg_jpeg(dec, vcnipUVD_JPEG_OUTBUF_CNTL, COND0, TYPE0,
set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_rptr, COND0, TYPE0, 0);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_cntl, COND0, TYPE0,
((0x00001587 & (~0x00000180L)) | (0x1 << 0x7) | (0x1 << 0x6)));
// enable error interrupts
set_reg_jpeg(dec, vcnipUVD_JPEG_INT_EN, COND0, TYPE0, 0xFFFFFFFE);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_int_en, COND0, TYPE0, 0xFFFFFFFE);
// start engine command
set_reg_jpeg(dec, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x6);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, 0x6);
// wait for job completion, wait for job JBSI fetch done
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_COND_RD_TIMER, COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, vcnipUVD_JPEG_RB_RPTR, COND3, TYPE3, 0xFFFFFFFF);
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, (dec->jpg.bsd_size >> 2));
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_cond_rd_timer, COND0, TYPE0, 0x01400200);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_rb_rptr, COND3, TYPE3, 0xFFFFFFFF);
// wait for job jpeg outbuf idle
set_reg_jpeg(dec, vcnipUVD_JRBC_IB_REF_DATA, COND0, TYPE0, 0xFFFFFFFF);
set_reg_jpeg(dec, vcnipUVD_JPEG_OUTBUF_WPTR, COND3, TYPE3, 0x00000001);
set_reg_jpeg(dec, dec->jpg_reg.jrbc_ib_ref_data, COND0, TYPE0, 0xFFFFFFFF);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_outbuf_wptr, COND3, TYPE3, 0x00000001);
// stop engine
set_reg_jpeg(dec, vcnipUVD_JPEG_CNTL, COND0, TYPE0, 0x4);
set_reg_jpeg(dec, dec->jpg_reg.jpeg_cntl, COND0, TYPE0, 0x4);
}
/**
@@ -314,11 +320,11 @@ void send_cmd_jpeg(struct radeon_decoder *dec, struct pipe_video_buffer *target,
dt = radeon_jpeg_get_decode_param(dec, target, picture);
if (dec->jpg.direct_reg == true) {
send_cmd_bitstream_direct(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target_direct(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
} else {
if (dec->jpg_reg.version == RDECODE_JPEG_REG_VER_V1) {
send_cmd_bitstream(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
} else {
send_cmd_bitstream_direct(dec, bs_buf->res->buf, 0, RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
send_cmd_target_direct(dec, dt, 0, RADEON_USAGE_WRITE, RADEON_DOMAIN_VRAM);
}
}