vc4: Convert to consuming NIR.

NIR brings us better optimization than I would have bothered to write
within the driver, developers sharing future optimization work, and the
ability to share device-specific lowering code that we and other
GLES2-level drivers need.

total uniforms in shared programs: 13421 -> 13422 (0.01%)
uniforms in affected programs:     62 -> 63 (1.61%)
total instructions in shared programs: 39961 -> 39707 (-0.64%)
instructions in affected programs:     15494 -> 15240 (-1.64%)

v2: Add missing imov support, and assert that there are no dest saturates.
v3: Rebase on the target-specific algebraic series.
v4: Rebase on gallium-includes-from-NIR changes in mater.
v5: Rebase on variables being in lists instead of hash tables.
v6: Squash in intermediate changes that used the NIR-to-TGSI pass (which
    I'm not committing)

src/gallium/drivers/vc4/vc4_qir.c

@@ -391,6 +391,9 @@ qir_compile_init(void)
         c->output_color_index = -1;
         c->output_point_size_index = -1;
 
+        c->def_ht = _mesa_hash_table_create(c, _mesa_hash_pointer,
+                                            _mesa_key_pointer_equal);
+
         return c;
 }
 

src/gallium/drivers/vc4/vc4_qir.h

@@ -32,9 +32,9 @@
 #include <string.h>
 
 #include "util/macros.h"
+#include "glsl/nir/nir.h"
 #include "util/simple_list.h"
 #include "util/u_math.h"
-#include "tgsi/tgsi_parse.h"
 
 enum qfile {
         QFILE_NULL,
@@ -282,11 +282,20 @@ struct vc4_compiler_ubo_range {
 
 struct vc4_compile {
         struct vc4_context *vc4;
-        struct tgsi_parse_context parser;
-        struct qreg *temps;
+        nir_shader *s;
+        nir_function_impl *impl;
+        struct exec_list *cf_node_list;
+
+        /**
+         * Mapping from nir_register * or nir_ssa_def * to array of struct
+         * qreg for the values.
+         */
+        struct hash_table *def_ht;
+
         /* For each temp, the instruction generating its value. */
         struct qinst **defs;
         uint32_t defs_array_size;
+
         /**
          * Inputs to the shader, arranged by TGSI declaration order.
          *
@@ -294,17 +303,15 @@ struct vc4_compile {
          */
         struct qreg *inputs;
         struct qreg *outputs;
-        struct qreg *consts;
-        struct qreg addr[4]; /* TGSI ARL destination. */
-        uint32_t temps_array_size;
         uint32_t inputs_array_size;
         uint32_t outputs_array_size;
         uint32_t uniforms_array_size;
-        uint32_t consts_array_size;
-        uint32_t num_consts;
 
         struct vc4_compiler_ubo_range *ubo_ranges;
         uint32_t ubo_ranges_array_size;
+        /** Number of uniform areas declared in ubo_ranges. */
+        uint32_t num_uniform_ranges;
+        /** Number of uniform areas used for indirect addressed loads. */
         uint32_t num_ubo_ranges;
         uint32_t next_ubo_dst_offset;
 

src/gallium/drivers/vc4/vc4_screen.c

@@ -43,6 +43,8 @@ static const struct debug_named_value debug_options[] = {
           "Dump generated QPU instructions" },
         { "qir",      VC4_DEBUG_QIR,
           "Dump QPU IR during program compile" },
+        { "nir",      VC4_DEBUG_NIR,
+          "Dump NIR during program compile" },
         { "tgsi",     VC4_DEBUG_TGSI,
           "Dump TGSI during program compile" },
         { "shaderdb", VC4_DEBUG_SHADERDB,

src/gallium/drivers/vc4/vc4_screen.h

@@ -40,6 +40,7 @@ struct vc4_bo;
 #define VC4_DEBUG_NORAST    0x0040
 #define VC4_DEBUG_ALWAYS_FLUSH 0x0080
 #define VC4_DEBUG_ALWAYS_SYNC  0x0100
+#define VC4_DEBUG_NIR       0x0200
 
 #define VC4_MAX_MIP_LEVELS 12
 #define VC4_MAX_TEXTURE_SAMPLERS 16