AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

vc4: Use VC4_SET/GET_FIELD for some RCL packets.

Browse Source
This commit is contained in:
Eric Anholt
2015-06-11 16:08:11 -07:00
parent e22a192784
commit 731ac05cc4
4 changed files with 87 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/gallium/drivers/vc4/kernel/vc4_packet.h
+28 -23
View File
@@ -149,18 +149,19 @@ enum vc4_packet {
/** @{
*
* byte 1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
* byte 0-1 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
*/
#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 7)
#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 6)
#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 5)
#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 4)
#define VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR (1 << 15)
#define VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR (1 << 14)
#define VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR (1 << 13)
#define VC4_STORE_TILE_BUFFER_DISABLE_SWAP (1 << 12)
#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 (0 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER (1 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_BGR565 (2 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_MASK (3 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK VC4_MASK(9, 8)
#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 8
#define VC4_LOADSTORE_TILE_BUFFER_RGBA8888 0
#define VC4_LOADSTORE_TILE_BUFFER_BGR565_DITHER 1
#define VC4_LOADSTORE_TILE_BUFFER_BGR565 2
/** @} */
/** @{
@@ -168,21 +169,24 @@ enum vc4_packet {
* byte 0 of VC4_PACKET_STORE_TILE_BUFFER_GENERAL and
* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL
*/
#define VC4_STORE_TILE_BUFFER_MODE_MASK VC4_MASK(7, 6)
#define VC4_STORE_TILE_BUFFER_MODE_SHIFT 6
#define VC4_STORE_TILE_BUFFER_MODE_SAMPLE0 (0 << 6)
#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X4 (1 << 6)
#define VC4_STORE_TILE_BUFFER_MODE_DECIMATE_X16 (2 << 6)
/** The values of the field are VC4_TILING_FORMAT_* */
#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK (3 << 4)
#define VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT 4
#define VC4_LOADSTORE_TILE_BUFFER_TILING_MASK VC4_MASK(5, 4)
#define VC4_LOADSTORE_TILE_BUFFER_TILING_SHIFT 4
#define VC4_LOADSTORE_TILE_BUFFER_NONE (0 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_COLOR (1 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_ZS (2 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_Z (3 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK (4 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_FULL (5 << 0)
#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_MASK VC4_MASK(2, 0)
#define VC4_LOADSTORE_TILE_BUFFER_BUFFER_SHIFT 0
#define VC4_LOADSTORE_TILE_BUFFER_NONE 0
#define VC4_LOADSTORE_TILE_BUFFER_COLOR 1
#define VC4_LOADSTORE_TILE_BUFFER_ZS 2
#define VC4_LOADSTORE_TILE_BUFFER_Z 3
#define VC4_LOADSTORE_TILE_BUFFER_VG_MASK 4
#define VC4_LOADSTORE_TILE_BUFFER_FULL 5
/** @} */
#define VC4_INDEX_BUFFER_U8 (0 << 4)
@@ -251,17 +255,18 @@ enum vc4_packet {
#define VC4_RENDER_CONFIG_ENABLE_VG_MASK (1 << 8)
/** The values of the field are VC4_TILING_FORMAT_* */
#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK (3 << 6)
#define VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK VC4_MASK(7, 6)
#define VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT 6
#define VC4_RENDER_CONFIG_DECIMATE_MODE_1X (0 << 4)
#define VC4_RENDER_CONFIG_DECIMATE_MODE_4X (1 << 4)
#define VC4_RENDER_CONFIG_DECIMATE_MODE_16X (2 << 4)
#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED (0 << 2)
#define VC4_RENDER_CONFIG_FORMAT_RGBA8888 (1 << 2)
#define VC4_RENDER_CONFIG_FORMAT_BGR565 (2 << 2)
#define VC4_RENDER_CONFIG_FORMAT_MASK (3 << 2)
#define VC4_RENDER_CONFIG_FORMAT_MASK VC4_MASK(3, 2)
#define VC4_RENDER_CONFIG_FORMAT_SHIFT 2
#define VC4_RENDER_CONFIG_FORMAT_BGR565_DITHERED 0
#define VC4_RENDER_CONFIG_FORMAT_RGBA8888 1
#define VC4_RENDER_CONFIG_FORMAT_BGR565 2
#define VC4_RENDER_CONFIG_TILE_BUFFER_64BIT (1 << 1)
#define VC4_RENDER_CONFIG_MS_MODE_4X (1 << 0)
src/gallium/drivers/vc4/kernel/vc4_validate.c
+10 -11
View File
@@ -311,17 +311,18 @@ validate_branch_to_sublist(VALIDATE_ARGS)
static int
validate_loadstore_tile_buffer_general(VALIDATE_ARGS)
{
uint32_t packet_b0 = *(uint8_t *)(untrusted + 0);
uint32_t packet_b1 = *(uint8_t *)(untrusted + 1);
uint16_t packet_b01 = *(uint16_t *)(untrusted + 0);
struct drm_gem_cma_object *fbo;
uint32_t buffer_type = packet_b0 & 0xf;
uint32_t buffer_type = VC4_GET_FIELD(packet_b01,
VC4_LOADSTORE_TILE_BUFFER_BUFFER);
uint32_t untrusted_address, offset, cpp;
switch (buffer_type) {
case VC4_LOADSTORE_TILE_BUFFER_NONE:
return 0;
case VC4_LOADSTORE_TILE_BUFFER_COLOR:
if ((packet_b1 & VC4_LOADSTORE_TILE_BUFFER_MASK) ==
if (VC4_GET_FIELD(packet_b01,
VC4_LOADSTORE_TILE_BUFFER_FORMAT) ==
VC4_LOADSTORE_TILE_BUFFER_RGBA8888) {
cpp = 4;
} else {
@@ -346,9 +347,8 @@ validate_loadstore_tile_buffer_general(VALIDATE_ARGS)
offset = untrusted_address & ~0xf;
if (!check_tex_size(exec, fbo, offset,
((packet_b0 &
VC4_LOADSTORE_TILE_BUFFER_FORMAT_MASK) >>
VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT),
VC4_GET_FIELD(packet_b01,
VC4_LOADSTORE_TILE_BUFFER_TILING),
exec->fb_width, exec->fb_height, cpp)) {
return -EINVAL;
}
@@ -590,7 +590,7 @@ validate_tile_rendering_mode_config(VALIDATE_ARGS)
exec->fb_height = *(uint16_t *)(untrusted + 6);
flags = *(uint16_t *)(untrusted + 8);
if ((flags & VC4_RENDER_CONFIG_FORMAT_MASK) ==
if (VC4_GET_FIELD(flags, VC4_RENDER_CONFIG_FORMAT) ==
VC4_RENDER_CONFIG_FORMAT_RGBA8888) {
cpp = 4;
} else {
@@ -599,9 +599,8 @@ validate_tile_rendering_mode_config(VALIDATE_ARGS)
offset = *(uint32_t *)untrusted;
if (!check_tex_size(exec, fbo, offset,
((flags &
VC4_RENDER_CONFIG_MEMORY_FORMAT_MASK) >>
VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT),
VC4_GET_FIELD(flags,
VC4_RENDER_CONFIG_MEMORY_FORMAT),
exec->fb_width, exec->fb_height, cpp)) {
return -EINVAL;
}
src/gallium/drivers/vc4/vc4_blit.c
+16 -13
View File
@@ -54,11 +54,13 @@ vc4_tile_blit_color_rcl(struct vc4_context *vc4,
cl_reloc(vc4, &vc4->rcl, dst->bo, dst_surf->offset);
cl_u16(&vc4->rcl, dst_surf->base.width);
cl_u16(&vc4->rcl, dst_surf->base.height);
cl_u16(&vc4->rcl, ((dst_surf->tiling <<
VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) |
(vc4_rt_format_is_565(dst_surf->base.format) ?
VC4_RENDER_CONFIG_FORMAT_BGR565 :
VC4_RENDER_CONFIG_FORMAT_RGBA8888)));
cl_u16(&vc4->rcl,
VC4_SET_FIELD(dst_surf->tiling,
VC4_RENDER_CONFIG_MEMORY_FORMAT) |
VC4_SET_FIELD(vc4_rt_format_is_565(dst_surf->base.format) ?
VC4_RENDER_CONFIG_FORMAT_BGR565 :
VC4_RENDER_CONFIG_FORMAT_RGBA8888,
VC4_RENDER_CONFIG_FORMAT));
uint32_t src_hindex = vc4_gem_hindex(vc4, src->bo);
@@ -69,14 +71,15 @@ vc4_tile_blit_color_rcl(struct vc4_context *vc4,
cl_start_reloc(&vc4->rcl, 1);
cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
cl_u8(&vc4->rcl,
VC4_LOADSTORE_TILE_BUFFER_COLOR |
(src_surf->tiling <<
VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
cl_u8(&vc4->rcl,
vc4_rt_format_is_565(src_surf->base.format) ?
VC4_LOADSTORE_TILE_BUFFER_BGR565 :
VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
cl_u16(&vc4->rcl,
VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_COLOR,
VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
VC4_SET_FIELD(src_surf->tiling,
VC4_LOADSTORE_TILE_BUFFER_TILING) |
VC4_SET_FIELD(vc4_rt_format_is_565(src_surf->base.format) ?
VC4_LOADSTORE_TILE_BUFFER_BGR565 :
VC4_LOADSTORE_TILE_BUFFER_RGBA8888,
VC4_LOADSTORE_TILE_BUFFER_FORMAT));
cl_reloc_hindex(&vc4->rcl, src_hindex,
src_surf->offset);
src/gallium/drivers/vc4/vc4_context.c
+33 -28
View File
@@ -50,10 +50,12 @@ vc4_store_before_load(struct vc4_context *vc4, bool *coords_emitted)
return;
cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
cl_u8(&vc4->rcl, VC4_LOADSTORE_TILE_BUFFER_NONE);
cl_u8(&vc4->rcl, (VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR));
cl_u16(&vc4->rcl,
VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_NONE,
VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR |
VC4_STORE_TILE_BUFFER_DISABLE_ZS_CLEAR |
VC4_STORE_TILE_BUFFER_DISABLE_VG_MASK_CLEAR);
cl_u32(&vc4->rcl, 0); /* no address, since we're in None mode */
*coords_emitted = false;
@@ -148,11 +150,13 @@ vc4_setup_rcl(struct vc4_context *vc4)
cl_reloc(vc4, &vc4->rcl, render_tex->bo, render_surf->offset);
cl_u16(&vc4->rcl, width);
cl_u16(&vc4->rcl, height);
cl_u16(&vc4->rcl, ((render_surf->tiling <<
VC4_RENDER_CONFIG_MEMORY_FORMAT_SHIFT) |
(vc4_rt_format_is_565(render_surf->base.format) ?
VC4_RENDER_CONFIG_FORMAT_BGR565 :
VC4_RENDER_CONFIG_FORMAT_RGBA8888)));
cl_u16(&vc4->rcl,
VC4_SET_FIELD(render_surf->tiling,
VC4_RENDER_CONFIG_MEMORY_FORMAT) |
VC4_SET_FIELD((vc4_rt_format_is_565(render_surf->base.format) ?
VC4_RENDER_CONFIG_FORMAT_BGR565 :
VC4_RENDER_CONFIG_FORMAT_RGBA8888),
VC4_RENDER_CONFIG_FORMAT));
/* The tile buffer normally gets cleared when the previous tile is
* stored. If the clear values changed between frames, then the tile
@@ -193,14 +197,15 @@ vc4_setup_rcl(struct vc4_context *vc4)
cl_start_reloc(&vc4->rcl, 1);
cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
cl_u8(&vc4->rcl,
VC4_LOADSTORE_TILE_BUFFER_COLOR |
(csurf->tiling <<
VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
cl_u8(&vc4->rcl,
vc4_rt_format_is_565(csurf->base.format) ?
VC4_LOADSTORE_TILE_BUFFER_BGR565 :
VC4_LOADSTORE_TILE_BUFFER_RGBA8888);
cl_u16(&vc4->rcl,
VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_COLOR,
VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
VC4_SET_FIELD(csurf->tiling,
VC4_LOADSTORE_TILE_BUFFER_TILING) |
VC4_SET_FIELD(vc4_rt_format_is_565(csurf->base.format) ?
VC4_LOADSTORE_TILE_BUFFER_BGR565 :
VC4_LOADSTORE_TILE_BUFFER_RGBA8888,
VC4_LOADSTORE_TILE_BUFFER_FORMAT));
cl_reloc_hindex(&vc4->rcl, color_hindex,
csurf->offset);
@@ -212,11 +217,11 @@ vc4_setup_rcl(struct vc4_context *vc4)
cl_start_reloc(&vc4->rcl, 1);
cl_u8(&vc4->rcl, VC4_PACKET_LOAD_TILE_BUFFER_GENERAL);
cl_u8(&vc4->rcl,
VC4_LOADSTORE_TILE_BUFFER_ZS |
(zsurf->tiling <<
VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
cl_u8(&vc4->rcl, 0);
cl_u16(&vc4->rcl,
VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_ZS,
VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
VC4_SET_FIELD(zsurf->tiling,
VC4_LOADSTORE_TILE_BUFFER_TILING));
cl_reloc_hindex(&vc4->rcl, depth_hindex,
zsurf->offset);
@@ -245,12 +250,12 @@ vc4_setup_rcl(struct vc4_context *vc4)
cl_start_reloc(&vc4->rcl, 1);
cl_u8(&vc4->rcl, VC4_PACKET_STORE_TILE_BUFFER_GENERAL);
cl_u8(&vc4->rcl,
VC4_LOADSTORE_TILE_BUFFER_ZS |
(zsurf->tiling <<
VC4_LOADSTORE_TILE_BUFFER_FORMAT_SHIFT));
cl_u8(&vc4->rcl,
VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR);
cl_u16(&vc4->rcl,
VC4_SET_FIELD(VC4_LOADSTORE_TILE_BUFFER_ZS,
VC4_LOADSTORE_TILE_BUFFER_BUFFER) |
VC4_SET_FIELD(zsurf->tiling,
VC4_LOADSTORE_TILE_BUFFER_TILING) |
VC4_STORE_TILE_BUFFER_DISABLE_COLOR_CLEAR);
cl_reloc_hindex(&vc4->rcl, depth_hindex,
zsurf->offset |
((end_of_frame &&