radeonsi: update surface sync packet emit for CIK
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -60,10 +60,21 @@ void si_cmd_draw_index_auto(struct si_pm4_state *pm4, uint32_t count,
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void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
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{
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si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
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si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
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si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
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si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
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si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
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si_pm4_cmd_end(pm4, false);
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if (pm4->chip_class >= CIK) {
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si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
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si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
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si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
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si_pm4_cmd_add(pm4, 0xff); /* CP_COHER_SIZE_HI */
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si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
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si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE_HI */
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si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
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si_pm4_cmd_end(pm4, false);
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} else {
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si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
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si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
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si_pm4_cmd_add(pm4, 0xffffffff); /* CP_COHER_SIZE */
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si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
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si_pm4_cmd_add(pm4, 0x0000000A); /* POLL_INTERVAL */
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si_pm4_cmd_end(pm4, false);
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}
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}
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