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i965: Fix inconsistent indentation in brw_gs_emit.c.

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This commit is contained in:
Kenneth Graunke
2011-11-13 22:41:06 -08:00
parent 5e3e9a8e9c
commit 728a830fae
1 changed files with 32 additions and 32 deletions
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src/mesa/drivers/dri/i965/brw_gs_emit.c
+32 -32
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@@ -76,11 +76,11 @@ static void brw_gs_emit_vue(struct brw_gs_compile *c,
struct brw_reg temp;
if (intel->gen < 6)
temp = c->reg.R0;
temp = c->reg.R0;
else {
temp = c->reg.temp;
brw_MOV(p, retype(temp, BRW_REGISTER_TYPE_UD),
retype(c->reg.R0, BRW_REGISTER_TYPE_UD));
temp = c->reg.temp;
brw_MOV(p, retype(temp, BRW_REGISTER_TYPE_UD),
retype(c->reg.R0, BRW_REGISTER_TYPE_UD));
}
/* Overwrite PrimType and PrimStart in the message header, for
@@ -117,32 +117,32 @@ static void brw_gs_emit_vue(struct brw_gs_compile *c,
static void brw_gs_ff_sync(struct brw_gs_compile *c, int num_prim)
{
struct brw_compile *p = &c->func;
struct intel_context *intel = &c->func.brw->intel;
struct brw_compile *p = &c->func;
struct intel_context *intel = &c->func.brw->intel;
if (intel->gen < 6) {
brw_MOV(p, get_element_ud(c->reg.R0, 1), brw_imm_ud(num_prim));
brw_ff_sync(p,
c->reg.R0,
0,
c->reg.R0,
1, /* allocate */
1, /* response length */
0 /* eot */);
} else {
brw_MOV(p, retype(c->reg.temp, BRW_REGISTER_TYPE_UD),
retype(c->reg.R0, BRW_REGISTER_TYPE_UD));
brw_MOV(p, get_element_ud(c->reg.temp, 1), brw_imm_ud(num_prim));
brw_ff_sync(p,
c->reg.temp,
0,
c->reg.temp,
1, /* allocate */
1, /* response length */
0 /* eot */);
brw_MOV(p, get_element_ud(c->reg.R0, 0),
get_element_ud(c->reg.temp, 0));
}
if (intel->gen < 6) {
brw_MOV(p, get_element_ud(c->reg.R0, 1), brw_imm_ud(num_prim));
brw_ff_sync(p,
c->reg.R0,
0,
c->reg.R0,
1, /* allocate */
1, /* response length */
0 /* eot */);
} else {
brw_MOV(p, retype(c->reg.temp, BRW_REGISTER_TYPE_UD),
retype(c->reg.R0, BRW_REGISTER_TYPE_UD));
brw_MOV(p, get_element_ud(c->reg.temp, 1), brw_imm_ud(num_prim));
brw_ff_sync(p,
c->reg.temp,
0,
c->reg.temp,
1, /* allocate */
1, /* response length */
0 /* eot */);
brw_MOV(p, get_element_ud(c->reg.R0, 0),
get_element_ud(c->reg.temp, 0));
}
}
@@ -156,7 +156,7 @@ void brw_gs_quads( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
* is the PV for quads, but vertex 0 for polygons:
*/
if (intel->needs_ff_sync)
brw_gs_ff_sync(c, 1);
brw_gs_ff_sync(c, 1);
if (key->pv_first) {
brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START));
brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_POLYGON << 2));
@@ -178,7 +178,7 @@ void brw_gs_quad_strip( struct brw_gs_compile *c, struct brw_gs_prog_key *key )
brw_gs_alloc_regs(c, 4);
if (intel->needs_ff_sync)
brw_gs_ff_sync(c, 1);
brw_gs_ff_sync(c, 1);
if (key->pv_first) {
brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_POLYGON << 2) | R02_PRIM_START));
brw_gs_emit_vue(c, c->reg.vertex[1], 0, (_3DPRIM_POLYGON << 2));
@@ -200,7 +200,7 @@ void brw_gs_lines( struct brw_gs_compile *c )
brw_gs_alloc_regs(c, 2);
if (intel->needs_ff_sync)
brw_gs_ff_sync(c, 1);
brw_gs_ff_sync(c, 1);
brw_gs_emit_vue(c, c->reg.vertex[0], 0, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_START));
brw_gs_emit_vue(c, c->reg.vertex[1], 1, ((_3DPRIM_LINESTRIP << 2) | R02_PRIM_END));
}