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i965: Fix brw_store_register_mem64 to stay within a single batch.

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Previously, the write of each 32-bit half might land in separate batch
buffers, which is insane.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
This commit is contained in:
Kenneth Graunke
2013-10-30 16:06:06 -07:00
parent 5eb0835b91
commit 723f047a3b
1 changed files with 1 additions and 4 deletions
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src/mesa/drivers/dri/i965/gen6_queryobj.c
+1 -4
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@@ -112,14 +112,11 @@ brw_store_register_mem64(struct brw_context *brw,
/* MI_STORE_REGISTER_MEM only stores a single 32-bit value, so to
* read a full 64-bit register, we need to do two of them.
*/
BEGIN_BATCH(3);
BEGIN_BATCH(6);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg);
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,
idx * sizeof(uint64_t));
ADVANCE_BATCH();
BEGIN_BATCH(3);
OUT_BATCH(MI_STORE_REGISTER_MEM | (3 - 2));
OUT_BATCH(reg + sizeof(uint32_t));
OUT_RELOC(bo, I915_GEM_DOMAIN_INSTRUCTION, I915_GEM_DOMAIN_INSTRUCTION,