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nvc0: patch up TEX cases with 5 or 6 sources on nve4

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Hackishly fixes alignment requirement of 2nd tuple for now.
This commit is contained in:
Christoph Bumiller
2013-04-06 17:40:02 +02:00
committed by Christoph Bumiller
parent 2b62ba7cb0
commit 71c1c8a9b8
1 changed files with 19 additions and 1 deletions
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src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
+19 -1
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@@ -728,13 +728,31 @@ NVC0LoweringPass::handleTEX(TexInstruction *i)
if (i->tex.useOffsets) {
uint32_t value = 0;
int n, c;
int s = i->srcCount(0xff);
int s = i->srcCount(0xff, true);
if (i->srcExists(s)) // move potential predicate out of the way
i->moveSources(s, 1);
for (n = 0; n < i->tex.useOffsets; ++n)
for (c = 0; c < 3; ++c)
value |= (i->tex.offset[n][c] & 0xf) << (n * 12 + c * 4);
i->setSrc(s, bld.loadImm(NULL, value));
}
if (prog->getTarget()->getChipset() >= NVISA_GK104_CHIPSET) {
//
// If TEX requires more than 4 sources, the 2nd register tuple must be
// aligned to 4, even if it consists of just a single 4-byte register.
//
// XXX HACK: We insert 0 sources to avoid the 5 or 6 regs case.
//
int s = i->srcCount(0xff, true);
if (s > 4 && s < 7) {
if (i->srcExists(s)) // move potential predicate out of the way
i->moveSources(s, 7 - s);
while (s < 7)
i->setSrc(s++, bld.loadImm(NULL, 0));
}
}
return true;
}