radv: Add radv_spirv_to_nir_options that summarize early gfx states.

radv_shader_spirv_to_nir now takes a more minimal struct instead of gfx
states. This struct will be used for NIR cache hashing in the future.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26696>

src/amd/vulkan/nir/radv_nir.h

@@ -64,7 +64,7 @@ bool radv_nir_lower_fs_intrinsics(nir_shader *nir, const struct radv_shader_stag
 bool radv_nir_lower_fs_barycentric(nir_shader *shader, const struct radv_graphics_state_key *gfx_state,
                                    unsigned rast_prim);
 
-bool radv_nir_lower_intrinsics_early(nir_shader *nir, const struct radv_graphics_state_key *gfx_state);
+bool radv_nir_lower_intrinsics_early(nir_shader *nir, bool lower_view_index_to_zero);
 
 bool radv_nir_lower_view_index(nir_shader *nir, bool per_primitive);
 

src/amd/vulkan/nir/radv_nir_lower_intrinsics_early.c

@@ -29,7 +29,7 @@
 #include "radv_private.h"
 
 bool
-radv_nir_lower_intrinsics_early(nir_shader *nir, const struct radv_graphics_state_key *gfx_state)
+radv_nir_lower_intrinsics_early(nir_shader *nir, bool lower_view_index_to_zero)
 {
    nir_function_impl *entry = nir_shader_get_entrypoint(nir);
    bool progress = false;
@@ -52,7 +52,7 @@ radv_nir_lower_intrinsics_early(nir_shader *nir, const struct radv_graphics_stat
             def = nir_ior(&b, intrin->src[0].ssa, intrin->src[1].ssa);
             break;
          case nir_intrinsic_load_view_index:
-            if (gfx_state->has_multiview_view_index)
+            if (!lower_view_index_to_zero)
                continue;
             def = nir_imm_zero(&b, 1, 32);
             break;

src/amd/vulkan/radv_pipeline_graphics.c

@@ -2468,7 +2468,12 @@ radv_graphics_shaders_compile(struct radv_device *device, struct vk_pipeline_cac
 
       /* NIR might already have been imported from a library. */
       if (!stages[s].nir) {
-         stages[s].nir = radv_shader_spirv_to_nir(device, &stages[s], gfx_state, is_internal);
+         struct radv_spirv_to_nir_options options = {
+            .lower_view_index_to_zero = !gfx_state->has_multiview_view_index,
+            .fix_dual_src_mrt1_export =
+               gfx_state->ps.epilog.mrt0_is_dual_src && device->instance->drirc.dual_color_blend_by_location,
+         };
+         stages[s].nir = radv_shader_spirv_to_nir(device, &stages[s], &options, is_internal);
       }
 
       stages[s].feedback.duration += os_time_get_nano() - stage_start;

src/amd/vulkan/radv_shader.c

@@ -301,7 +301,7 @@ fix_dual_src_mrt1_export(nir_shader *nir)
 
 nir_shader *
 radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_stage *stage,
-                         const struct radv_graphics_state_key *gfx_state, bool is_internal)
+                         const struct radv_spirv_to_nir_options *options, bool is_internal)
 {
    unsigned subgroup_size = 64, ballot_bit_size = 64;
    const unsigned required_subgroup_size = stage->key.subgroup_required_size * 32;
@@ -495,8 +495,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
       NIR_PASS(_, nir, nir_remove_dead_variables,
                nir_var_shader_in | nir_var_shader_out | nir_var_system_value | nir_var_mem_shared, &dead_vars_opts);
 
-      if (nir->info.stage == MESA_SHADER_FRAGMENT && gfx_state->ps.epilog.mrt0_is_dual_src &&
-          device->instance->drirc.dual_color_blend_by_location)
+      if (nir->info.stage == MESA_SHADER_FRAGMENT && options->fix_dual_src_mrt1_export)
          fix_dual_src_mrt1_export(nir);
 
       /* Variables can make nir_propagate_invariant more conservative
@@ -653,7 +652,7 @@ radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_st
    NIR_PASS(_, nir, nir_lower_explicit_io, nir_var_mem_ubo | nir_var_mem_ssbo,
             nir_address_format_vec2_index_32bit_offset);
 
-   NIR_PASS(_, nir, radv_nir_lower_intrinsics_early, gfx_state);
+   NIR_PASS(_, nir, radv_nir_lower_intrinsics_early, options && options->lower_view_index_to_zero);
 
    /* Lower deref operations for compute shared memory. */
    if (nir->info.stage == MESA_SHADER_COMPUTE || nir->info.stage == MESA_SHADER_TASK ||

src/amd/vulkan/radv_shader.h

@@ -120,6 +120,11 @@ struct radv_ps_epilog_key {
    bool alpha_to_coverage_via_mrtz;
 };
 
+struct radv_spirv_to_nir_options {
+   uint32_t lower_view_index_to_zero : 1;
+   uint32_t fix_dual_src_mrt1_export : 1;
+};
+
 struct radv_graphics_state_key {
    uint32_t lib_flags : 4; /* VkGraphicsPipelineLibraryFlagBitsEXT */
 
@@ -780,7 +785,7 @@ void radv_nir_lower_rt_abi(nir_shader *shader, const VkRayTracingPipelineCreateI
 struct radv_shader_stage;
 
 nir_shader *radv_shader_spirv_to_nir(struct radv_device *device, const struct radv_shader_stage *stage,
-                                     const struct radv_graphics_state_key *gfx_state, bool is_internal);
+                                     const struct radv_spirv_to_nir_options *options, bool is_internal);
 
 void radv_init_shader_arenas(struct radv_device *device);
 void radv_destroy_shader_arenas(struct radv_device *device);