nvk: Support base instance in instanced draw calls
Vulkan's gl_InstanceIndex is different than OpenGL gl_InstanceID. For nvk, gl_InstanceIndex is lowered as gl_BaseInstance + gl_InstanceID in nir code. This means we need to supply base instance to the vertex shader. We load the value at mme draw time to a root constant, as it seems there is no existing system value corresponding to this info. Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24326>
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Marge Bot
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@@ -21,6 +21,12 @@ struct nvk_push_descriptor_set;
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/** Root descriptor table. This gets pushed to the GPU directly */
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struct nvk_root_descriptor_table {
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union {
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struct {
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uint32_t base_vertex;
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uint32_t base_instance;
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uint32_t draw_id;
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uint32_t _pad[5];
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} draw;
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struct {
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uint32_t block_size[3];
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uint32_t grid_size[3];
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@@ -33,7 +33,7 @@ nvk_queue_init_context_draw_state(struct nvk_queue *queue)
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{
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struct nvk_device *dev = nvk_queue_device(queue);
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uint32_t push_data[768];
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uint32_t push_data[1024];
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struct nv_push push;
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nv_push_init(&push, push_data, ARRAY_SIZE(push_data));
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struct nv_push *p = &push;
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@@ -1433,6 +1433,14 @@ nvk_build_mme_draw(struct mme_builder *b, struct mme_value begin)
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struct mme_value first_vertex = mme_load(b);
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struct mme_value first_instance = mme_load(b);
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// load base instance in root descriptor
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const uint32_t base_instance_offset =
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nvk_root_descriptor_offset(draw.base_instance);
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mme_mthd(b, NV9097_LOAD_CONSTANT_BUFFER_OFFSET);
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mme_emit(b, mme_imm(base_instance_offset));
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mme_mthd(b, NV9097_LOAD_CONSTANT_BUFFER(0));
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mme_emit(b, first_instance);
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mme_mthd(b, NV9097_SET_GLOBAL_BASE_VERTEX_INDEX);
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mme_emit(b, mme_zero());
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@@ -1511,6 +1519,14 @@ nvk_mme_build_draw_indexed(struct mme_builder *b,
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struct mme_value vertex_offset = mme_load(b);
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struct mme_value first_instance = mme_load(b);
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// load base instance in root descriptor
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const uint32_t base_instance_offset =
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nvk_root_descriptor_offset(draw.base_instance);
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mme_mthd(b, NV9097_LOAD_CONSTANT_BUFFER_OFFSET);
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mme_emit(b, mme_imm(base_instance_offset));
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mme_mthd(b, NV9097_LOAD_CONSTANT_BUFFER(0));
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mme_emit(b, first_instance);
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mme_mthd(b, NV9097_SET_GLOBAL_BASE_VERTEX_INDEX);
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mme_emit(b, vertex_offset);
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@@ -668,10 +668,10 @@ nvk_compile_nir(struct nvk_physical_device *device, nir_shader *nir,
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info->bin.smemSize = shader->cp.smem_size;
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info->dbgFlags = debug_get_num_option("NV50_PROG_DEBUG", 0);
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info->optLevel = debug_get_num_option("NV50_PROG_OPTIMIZE", 3);
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info->io.auxCBSlot = 15;
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info->io.auxCBSlot = 1;
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info->io.uboInfoBase = 0;
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info->io.drawInfoBase = 0;
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if (nir->info.stage == MESA_SHADER_COMPUTE) {
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info->io.auxCBSlot = 1;
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info->prop.cp.gridInfoBase = 0;
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} else {
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info->assignSlots = nvc0_program_assign_varying_slots;
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