radv,aco: use the trap handler layout struct while compiling the shader

It's less error prone to rely on the layout for offsets.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32056>

src/amd/compiler/aco_instruction_selection.cpp

@@ -12455,6 +12455,8 @@ select_trap_handler_shader(Program* program, ac_shader_config* config,
                            const struct aco_compiler_options* options,
                            const struct aco_shader_info* info, const struct ac_shader_args* args)
 {
+   uint32_t offset = 0;
+
    assert(options->gfx_level >= GFX8 && options->gfx_level <= GFX11);
 
    init_program(program, compute_cs, info, options->gfx_level, options->family, options->wgp_mode,
@@ -12505,6 +12507,8 @@ select_trap_handler_shader(Program* program, ac_shader_config* config,
       bld.vop1(aco_opcode::v_clrexcp);
    }
 
+   offset = offsetof(struct aco_trap_handler_layout, ttmp0);
+
    if (ctx.program->gfx_level >= GFX9) {
       /* Get TMA. */
       if (ctx.program->gfx_level >= GFX11) {
@@ -12526,7 +12530,7 @@ select_trap_handler_shader(Program* program, ac_shader_config* config,
       bld.copy(Definition(PhysReg{256}, v2) /* v[0-1] */, Operand(ttmp0_reg, s2));
 
       bld.mubuf(aco_opcode::buffer_store_dwordx2, Operand(tma_rsrc, s4), Operand(v1),
-                Operand::c32(0u), Operand(PhysReg{256}, v2) /* v[0-1] */, 0 /* offset */,
+                Operand::c32(0u), Operand(PhysReg{256}, v2) /* v[0-1] */, offset /* offset */,
                 false /* offen */, false /* idxen */, /* addr64 */ false,
                 /* disable_wqm */ false, cache_glc);
    } else {
@@ -12535,7 +12539,7 @@ select_trap_handler_shader(Program* program, ac_shader_config* config,
                Operand::zero());
 
       /* Store TTMP0-TTMP1. */
-      bld.smem(aco_opcode::s_buffer_store_dwordx2, Operand(tma_rsrc, s4), Operand::zero(),
+      bld.smem(aco_opcode::s_buffer_store_dwordx2, Operand(tma_rsrc, s4), Operand::c32(offset),
                Operand(ttmp0_reg, s2), memory_sync_info(), cache_glc);
    }
 
@@ -12548,7 +12552,8 @@ select_trap_handler_shader(Program* program, ac_shader_config* config,
       6, /* WH_REG_LDS_ALLOC */
       7, /* HW_REG_IB_STS */
    };
-   uint32_t offset = 8;
+
+   offset = offsetof(struct aco_trap_handler_layout, sq_wave_regs.status);
 
    /* Store saved SQ_WAVE_STATUS which can change inside the trap. */
    dump_sgpr_to_mem(&ctx, Operand(tma_rsrc, s4), Operand(save_wave_status, s1), offset);
@@ -12563,6 +12568,8 @@ select_trap_handler_shader(Program* program, ac_shader_config* config,
       offset += 4;
    }
 
+   assert(offset == offsetof(struct aco_trap_handler_layout, m0));
+
    /* Dump shader registers (m0, exec). */
    dump_sgpr_to_mem(&ctx, Operand(tma_rsrc, s4), Operand(save_m0, s1), offset);
    offset += 4;
@@ -12571,6 +12578,8 @@ select_trap_handler_shader(Program* program, ac_shader_config* config,
    dump_sgpr_to_mem(&ctx, Operand(tma_rsrc, s4), Operand(save_exec_hi, s1), offset);
    offset += 4;
 
+   assert(offset == offsetof(struct aco_trap_handler_layout, sgprs[0]));
+
    /* Dump all SGPRs. */
    for (uint32_t i = 0; i < program->dev.sgpr_limit; i++) {
       dump_sgpr_to_mem(&ctx, Operand(tma_rsrc, s4), Operand(PhysReg{i}, s1), offset);

src/amd/compiler/aco_shader_info.h

@@ -196,6 +196,28 @@ struct aco_symbol {
    unsigned offset;
 };
 
+#define MAX_SGPRS 108
+
+struct aco_trap_handler_layout {
+   uint32_t ttmp0;
+   uint32_t ttmp1;
+
+   struct {
+      uint32_t status;
+      uint32_t mode;
+      uint32_t trap_sts;
+      uint32_t hw_id1;
+      uint32_t gpr_alloc;
+      uint32_t lds_alloc;
+      uint32_t ib_sts;
+   } sq_wave_regs;
+
+   uint32_t m0;
+   uint32_t exec_lo;
+   uint32_t exec_hi;
+   uint32_t sgprs[MAX_SGPRS];
+};
+
 #ifdef __cplusplus
 }
 #endif

src/amd/vulkan/radv_debug.c

@@ -994,30 +994,8 @@ radv_dump_faulty_shader(struct radv_device *device, uint64_t faulty_pc, FILE *f)
    free(instructions);
 }
 
-#define MAX_SGPRS 108
-
-struct radv_trap_handler_layout {
-   uint32_t ttmp0;
-   uint32_t ttmp1;
-
-   struct {
-      uint32_t status;
-      uint32_t mode;
-      uint32_t trap_sts;
-      uint32_t hw_id1;
-      uint32_t gpr_alloc;
-      uint32_t lds_alloc;
-      uint32_t ib_sts;
-   } sq_wave_regs;
-
-   uint32_t m0;
-   uint32_t exec_lo;
-   uint32_t exec_hi;
-   uint32_t sgprs[MAX_SGPRS];
-};
-
 static void
-radv_dump_sq_hw_regs(struct radv_device *device, const struct radv_trap_handler_layout *layout, FILE *f)
+radv_dump_sq_hw_regs(struct radv_device *device, const struct aco_trap_handler_layout *layout, FILE *f)
 {
    const struct radv_physical_device *pdev = radv_device_physical(device);
    enum amd_gfx_level gfx_level = pdev->info.gfx_level;
@@ -1045,7 +1023,7 @@ radv_dump_sq_hw_regs(struct radv_device *device, const struct radv_trap_handler_
 }
 
 static void
-radv_dump_shader_regs(const struct radv_trap_handler_layout *layout, FILE *f)
+radv_dump_shader_regs(const struct aco_trap_handler_layout *layout, FILE *f)
 {
    fprintf(f, "\nShader registers:\n");
 
@@ -1067,7 +1045,7 @@ radv_check_trap_handler(struct radv_queue *queue)
    enum amd_ip_type ring = radv_queue_ring(queue);
    struct radv_device *device = radv_queue_device(queue);
    struct radeon_winsys *ws = device->ws;
-   const struct radv_trap_handler_layout *layout = (struct radv_trap_handler_layout *)&device->tma_ptr[4];
+   const struct aco_trap_handler_layout *layout = (struct aco_trap_handler_layout *)&device->tma_ptr[4];
 
    /* Wait for the context to be idle in a finite time. */
    ws->ctx_wait_idle(queue->hw_ctx, ring, queue->vk.index_in_family);