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dzn: Use DEPTH_STENCIL_DESC2 for front/back stencil read/write masks

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Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19537>
This commit is contained in:
Jesse Natalie
2022-08-26 10:14:26 -07:00
committed by Marge Bot
parent 73c9cfb61b
commit 6e7896aa44
3 changed files with 60 additions and 63 deletions
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src/microsoft/ci/warp-skips.txt
-6
View File
@@ -1,9 +1,3 @@
# We don't support independent front/back stencil tests yet, and the check
# is currently done at pipeline creation time, thus causing a crash any time
# both the front/back stencil test are active (i.e. not always or never) and
# any of the compare mask, reference value or write mask is dynamic.
dEQP-VK.api.command_buffers.record_many_draws*
# Those tests timeout in CI, so let's skip for now.
dEQP-VK.dynamic_state.ds_state.stencil_params*
src/microsoft/vulkan/dzn_pipeline.c
+56 -55
View File
@@ -1222,7 +1222,7 @@ translate_stencil_op(VkStencilOp in)
static void
translate_stencil_test(struct dzn_graphics_pipeline *pipeline,
D3D12_DEPTH_STENCIL_DESC1 *out,
D3D12_DEPTH_STENCIL_DESC2 *out,
const VkGraphicsPipelineCreateInfo *in)
{
const VkPipelineDepthStencilStateCreateInfo *in_zsa =
@@ -1255,18 +1255,6 @@ translate_stencil_test(struct dzn_graphics_pipeline *pipeline,
else
pipeline->zsa.stencil_test.back.compare_mask = 0;
bool diff_wr_mask =
in->pRasterizationState->cullMode == VK_CULL_MODE_NONE &&
(pipeline->zsa.stencil_test.dynamic_write_mask ||
in_zsa->back.writeMask != in_zsa->front.writeMask);
bool diff_cmp_mask =
back_test_uses_ref && front_test_uses_ref &&
(pipeline->zsa.stencil_test.dynamic_compare_mask ||
pipeline->zsa.stencil_test.front.compare_mask != pipeline->zsa.stencil_test.back.compare_mask);
if (diff_cmp_mask || diff_wr_mask)
pipeline->zsa.stencil_test.independent_front_back = true;
bool back_wr_uses_ref =
!(in->pRasterizationState->cullMode & VK_CULL_MODE_BACK_BIT) &&
((in_zsa->back.compareOp != VK_COMPARE_OP_ALWAYS &&
@@ -1305,28 +1293,21 @@ translate_stencil_test(struct dzn_graphics_pipeline *pipeline,
pipeline->zsa.stencil_test.back.ref =
pipeline->zsa.stencil_test.dynamic_ref ? 0 : in_zsa->back.reference;
/* FIXME: We don't support independent {compare,write}_mask.
* Until we have proper support for independent front/back
* stencil test, let's prioritize the front setup when both are active.
*/
out->StencilReadMask =
front_test_uses_ref ?
pipeline->zsa.stencil_test.front.compare_mask :
back_test_uses_ref ?
pipeline->zsa.stencil_test.back.compare_mask : 0;
out->StencilWriteMask =
pipeline->zsa.stencil_test.front.write_mask ?
pipeline->zsa.stencil_test.front.write_mask :
pipeline->zsa.stencil_test.back.write_mask;
assert(!pipeline->zsa.stencil_test.independent_front_back);
out->FrontFace.StencilReadMask = pipeline->zsa.stencil_test.front.compare_mask;
out->BackFace.StencilReadMask = pipeline->zsa.stencil_test.back.compare_mask;
out->FrontFace.StencilWriteMask = pipeline->zsa.stencil_test.front.write_mask;
out->BackFace.StencilWriteMask = pipeline->zsa.stencil_test.back.write_mask;
}
static void
dzn_graphics_pipeline_translate_zsa(struct dzn_graphics_pipeline *pipeline,
dzn_graphics_pipeline_translate_zsa(struct dzn_device *device,
struct dzn_graphics_pipeline *pipeline,
D3D12_PIPELINE_STATE_STREAM_DESC *out,
const VkGraphicsPipelineCreateInfo *in)
{
struct dzn_physical_device *pdev =
container_of(device->vk.physical, struct dzn_physical_device, vk);
const VkPipelineRasterizationStateCreateInfo *in_rast =
in->pRasterizationState;
const VkPipelineDepthStencilStateCreateInfo *in_zsa =
@@ -1335,45 +1316,65 @@ dzn_graphics_pipeline_translate_zsa(struct dzn_graphics_pipeline *pipeline,
if (!in_zsa)
return;
d3d12_gfx_pipeline_state_stream_new_desc(out, DEPTH_STENCIL1, D3D12_DEPTH_STENCIL_DESC1, desc);
pipeline->templates.desc_offsets.ds =
(uintptr_t)desc - (uintptr_t)out->pPipelineStateSubobjectStream;
D3D12_DEPTH_STENCIL_DESC2 desc;
memset(&desc, 0, sizeof(desc));
desc->DepthEnable =
desc.DepthEnable =
in_zsa->depthTestEnable || in_zsa->depthBoundsTestEnable;
desc->DepthWriteMask =
desc.DepthWriteMask =
in_zsa->depthWriteEnable ?
D3D12_DEPTH_WRITE_MASK_ALL : D3D12_DEPTH_WRITE_MASK_ZERO;
desc->DepthFunc =
desc.DepthFunc =
in_zsa->depthTestEnable ?
dzn_translate_compare_op(in_zsa->depthCompareOp) :
D3D12_COMPARISON_FUNC_ALWAYS;
pipeline->zsa.depth_bounds.enable = in_zsa->depthBoundsTestEnable;
pipeline->zsa.depth_bounds.min = in_zsa->minDepthBounds;
pipeline->zsa.depth_bounds.max = in_zsa->maxDepthBounds;
desc->DepthBoundsTestEnable = in_zsa->depthBoundsTestEnable;
desc->StencilEnable = in_zsa->stencilTestEnable;
desc.DepthBoundsTestEnable = in_zsa->depthBoundsTestEnable;
desc.StencilEnable = in_zsa->stencilTestEnable;
if (in_zsa->stencilTestEnable) {
desc->FrontFace.StencilFailOp =
translate_stencil_op(in_zsa->front.failOp);
desc->FrontFace.StencilDepthFailOp =
translate_stencil_op(in_zsa->front.depthFailOp);
desc->FrontFace.StencilPassOp =
translate_stencil_op(in_zsa->front.passOp);
desc->FrontFace.StencilFunc =
dzn_translate_compare_op(in_zsa->front.compareOp);
desc->BackFace.StencilFailOp =
translate_stencil_op(in_zsa->back.failOp);
desc->BackFace.StencilDepthFailOp =
translate_stencil_op(in_zsa->back.depthFailOp);
desc->BackFace.StencilPassOp =
translate_stencil_op(in_zsa->back.passOp);
desc->BackFace.StencilFunc =
dzn_translate_compare_op(in_zsa->back.compareOp);
desc.FrontFace.StencilFailOp = translate_stencil_op(in_zsa->front.failOp);
desc.FrontFace.StencilDepthFailOp = translate_stencil_op(in_zsa->front.depthFailOp);
desc.FrontFace.StencilPassOp = translate_stencil_op(in_zsa->front.passOp);
desc.FrontFace.StencilFunc = dzn_translate_compare_op(in_zsa->front.compareOp);
desc.BackFace.StencilFailOp = translate_stencil_op(in_zsa->back.failOp);
desc.BackFace.StencilDepthFailOp = translate_stencil_op(in_zsa->back.depthFailOp);
desc.BackFace.StencilPassOp = translate_stencil_op(in_zsa->back.passOp);
desc.BackFace.StencilFunc = dzn_translate_compare_op(in_zsa->back.compareOp);
pipeline->zsa.stencil_test.enable = true;
translate_stencil_test(pipeline, desc, in);
translate_stencil_test(pipeline, &desc, in);
}
if (pdev->options14.IndependentFrontAndBackStencilRefMaskSupported) {
d3d12_gfx_pipeline_state_stream_new_desc(out, DEPTH_STENCIL2, D3D12_DEPTH_STENCIL_DESC2, stream_desc);
pipeline->templates.desc_offsets.ds =
(uintptr_t)stream_desc - (uintptr_t)out->pPipelineStateSubobjectStream;
*stream_desc = desc;
} else {
d3d12_gfx_pipeline_state_stream_new_desc(out, DEPTH_STENCIL1, D3D12_DEPTH_STENCIL_DESC1, stream_desc);
pipeline->templates.desc_offsets.ds =
(uintptr_t)stream_desc - (uintptr_t)out->pPipelineStateSubobjectStream;
stream_desc->DepthEnable = desc.DepthEnable;
stream_desc->DepthWriteMask = desc.DepthWriteMask;
stream_desc->DepthFunc = desc.DepthFunc;
stream_desc->DepthBoundsTestEnable = desc.DepthBoundsTestEnable;
stream_desc->StencilEnable = desc.StencilEnable;
stream_desc->FrontFace.StencilFailOp = desc.FrontFace.StencilFailOp;
stream_desc->FrontFace.StencilDepthFailOp = desc.FrontFace.StencilDepthFailOp;
stream_desc->FrontFace.StencilPassOp = desc.FrontFace.StencilPassOp;
stream_desc->FrontFace.StencilFunc = desc.FrontFace.StencilFunc;
stream_desc->BackFace.StencilFailOp = desc.BackFace.StencilFailOp;
stream_desc->BackFace.StencilDepthFailOp = desc.BackFace.StencilDepthFailOp;
stream_desc->BackFace.StencilPassOp = desc.BackFace.StencilPassOp;
stream_desc->BackFace.StencilFunc = desc.BackFace.StencilFunc;
/* No support for independent front/back, just pick front (if set, else back) */
stream_desc->StencilReadMask = desc.FrontFace.StencilReadMask ? desc.FrontFace.StencilReadMask : desc.BackFace.StencilReadMask;
stream_desc->StencilWriteMask = desc.FrontFace.StencilWriteMask ? desc.FrontFace.StencilWriteMask : desc.BackFace.StencilWriteMask;
}
}
@@ -1681,7 +1682,7 @@ dzn_graphics_pipeline_create(struct dzn_device *device,
dzn_graphics_pipeline_translate_rast(pipeline, stream_desc, pCreateInfo);
dzn_graphics_pipeline_translate_ms(pipeline, stream_desc, pCreateInfo);
dzn_graphics_pipeline_translate_zsa(pipeline, stream_desc, pCreateInfo);
dzn_graphics_pipeline_translate_zsa(device, pipeline, stream_desc, pCreateInfo);
dzn_graphics_pipeline_translate_blend(pipeline, stream_desc, pCreateInfo);
if (pass) {
src/microsoft/vulkan/dzn_private.h
+4 -2
View File
@@ -716,6 +716,9 @@ enum dzn_register_space {
#define D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(__type) \
ALIGN_POT(ALIGN_POT(sizeof(D3D12_PIPELINE_STATE_SUBOBJECT_TYPE), alignof(__type)) + sizeof(__type), alignof(void *))
static_assert(sizeof(D3D12_DEPTH_STENCIL_DESC2) > sizeof(D3D12_DEPTH_STENCIL_DESC1),
"Using just one of these descs in the max size calculation");
#define MAX_GFX_PIPELINE_STATE_STREAM_SIZE \
D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(ID3D12RootSignature *) + \
(D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_SHADER_BYTECODE) * 5) + /* VS, PS, DS, HS, GS */ \
@@ -732,7 +735,7 @@ enum dzn_register_space {
D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_NODE_MASK) + \
D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_CACHED_PIPELINE_STATE) + \
D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_PIPELINE_STATE_FLAGS) + \
D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_DEPTH_STENCIL_DESC1) + \
D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_DEPTH_STENCIL_DESC2) + \
D3D12_PIPELINE_STATE_STREAM_DESC_SIZE(D3D12_VIEW_INSTANCING_DESC)
#define MAX_COMPUTE_PIPELINE_STATE_STREAM_SIZE \
@@ -799,7 +802,6 @@ struct dzn_graphics_pipeline {
struct {
struct {
bool enable;
bool independent_front_back;
bool dynamic_ref;
bool dynamic_write_mask;
bool dynamic_compare_mask;