AlexIndustrial/mesa
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

i965/nir: Dot not assign direct uniform locations first for vec4-based shaders

Browse Source 
In the vec4 backend we want uniform locations to be assigned consecutively
since that way the offsets produced by nir_lower_io are exactly what we
need to implement nir_intrinsic_load_uniform. Otherwise we would need a
mapping to match the output of nir_lower_io to the actual uniform registers
we need to use.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
This commit is contained in:
Iago Toral Quiroga
2015-07-03 08:23:33 +02:00
committed by Jason Ekstrand
parent 01f6235020
commit 6e58fc56a5
1 changed files with 10 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/mesa/drivers/dri/i965/brw_nir.c
+10 -4
View File
@@ -101,10 +101,16 @@ brw_create_nir(struct brw_context *brw,
/* Get rid of split copies */
nir_optimize(nir);
nir_assign_var_locations_direct_first(nir, &nir->uniforms,
&nir->num_direct_uniforms,
&nir->num_uniforms,
is_scalar);
if (is_scalar) {
nir_assign_var_locations_direct_first(nir, &nir->uniforms,
&nir->num_direct_uniforms,
&nir->num_uniforms,
is_scalar);
} else {
nir_assign_var_locations(&nir->uniforms,
&nir->num_uniforms,
is_scalar);
}
nir_assign_var_locations(&nir->inputs, &nir->num_inputs, is_scalar);
nir_assign_var_locations(&nir->outputs, &nir->num_outputs, is_scalar);