iris: Delete unused bo->cache_coherent flag
This was used in the heuristics for deciding whether to CPU map, but those have since been deleted, so this is now unused. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11644>
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@@ -651,7 +651,6 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
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bo->name = name;
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p_atomic_set(&bo->refcount, 1);
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bo->reusable = bucket && bufmgr->bo_reuse;
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bo->cache_coherent = bufmgr->has_llc;
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bo->index = -1;
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bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS | EXEC_OBJECT_PINNED;
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@@ -667,8 +666,8 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
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/* On integrated GPUs, enable snooping to ensure coherency if needed.
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* For discrete, we instead use SMEM and avoid WB maps for coherency.
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*/
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if (bufmgr->vram.size == 0 &&
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(flags & BO_ALLOC_COHERENT) && !bo->cache_coherent) {
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if ((flags & BO_ALLOC_COHERENT) &&
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!bufmgr->has_llc && bufmgr->vram.size == 0) {
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struct drm_i915_gem_caching arg = {
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.handle = bo->gem_handle,
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.caching = 1,
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@@ -676,7 +675,6 @@ iris_bo_alloc(struct iris_bufmgr *bufmgr,
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if (intel_ioctl(bufmgr->fd, DRM_IOCTL_I915_GEM_SET_CACHING, &arg) != 0)
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goto err_free;
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bo->cache_coherent = true;
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bo->reusable = false;
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}
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@@ -735,7 +733,6 @@ iris_bo_create_userptr(struct iris_bufmgr *bufmgr, const char *name,
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p_atomic_set(&bo->refcount, 1);
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bo->userptr = true;
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bo->cache_coherent = true;
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bo->index = -1;
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bo->idle = true;
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bo->mmap_mode = IRIS_MMAP_WB;
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@@ -1338,7 +1335,6 @@ iris_bo_mark_exported_locked(struct iris_bo *bo)
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* display HW. So make sure our CPU mappings don't assume cache
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* coherency since display is outside that cache.
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*/
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bo->cache_coherent = false;
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bo->exported = true;
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bo->reusable = false;
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}
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@@ -229,11 +229,6 @@ struct iris_bo {
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/** Has this buffer been exported to external clients? */
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bool exported;
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/**
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* Boolean of whether this buffer is cache coherent
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*/
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bool cache_coherent;
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/**
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* Boolean of whether this buffer points into user memory
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*/
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