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radv/gfx10: update DB_DFSM_CONTROL register

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Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
This commit is contained in:
Samuel Pitoiset
2019-06-25 10:53:17 +02:00
committed by Bas Nieuwenhuizen
parent 2435b571de
commit 6b9dbb28ef
1 changed files with 8 additions and 2 deletions
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src/amd/vulkan/radv_pipeline.c
+8 -2
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@@ -2720,8 +2720,14 @@ radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
radeon_set_context_reg(ctx_cs, R_028C44_PA_SC_BINNER_CNTL_0,
pa_sc_binner_cntl_0);
radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
db_dfsm_control);
if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
radeon_set_context_reg(ctx_cs, R_028038_DB_DFSM_CONTROL,
db_dfsm_control);
} else {
radeon_set_context_reg(ctx_cs, R_028060_DB_DFSM_CONTROL,
db_dfsm_control);
}
}