ilo: add support for stencil resources on GEN7+
For allocations, we need to support stencil-only and separate stencil resources. For mapping, we need to support software tiling and packing/unpacking for separate stencil resources.
This commit is contained in:
@@ -59,6 +59,7 @@ struct ilo_dev_info {
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int devid;
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bool has_llc;
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bool has_gen7_sol_reset;
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bool has_address_swizzling;
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int gen;
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int gt;
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@@ -72,7 +72,7 @@ ilo_translate_format(enum pipe_format format, unsigned bind)
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* one such example). We have to live with that at least for now.
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*
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* For ETC1 format, the texture data will be decompressed before being
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* written to the bo. See transfer_unmap_sys_convert().
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* written to the bo. See tex_staging_sys_convert_write().
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*/
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switch (format) {
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case PIPE_FORMAT_Z16_UNORM:
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@@ -3674,6 +3674,9 @@ gen6_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
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surface_type = ilo_gpe_gen6_translate_texture(tex->base.target);
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assert(surface_type != BRW_SURFACE_BUFFER);
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if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && tex->separate_s8)
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format = PIPE_FORMAT_Z32_FLOAT;
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if (is_rt)
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surface_format = ilo_translate_render_format(format);
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else
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@@ -1424,6 +1424,9 @@ gen7_fill_normal_SURFACE_STATE(const struct ilo_dev_info *dev,
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surface_type = ilo_gpe_gen6_translate_texture(tex->base.target);
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assert(surface_type != BRW_SURFACE_BUFFER);
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if (format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT && tex->separate_s8)
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format = PIPE_FORMAT_Z32_FLOAT;
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if (is_rt)
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surface_format = ilo_translate_render_format(format);
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else
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@@ -38,7 +38,7 @@ struct tex_layout {
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enum pipe_format format;
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unsigned block_width, block_height, block_size;
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bool compressed;
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bool has_depth, has_stencil;
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bool has_depth, has_stencil, separate_stencil;
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enum intel_tiling_mode tiling;
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bool can_be_linear;
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@@ -571,11 +571,33 @@ tex_layout_init_format(struct tex_layout *layout)
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const struct pipe_resource *templ = layout->templ;
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enum pipe_format format;
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const struct util_format_description *desc;
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bool separate_stencil;
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/* GEN7+ requires separate stencil buffers */
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separate_stencil = (layout->dev->gen >= ILO_GEN(7));
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switch (templ->format) {
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case PIPE_FORMAT_ETC1_RGB8:
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format = PIPE_FORMAT_R8G8B8X8_UNORM;
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break;
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case PIPE_FORMAT_Z24_UNORM_S8_UINT:
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if (separate_stencil) {
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format = PIPE_FORMAT_Z24X8_UNORM;
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layout->separate_stencil = true;
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}
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else {
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format = templ->format;
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}
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break;
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case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
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if (separate_stencil) {
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format = PIPE_FORMAT_Z32_FLOAT;
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layout->separate_stencil = true;
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}
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else {
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format = templ->format;
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}
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break;
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default:
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format = templ->format;
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break;
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@@ -906,6 +928,9 @@ tex_set_bo(struct ilo_texture *tex, struct intel_bo *bo)
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static void
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tex_destroy(struct ilo_texture *tex)
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{
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if (tex->separate_s8)
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tex_destroy(tex->separate_s8);
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tex->bo->unreference(tex->bo);
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tex_free_slices(tex);
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FREE(tex);
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@@ -987,6 +1012,29 @@ tex_create(struct pipe_screen *screen,
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tex_set_bo(tex, bo);
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/* allocate separate stencil resource */
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if (layout.separate_stencil) {
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struct pipe_resource s8_templ = *layout.templ;
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struct pipe_resource *s8;
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/*
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* Unless PIPE_BIND_DEPTH_STENCIL is set, the resource may have other
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* tilings. But that should be fine since it will never be bound as the
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* stencil buffer, and our transfer code can handle all tilings.
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*/
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s8_templ.format = PIPE_FORMAT_S8_UINT;
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s8 = screen->resource_create(screen, &s8_templ);
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if (!s8) {
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tex_destroy(tex);
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return NULL;
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}
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tex->separate_s8 = ilo_texture(s8);
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assert(tex->separate_s8->bo_format == PIPE_FORMAT_S8_UINT);
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}
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return &tex->base;
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}
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@@ -78,6 +78,8 @@ struct ilo_texture {
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unsigned x;
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unsigned y;
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} *slice_offsets[PIPE_MAX_TEXTURE_LEVELS];
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struct ilo_texture *separate_s8;
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};
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static inline struct ilo_buffer *
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@@ -626,8 +626,9 @@ static bool
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init_dev(struct ilo_dev_info *dev, const struct intel_winsys_info *info)
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{
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dev->devid = info->devid;
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dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
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dev->has_llc = info->has_llc;
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dev->has_gen7_sol_reset = info->has_gen7_sol_reset;
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dev->has_address_swizzling = info->has_address_swizzling;
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/*
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* From the Sandy Bridge PRM, volume 4 part 2, page 18:
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@@ -42,6 +42,7 @@ enum ilo_transfer_map_method {
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/* use staging system buffer */
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ILO_TRANSFER_MAP_SW_CONVERT,
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ILO_TRANSFER_MAP_SW_ZS,
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};
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struct ilo_transfer {
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@@ -200,32 +201,42 @@ choose_transfer_method(struct ilo_context *ilo, struct ilo_transfer *xfer)
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}
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if (tex && !(usage & PIPE_TRANSFER_MAP_DIRECTLY)) {
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if (tex->separate_s8 || tex->bo_format == PIPE_FORMAT_S8_UINT)
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xfer->method = ILO_TRANSFER_MAP_SW_ZS;
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/* need to convert on-the-fly */
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if (tex->bo_format != tex->base.format)
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else if (tex->bo_format != tex->base.format)
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xfer->method = ILO_TRANSFER_MAP_SW_CONVERT;
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}
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return true;
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}
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static void
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tex_get_box_origin(const struct ilo_texture *tex,
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unsigned level, unsigned slice,
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const struct pipe_box *box,
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unsigned *mem_x, unsigned *mem_y)
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{
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unsigned x, y;
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x = tex->slice_offsets[level][slice + box->z].x + box->x;
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y = tex->slice_offsets[level][slice + box->z].y + box->y;
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assert(x % tex->block_width == 0 && y % tex->block_height == 0);
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*mem_x = x / tex->block_width * tex->bo_cpp;
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*mem_y = y / tex->block_height;
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}
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static unsigned
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tex_get_box_offset(const struct ilo_texture *tex, unsigned level,
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const struct pipe_box *box)
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{
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unsigned x, y;
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unsigned mem_x, mem_y;
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x = tex->slice_offsets[level][box->z].x;
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y = tex->slice_offsets[level][box->z].y;
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tex_get_box_origin(tex, level, 0, box, &mem_x, &mem_y);
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x += box->x;
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y += box->y;
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/* in blocks */
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assert(x % tex->block_width == 0 && y % tex->block_height == 0);
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x /= tex->block_width;
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y /= tex->block_height;
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return y * tex->bo_stride + x * tex->bo_cpp;
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return mem_y * tex->bo_stride + mem_x;
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}
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static unsigned
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@@ -254,6 +265,394 @@ tex_get_slice_stride(const struct ilo_texture *tex, unsigned level)
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return (qpitch / tex->block_height) * tex->bo_stride;
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}
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static unsigned
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tex_tile_x_swizzle(unsigned addr)
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{
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/*
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* From the Ivy Bridge PRM, volume 1 part 2, page 24:
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*
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* "As shown in the tiling algorithm, the new address bit[6] should be:
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*
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* Address bit[6] <= TiledAddr bit[6] XOR
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* TiledAddr bit[9] XOR
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* TiledAddr bit[10]"
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*/
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return addr ^ (((addr >> 3) ^ (addr >> 4)) & 0x40);
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}
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static unsigned
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tex_tile_y_swizzle(unsigned addr)
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{
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/*
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* From the Ivy Bridge PRM, volume 1 part 2, page 24:
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*
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* "As shown in the tiling algorithm, The new address bit[6] becomes:
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*
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* Address bit[6] <= TiledAddr bit[6] XOR
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* TiledAddr bit[9]"
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*/
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return addr ^ ((addr >> 3) & 0x40);
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}
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static unsigned
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tex_tile_x_offset(unsigned mem_x, unsigned mem_y,
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unsigned tiles_per_row, bool swizzle)
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{
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/*
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* From the Sandy Bridge PRM, volume 1 part 2, page 21, we know that a
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* X-major tile has 8 rows and 32 OWord columns (512 bytes). Tiles in the
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* tiled region are numbered in row-major order, starting from zero. The
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* tile number can thus be calculated as follows:
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*
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* tile = (mem_y / 8) * tiles_per_row + (mem_x / 512)
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*
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* OWords in that tile are also numbered in row-major order, starting from
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* zero. The OWord number can thus be calculated as follows:
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*
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* oword = (mem_y % 8) * 32 + ((mem_x % 512) / 16)
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*
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* and the tiled offset is
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*
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* offset = tile * 4096 + oword * 16 + (mem_x % 16)
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* = tile * 4096 + (mem_y % 8) * 512 + (mem_x % 512)
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*/
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unsigned tile, offset;
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tile = (mem_y >> 3) * tiles_per_row + (mem_x >> 9);
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offset = tile << 12 | (mem_y & 0x7) << 9 | (mem_x & 0x1ff);
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return (swizzle) ? tex_tile_x_swizzle(offset) : offset;
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}
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static unsigned
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tex_tile_y_offset(unsigned mem_x, unsigned mem_y,
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unsigned tiles_per_row, bool swizzle)
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{
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/*
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* From the Sandy Bridge PRM, volume 1 part 2, page 22, we know that a
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* Y-major tile has 32 rows and 8 OWord columns (128 bytes). Tiles in the
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* tiled region are numbered in row-major order, starting from zero. The
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* tile number can thus be calculated as follows:
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*
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* tile = (mem_y / 32) * tiles_per_row + (mem_x / 128)
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*
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* OWords in that tile are numbered in column-major order, starting from
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* zero. The OWord number can thus be calculated as follows:
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*
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* oword = ((mem_x % 128) / 16) * 32 + (mem_y % 32)
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*
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* and the tiled offset is
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*
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* offset = tile * 4096 + oword * 16 + (mem_x % 16)
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*/
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unsigned tile, oword, offset;
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tile = (mem_y >> 5) * tiles_per_row + (mem_x >> 7);
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oword = (mem_x & 0x70) << 1 | (mem_y & 0x1f);
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offset = tile << 12 | oword << 4 | (mem_x & 0xf);
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return (swizzle) ? tex_tile_y_swizzle(offset) : offset;
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}
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static unsigned
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tex_tile_w_offset(unsigned mem_x, unsigned mem_y,
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unsigned tiles_per_row, bool swizzle)
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{
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/*
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* From the Sandy Bridge PRM, volume 1 part 2, page 23, we know that a
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* W-major tile has 8 8x8-block rows and 8 8x8-block columns. Tiles in the
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* tiled region are numbered in row-major order, starting from zero. The
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* tile number can thus be calculated as follows:
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*
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* tile = (mem_y / 64) * tiles_per_row + (mem_x / 64)
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*
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* 8x8-blocks in that tile are numbered in column-major order, starting
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* from zero. The 8x8-block number can thus be calculated as follows:
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*
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* blk8 = ((mem_x % 64) / 8) * 8 + ((mem_y % 64) / 8)
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*
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* Each 8x8-block is divided into 4 4x4-blocks, in row-major order. Each
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* 4x4-block is further divided into 4 2x2-blocks, also in row-major order.
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* We have
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*
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* blk4 = (((mem_y % 64) / 4) & 1) * 2 + (((mem_x % 64) / 4) & 1)
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* blk2 = (((mem_y % 64) / 2) & 1) * 2 + (((mem_x % 64) / 2) & 1)
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* blk1 = (((mem_y % 64) ) & 1) * 2 + (((mem_x % 64) ) & 1)
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*
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* and the tiled offset is
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*
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* offset = tile * 4096 + blk8 * 64 + blk4 * 16 + blk2 * 4 + blk1
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*/
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unsigned tile, blk8, blk4, blk2, blk1, offset;
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tile = (mem_y >> 6) * tiles_per_row + (mem_x >> 6);
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blk8 = ((mem_x >> 3) & 0x7) << 3 | ((mem_y >> 3) & 0x7);
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blk4 = ((mem_y >> 2) & 0x1) << 1 | ((mem_x >> 2) & 0x1);
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blk2 = ((mem_y >> 1) & 0x1) << 1 | ((mem_x >> 1) & 0x1);
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blk1 = ((mem_y ) & 0x1) << 1 | ((mem_x ) & 0x1);
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offset = tile << 12 | blk8 << 6 | blk4 << 4 | blk2 << 2 | blk1;
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return (swizzle) ? tex_tile_y_swizzle(offset) : offset;
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}
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static unsigned
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tex_tile_none_offset(unsigned mem_x, unsigned mem_y,
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unsigned tiles_per_row, bool swizzle)
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{
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return mem_y * tiles_per_row + mem_x;
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}
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typedef unsigned (*tex_tile_offset_func)(unsigned mem_x, unsigned mem_y,
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unsigned tiles_per_row,
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bool swizzle);
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static tex_tile_offset_func
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tex_tile_choose_offset_func(const struct ilo_texture *tex,
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unsigned *tiles_per_row)
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{
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switch (tex->tiling) {
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case INTEL_TILING_X:
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*tiles_per_row = tex->bo_stride / 512;
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return tex_tile_x_offset;
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case INTEL_TILING_Y:
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*tiles_per_row = tex->bo_stride / 128;
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return tex_tile_y_offset;
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case INTEL_TILING_NONE:
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default:
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/* W-tiling */
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if (tex->bo_format == PIPE_FORMAT_S8_UINT) {
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*tiles_per_row = tex->bo_stride / 64;
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return tex_tile_w_offset;
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}
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else {
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*tiles_per_row = tex->bo_stride;
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return tex_tile_none_offset;
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}
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}
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}
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static void
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tex_staging_sys_zs_read(struct ilo_context *ilo,
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struct ilo_texture *tex,
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const struct ilo_transfer *xfer)
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{
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const bool swizzle = ilo->dev->has_address_swizzling;
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const struct pipe_box *box = &xfer->base.box;
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const uint8_t *src = tex->bo->get_virtual(tex->bo);
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tex_tile_offset_func tile_offset;
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unsigned tiles_per_row;
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int slice;
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tile_offset = tex_tile_choose_offset_func(tex, &tiles_per_row);
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assert(tex->block_width == 1 && tex->block_height == 1);
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if (tex->separate_s8) {
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struct ilo_texture *s8_tex = tex->separate_s8;
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const uint8_t *s8_src = s8_tex->bo->get_virtual(s8_tex->bo);
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tex_tile_offset_func s8_tile_offset;
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unsigned s8_tiles_per_row;
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int dst_cpp, dst_s8_pos, src_cpp_used;
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s8_tile_offset = tex_tile_choose_offset_func(s8_tex, &s8_tiles_per_row);
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if (tex->base.format == PIPE_FORMAT_Z24_UNORM_S8_UINT) {
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assert(tex->bo_format == PIPE_FORMAT_Z24X8_UNORM);
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dst_cpp = 4;
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dst_s8_pos = 3;
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src_cpp_used = 3;
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}
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else {
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assert(tex->base.format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT);
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assert(tex->bo_format == PIPE_FORMAT_Z32_FLOAT);
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dst_cpp = 8;
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dst_s8_pos = 4;
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src_cpp_used = 4;
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}
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for (slice = 0; slice < box->depth; slice++) {
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unsigned mem_x, mem_y, s8_mem_x, s8_mem_y;
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uint8_t *dst;
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int i, j;
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tex_get_box_origin(tex, xfer->base.level, slice,
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box, &mem_x, &mem_y);
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tex_get_box_origin(s8_tex, xfer->base.level, slice,
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box, &s8_mem_x, &s8_mem_y);
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dst = xfer->staging_sys + xfer->base.layer_stride * slice;
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for (i = 0; i < box->height; i++) {
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unsigned x = mem_x, s8_x = s8_mem_x;
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uint8_t *d = dst;
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for (j = 0; j < box->width; j++) {
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const unsigned offset =
|
||||
tile_offset(x, mem_y, tiles_per_row, swizzle);
|
||||
const unsigned s8_offset =
|
||||
s8_tile_offset(s8_x, s8_mem_y, s8_tiles_per_row, swizzle);
|
||||
|
||||
memcpy(d, src + offset, src_cpp_used);
|
||||
d[dst_s8_pos] = s8_src[s8_offset];
|
||||
|
||||
d += dst_cpp;
|
||||
x += tex->bo_cpp;
|
||||
s8_x++;
|
||||
}
|
||||
|
||||
dst += xfer->base.stride;
|
||||
mem_y++;
|
||||
s8_mem_y++;
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
assert(tex->bo_format == PIPE_FORMAT_S8_UINT);
|
||||
|
||||
for (slice = 0; slice < box->depth; slice++) {
|
||||
unsigned mem_x, mem_y;
|
||||
uint8_t *dst;
|
||||
int i, j;
|
||||
|
||||
tex_get_box_origin(tex, xfer->base.level, slice,
|
||||
box, &mem_x, &mem_y);
|
||||
|
||||
dst = xfer->staging_sys + xfer->base.layer_stride * slice;
|
||||
|
||||
for (i = 0; i < box->height; i++) {
|
||||
unsigned x = mem_x;
|
||||
uint8_t *d = dst;
|
||||
|
||||
for (j = 0; j < box->width; j++) {
|
||||
const unsigned offset =
|
||||
tile_offset(x, mem_y, tiles_per_row, swizzle);
|
||||
|
||||
*d = src[offset];
|
||||
|
||||
d++;
|
||||
x++;
|
||||
}
|
||||
|
||||
dst += xfer->base.stride;
|
||||
mem_y++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
tex_staging_sys_zs_write(struct ilo_context *ilo,
|
||||
struct ilo_texture *tex,
|
||||
const struct ilo_transfer *xfer)
|
||||
{
|
||||
const bool swizzle = ilo->dev->has_address_swizzling;
|
||||
const struct pipe_box *box = &xfer->base.box;
|
||||
uint8_t *dst = tex->bo->get_virtual(tex->bo);
|
||||
tex_tile_offset_func tile_offset;
|
||||
unsigned tiles_per_row;
|
||||
int slice;
|
||||
|
||||
tile_offset = tex_tile_choose_offset_func(tex, &tiles_per_row);
|
||||
|
||||
assert(tex->block_width == 1 && tex->block_height == 1);
|
||||
|
||||
if (tex->separate_s8) {
|
||||
struct ilo_texture *s8_tex = tex->separate_s8;
|
||||
uint8_t *s8_dst = s8_tex->bo->get_virtual(s8_tex->bo);
|
||||
tex_tile_offset_func s8_tile_offset;
|
||||
unsigned s8_tiles_per_row;
|
||||
int src_cpp, src_s8_pos, dst_cpp_used;
|
||||
|
||||
s8_tile_offset = tex_tile_choose_offset_func(s8_tex, &s8_tiles_per_row);
|
||||
|
||||
if (tex->base.format == PIPE_FORMAT_Z24_UNORM_S8_UINT) {
|
||||
assert(tex->bo_format == PIPE_FORMAT_Z24X8_UNORM);
|
||||
|
||||
src_cpp = 4;
|
||||
src_s8_pos = 3;
|
||||
dst_cpp_used = 3;
|
||||
}
|
||||
else {
|
||||
assert(tex->base.format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT);
|
||||
assert(tex->bo_format == PIPE_FORMAT_Z32_FLOAT);
|
||||
|
||||
src_cpp = 8;
|
||||
src_s8_pos = 4;
|
||||
dst_cpp_used = 4;
|
||||
}
|
||||
|
||||
for (slice = 0; slice < box->depth; slice++) {
|
||||
unsigned mem_x, mem_y, s8_mem_x, s8_mem_y;
|
||||
const uint8_t *src;
|
||||
int i, j;
|
||||
|
||||
tex_get_box_origin(tex, xfer->base.level, slice,
|
||||
box, &mem_x, &mem_y);
|
||||
tex_get_box_origin(s8_tex, xfer->base.level, slice,
|
||||
box, &s8_mem_x, &s8_mem_y);
|
||||
|
||||
src = xfer->staging_sys + xfer->base.layer_stride * slice;
|
||||
|
||||
for (i = 0; i < box->height; i++) {
|
||||
unsigned x = mem_x, s8_x = s8_mem_x;
|
||||
const uint8_t *s = src;
|
||||
|
||||
for (j = 0; j < box->width; j++) {
|
||||
const unsigned offset =
|
||||
tile_offset(x, mem_y, tiles_per_row, swizzle);
|
||||
const unsigned s8_offset =
|
||||
s8_tile_offset(s8_x, s8_mem_y, s8_tiles_per_row, swizzle);
|
||||
|
||||
memcpy(dst + offset, s, dst_cpp_used);
|
||||
s8_dst[s8_offset] = s[src_s8_pos];
|
||||
|
||||
s += src_cpp;
|
||||
x += tex->bo_cpp;
|
||||
s8_x++;
|
||||
}
|
||||
|
||||
src += xfer->base.stride;
|
||||
mem_y++;
|
||||
s8_mem_y++;
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
assert(tex->bo_format == PIPE_FORMAT_S8_UINT);
|
||||
|
||||
for (slice = 0; slice < box->depth; slice++) {
|
||||
unsigned mem_x, mem_y;
|
||||
const uint8_t *src;
|
||||
int i, j;
|
||||
|
||||
tex_get_box_origin(tex, xfer->base.level, slice,
|
||||
box, &mem_x, &mem_y);
|
||||
|
||||
src = xfer->staging_sys + xfer->base.layer_stride * slice;
|
||||
|
||||
for (i = 0; i < box->height; i++) {
|
||||
unsigned x = mem_x;
|
||||
const uint8_t *s = src;
|
||||
|
||||
for (j = 0; j < box->width; j++) {
|
||||
const unsigned offset =
|
||||
tile_offset(x, mem_y, tiles_per_row, swizzle);
|
||||
|
||||
dst[offset] = *s;
|
||||
|
||||
s++;
|
||||
x++;
|
||||
}
|
||||
|
||||
src += xfer->base.stride;
|
||||
mem_y++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
tex_staging_sys_convert_write(struct ilo_context *ilo,
|
||||
struct ilo_texture *tex,
|
||||
@@ -302,39 +701,75 @@ tex_staging_sys_convert_write(struct ilo_context *ilo,
|
||||
}
|
||||
}
|
||||
|
||||
static bool
|
||||
tex_staging_sys_map_bo(const struct ilo_context *ilo,
|
||||
const struct ilo_texture *tex,
|
||||
bool for_read_back, bool linear_view)
|
||||
{
|
||||
const bool prefer_cpu = (ilo->dev->has_llc || for_read_back);
|
||||
int err;
|
||||
|
||||
if (prefer_cpu && (tex->tiling == INTEL_TILING_NONE || !linear_view))
|
||||
err = tex->bo->map(tex->bo, !for_read_back);
|
||||
else
|
||||
err = tex->bo->map_gtt(tex->bo);
|
||||
|
||||
if (!tex->separate_s8)
|
||||
return !err;
|
||||
|
||||
err = tex->separate_s8->bo->map(tex->separate_s8->bo, !for_read_back);
|
||||
if (err)
|
||||
tex->bo->unmap(tex->bo);
|
||||
|
||||
return !err;
|
||||
}
|
||||
|
||||
static void
|
||||
tex_staging_sys_unmap_bo(const struct ilo_context *ilo,
|
||||
const struct ilo_texture *tex)
|
||||
{
|
||||
if (tex->separate_s8)
|
||||
tex->separate_s8->bo->unmap(tex->separate_s8->bo);
|
||||
|
||||
tex->bo->unmap(tex->bo);
|
||||
}
|
||||
|
||||
static void
|
||||
tex_staging_sys_unmap(struct ilo_context *ilo,
|
||||
struct ilo_texture *tex,
|
||||
struct ilo_transfer *xfer)
|
||||
{
|
||||
int err;
|
||||
bool success;
|
||||
|
||||
if (!(xfer->base.usage & PIPE_TRANSFER_WRITE)) {
|
||||
FREE(xfer->staging_sys);
|
||||
return;
|
||||
}
|
||||
|
||||
if (tex->tiling == INTEL_TILING_NONE && ilo->dev->has_llc)
|
||||
err = tex->bo->map(tex->bo, true);
|
||||
else
|
||||
err = tex->bo->map_gtt(tex->bo);
|
||||
|
||||
if (err) {
|
||||
ilo_err("failed to map resource for moving staging data\n");
|
||||
FREE(xfer->staging_sys);
|
||||
return;
|
||||
}
|
||||
|
||||
switch (xfer->method) {
|
||||
case ILO_TRANSFER_MAP_SW_CONVERT:
|
||||
tex_staging_sys_convert_write(ilo, tex, xfer);
|
||||
success = tex_staging_sys_map_bo(ilo, tex, false, true);
|
||||
if (success) {
|
||||
tex_staging_sys_convert_write(ilo, tex, xfer);
|
||||
tex_staging_sys_unmap_bo(ilo, tex);
|
||||
}
|
||||
break;
|
||||
case ILO_TRANSFER_MAP_SW_ZS:
|
||||
success = tex_staging_sys_map_bo(ilo, tex, false, false);
|
||||
if (success) {
|
||||
tex_staging_sys_zs_write(ilo, tex, xfer);
|
||||
tex_staging_sys_unmap_bo(ilo, tex);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
assert(!"unknown mapping method");
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
|
||||
tex->bo->unmap(tex->bo);
|
||||
if (!success)
|
||||
ilo_err("failed to map resource for moving staging data\n");
|
||||
|
||||
FREE(xfer->staging_sys);
|
||||
}
|
||||
|
||||
@@ -347,7 +782,7 @@ tex_staging_sys_map(struct ilo_context *ilo,
|
||||
const size_t stride = util_format_get_stride(tex->base.format, box->width);
|
||||
const size_t size =
|
||||
util_format_get_2d_size(tex->base.format, stride, box->height);
|
||||
bool read_back = false;
|
||||
bool read_back = false, success;
|
||||
|
||||
xfer->staging_sys = MALLOC(size * box->depth);
|
||||
if (!xfer->staging_sys)
|
||||
@@ -372,8 +807,25 @@ tex_staging_sys_map(struct ilo_context *ilo,
|
||||
if (!read_back)
|
||||
return true;
|
||||
|
||||
/* TODO */
|
||||
return false;
|
||||
switch (xfer->method) {
|
||||
case ILO_TRANSFER_MAP_SW_CONVERT:
|
||||
assert(!"no on-the-fly format conversion for mapping");
|
||||
success = false;
|
||||
break;
|
||||
case ILO_TRANSFER_MAP_SW_ZS:
|
||||
success = tex_staging_sys_map_bo(ilo, tex, true, false);
|
||||
if (success) {
|
||||
tex_staging_sys_zs_read(ilo, tex, xfer);
|
||||
tex_staging_sys_unmap_bo(ilo, tex);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
assert(!"unknown mapping method");
|
||||
success = false;
|
||||
break;
|
||||
}
|
||||
|
||||
return success;
|
||||
}
|
||||
|
||||
static void
|
||||
@@ -423,6 +875,7 @@ tex_map(struct ilo_context *ilo, struct ilo_transfer *xfer)
|
||||
success = tex_direct_map(ilo, tex, xfer);
|
||||
break;
|
||||
case ILO_TRANSFER_MAP_SW_CONVERT:
|
||||
case ILO_TRANSFER_MAP_SW_ZS:
|
||||
success = tex_staging_sys_map(ilo, tex, xfer);
|
||||
break;
|
||||
default:
|
||||
@@ -446,6 +899,7 @@ tex_unmap(struct ilo_context *ilo, struct ilo_transfer *xfer)
|
||||
tex_direct_unmap(ilo, tex, xfer);
|
||||
break;
|
||||
case ILO_TRANSFER_MAP_SW_CONVERT:
|
||||
case ILO_TRANSFER_MAP_SW_ZS:
|
||||
tex_staging_sys_unmap(ilo, tex, xfer);
|
||||
break;
|
||||
default:
|
||||
|
||||
Reference in New Issue
Block a user